1 /* SPDX-License-Identifier: GPL-2.0-only */
2 #ifndef _ASM_X86_APIC_H
3 #define _ASM_X86_APIC_H
5 #include <linux/cpumask.h>
7 #include <asm/alternative.h>
8 #include <asm/cpufeature.h>
9 #include <asm/apicdef.h>
10 #include <linux/atomic.h>
11 #include <asm/fixmap.h>
12 #include <asm/mpspec.h>
14 #include <asm/hardirq.h>
16 #define ARCH_APICTIMER_STOPS_ON_C3 1
22 #define APIC_VERBOSE 1
25 /* Macros for apic_extnmi which controls external NMI masking */
26 #define APIC_EXTNMI_BSP 0 /* Default */
27 #define APIC_EXTNMI_ALL 1
28 #define APIC_EXTNMI_NONE 2
31 * Define the default level of output to be very little
32 * This can be turned up by using apic=verbose for more
33 * information and apic=debug for _lots_ of information.
34 * apic_verbosity is defined in apic.c
36 #define apic_printk(v, s, a...) do { \
37 if ((v) <= apic_verbosity) \
42 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
43 extern void x86_32_probe_apic(void);
45 static inline void x86_32_probe_apic(void) { }
48 #ifdef CONFIG_X86_LOCAL_APIC
50 extern int apic_verbosity;
51 extern int local_apic_timer_c2_ok;
53 extern bool apic_is_disabled;
54 extern unsigned int lapic_timer_period;
56 extern int cpuid_to_apicid[];
58 extern enum apic_intr_mode_id apic_intr_mode;
59 enum apic_intr_mode_id {
62 APIC_VIRTUAL_WIRE_NO_CONFIG,
64 APIC_SYMMETRIC_IO_NO_ROUTING
68 * With 82489DX we can't rely on apic feature bit
69 * retrieved via cpuid but still have to deal with
70 * such an apic chip so we assume that SMP configuration
71 * is found from MP table (64bit case uses ACPI mostly
72 * which set smp presence flag as well so we are safe
73 * to use this helper too).
75 static inline bool apic_from_smp_config(void)
77 return smp_found_config && !apic_is_disabled;
81 * Basic functions accessing APICs.
83 #ifdef CONFIG_PARAVIRT
84 #include <asm/paravirt.h>
87 static inline void native_apic_mem_write(u32 reg, u32 v)
89 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
91 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP,
92 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
93 ASM_OUTPUT2("0" (v), "m" (*addr)));
96 static inline u32 native_apic_mem_read(u32 reg)
98 return *((volatile u32 *)(APIC_BASE + reg));
101 static inline void native_apic_mem_eoi(void)
103 native_apic_mem_write(APIC_EOI, APIC_EOI_ACK);
106 extern void native_apic_icr_write(u32 low, u32 id);
107 extern u64 native_apic_icr_read(void);
109 static inline bool apic_is_x2apic_enabled(void)
113 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr))
115 return msr & X2APIC_ENABLE;
118 extern void enable_IR_x2apic(void);
120 extern int get_physical_broadcast(void);
122 extern int lapic_get_maxlvt(void);
123 extern void clear_local_APIC(void);
124 extern void disconnect_bsp_APIC(int virt_wire_setup);
125 extern void disable_local_APIC(void);
126 extern void apic_soft_disable(void);
127 extern void lapic_shutdown(void);
128 extern void sync_Arb_IDs(void);
129 extern void init_bsp_APIC(void);
130 extern void apic_intr_mode_select(void);
131 extern void apic_intr_mode_init(void);
132 extern void init_apic_mappings(void);
133 void register_lapic_address(unsigned long address);
134 extern void setup_boot_APIC_clock(void);
135 extern void setup_secondary_APIC_clock(void);
136 extern void lapic_update_tsc_freq(void);
139 static inline bool apic_force_enable(unsigned long addr)
144 extern bool apic_force_enable(unsigned long addr);
147 extern void apic_ap_setup(void);
150 * On 32bit this is mach-xxx local
153 extern int apic_is_clustered_box(void);
155 static inline int apic_is_clustered_box(void)
161 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
162 extern void lapic_assign_system_vectors(void);
163 extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace);
164 extern void lapic_update_legacy_vectors(void);
165 extern void lapic_online(void);
166 extern void lapic_offline(void);
167 extern bool apic_needs_pit(void);
169 extern void apic_send_IPI_allbutself(unsigned int vector);
171 #else /* !CONFIG_X86_LOCAL_APIC */
172 static inline void lapic_shutdown(void) { }
173 #define local_apic_timer_c2_ok 1
174 static inline void init_apic_mappings(void) { }
175 static inline void disable_local_APIC(void) { }
176 # define setup_boot_APIC_clock x86_init_noop
177 # define setup_secondary_APIC_clock x86_init_noop
178 static inline void lapic_update_tsc_freq(void) { }
179 static inline void init_bsp_APIC(void) { }
180 static inline void apic_intr_mode_select(void) { }
181 static inline void apic_intr_mode_init(void) { }
182 static inline void lapic_assign_system_vectors(void) { }
183 static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { }
184 static inline bool apic_needs_pit(void) { return true; }
185 #endif /* !CONFIG_X86_LOCAL_APIC */
187 #ifdef CONFIG_X86_X2APIC
188 static inline void native_apic_msr_write(u32 reg, u32 v)
190 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
194 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
197 static inline void native_apic_msr_eoi(void)
199 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
202 static inline u32 native_apic_msr_read(u32 reg)
209 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
213 static inline void native_x2apic_icr_write(u32 low, u32 id)
215 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
218 static inline u64 native_x2apic_icr_read(void)
222 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
226 extern int x2apic_mode;
227 extern int x2apic_phys;
228 extern void __init x2apic_set_max_apicid(u32 apicid);
229 extern void x2apic_setup(void);
230 static inline int x2apic_enabled(void)
232 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled();
235 #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC))
236 #else /* !CONFIG_X86_X2APIC */
237 static inline void x2apic_setup(void) { }
238 static inline int x2apic_enabled(void) { return 0; }
239 static inline u32 native_apic_msr_read(u32 reg) { BUG(); }
240 #define x2apic_mode (0)
241 #define x2apic_supported() (0)
242 #endif /* !CONFIG_X86_X2APIC */
243 extern void __init check_x2apic(void);
248 * Copyright 2004 James Cleverdon, IBM.
250 * Generic APIC sub-arch data struct.
252 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
253 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
257 /* Hotpath functions first */
259 void (*native_eoi)(void);
260 void (*write)(u32 reg, u32 v);
261 u32 (*read)(u32 reg);
263 /* IPI related functions */
264 void (*wait_icr_idle)(void);
265 u32 (*safe_wait_icr_idle)(void);
267 void (*send_IPI)(int cpu, int vector);
268 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
269 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec);
270 void (*send_IPI_allbutself)(int vector);
271 void (*send_IPI_all)(int vector);
272 void (*send_IPI_self)(int vector);
274 enum apic_delivery_modes delivery_mode;
277 dest_mode_logical : 1,
278 x2apic_set_max_apicid : 1;
280 u32 (*calc_dest_apicid)(unsigned int cpu);
282 /* ICR related functions */
283 u64 (*icr_read)(void);
284 void (*icr_write)(u32 low, u32 high);
286 /* The limit of the APIC ID space. */
289 /* Probe, setup and smpboot functions */
291 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
292 bool (*apic_id_registered)(void);
294 bool (*check_apicid_used)(physid_mask_t *map, int apicid);
295 void (*init_apic_ldr)(void);
296 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
297 int (*cpu_present_to_apicid)(int mps_cpu);
298 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
300 u32 (*get_apic_id)(unsigned long x);
301 u32 (*set_apic_id)(unsigned int id);
303 /* wakeup_secondary_cpu */
304 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
305 /* wakeup secondary CPU using 64-bit wakeup point */
306 int (*wakeup_secondary_cpu_64)(int apicid, unsigned long start_eip);
311 struct apic_override {
313 void (*native_eoi)(void);
314 void (*write)(u32 reg, u32 v);
315 u32 (*read)(u32 reg);
316 void (*send_IPI)(int cpu, int vector);
317 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
318 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec);
319 void (*send_IPI_allbutself)(int vector);
320 void (*send_IPI_all)(int vector);
321 void (*send_IPI_self)(int vector);
322 u64 (*icr_read)(void);
323 void (*icr_write)(u32 low, u32 high);
324 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
325 int (*wakeup_secondary_cpu_64)(int apicid, unsigned long start_eip);
329 * Pointer to the local APIC driver in use on this system (there's
330 * always just one such driver in use - the kernel decides via an
331 * early probing process which one it picks - and then sticks to it):
333 extern struct apic *apic;
336 * APIC drivers are probed based on how they are listed in the .apicdrivers
337 * section. So the order is important and enforced by the ordering
338 * of different apic driver files in the Makefile.
340 * For the files having two apic drivers, we use apic_drivers()
341 * to enforce the order with in them.
343 #define apic_driver(sym) \
344 static const struct apic *__apicdrivers_##sym __used \
345 __aligned(sizeof(struct apic *)) \
346 __section(".apicdrivers") = { &sym }
348 #define apic_drivers(sym1, sym2) \
349 static struct apic *__apicdrivers_##sym1##sym2[2] __used \
350 __aligned(sizeof(struct apic *)) \
351 __section(".apicdrivers") = { &sym1, &sym2 }
353 extern struct apic *__apicdrivers[], *__apicdrivers_end[];
356 * APIC functionality to boot other CPUs - only used on SMP:
359 extern int lapic_can_unplug_cpu(void);
362 #ifdef CONFIG_X86_LOCAL_APIC
363 extern struct apic_override __x86_apic_override;
365 void __init apic_setup_apic_calls(void);
366 void __init apic_install_driver(struct apic *driver);
368 #define apic_update_callback(_callback, _fn) { \
369 __x86_apic_override._callback = _fn; \
370 apic->_callback = _fn; \
371 pr_info("APIC: %s() replaced with %ps()\n", #_callback, _fn); \
374 static __always_inline u32 apic_read(u32 reg)
376 return apic->read(reg);
379 static __always_inline void apic_write(u32 reg, u32 val)
381 apic->write(reg, val);
384 static __always_inline void apic_eoi(void)
389 static __always_inline void apic_native_eoi(void)
394 static __always_inline u64 apic_icr_read(void)
396 return apic->icr_read();
399 static __always_inline void apic_icr_write(u32 low, u32 high)
401 apic->icr_write(low, high);
404 static __always_inline void __apic_send_IPI(int cpu, int vector)
406 apic->send_IPI(cpu, vector);
409 static __always_inline void __apic_send_IPI_mask(const struct cpumask *mask, int vector)
411 apic->send_IPI_mask(mask, vector);
414 static __always_inline void __apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
416 apic->send_IPI_mask_allbutself(mask, vector);
419 static __always_inline void __apic_send_IPI_allbutself(int vector)
421 apic->send_IPI_allbutself(vector);
424 static __always_inline void __apic_send_IPI_all(int vector)
426 apic->send_IPI_all(vector);
429 static __always_inline void __apic_send_IPI_self(int vector)
431 apic->send_IPI_self(vector);
434 static __always_inline void apic_wait_icr_idle(void)
436 if (apic->wait_icr_idle)
437 apic->wait_icr_idle();
440 static __always_inline u32 safe_apic_wait_icr_idle(void)
442 return apic->safe_wait_icr_idle ? apic->safe_wait_icr_idle() : 0;
445 static __always_inline bool apic_id_valid(u32 apic_id)
447 return apic_id <= apic->max_apic_id;
450 #else /* CONFIG_X86_LOCAL_APIC */
452 static inline u32 apic_read(u32 reg) { return 0; }
453 static inline void apic_write(u32 reg, u32 val) { }
454 static inline void apic_eoi(void) { }
455 static inline u64 apic_icr_read(void) { return 0; }
456 static inline void apic_icr_write(u32 low, u32 high) { }
457 static inline void apic_wait_icr_idle(void) { }
458 static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
459 static inline void apic_set_eoi_cb(void (*eoi)(void)) {}
460 static inline void apic_native_eoi(void) { WARN_ON_ONCE(1); }
461 static inline void apic_setup_apic_calls(void) { }
463 #define apic_update_callback(_callback, _fn) do { } while (0)
465 #endif /* CONFIG_X86_LOCAL_APIC */
467 extern void apic_ack_irq(struct irq_data *data);
469 static inline bool lapic_vector_set_in_irr(unsigned int vector)
471 u32 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
473 return !!(irr & (1U << (vector % 32)));
476 static inline unsigned default_get_apic_id(unsigned long x)
478 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
480 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
481 return (x >> 24) & 0xFF;
483 return (x >> 24) & 0x0F;
487 * Warm reset vector position:
489 #define TRAMPOLINE_PHYS_LOW 0x467
490 #define TRAMPOLINE_PHYS_HIGH 0x469
492 extern void generic_bigsmp_probe(void);
494 #ifdef CONFIG_X86_LOCAL_APIC
498 extern struct apic apic_noop;
500 static inline unsigned int read_apic_id(void)
502 unsigned int reg = apic_read(APIC_ID);
504 return apic->get_apic_id(reg);
508 typedef int (*wakeup_cpu_handler)(int apicid, unsigned long start_eip);
509 extern int default_acpi_madt_oem_check(char *, char *);
510 extern void x86_64_probe_apic(void);
512 static inline int default_acpi_madt_oem_check(char *a, char *b) { return 0; }
513 static inline void x86_64_probe_apic(void) { }
516 extern int default_apic_id_valid(u32 apicid);
518 extern u32 apic_default_calc_apicid(unsigned int cpu);
519 extern u32 apic_flat_calc_apicid(unsigned int cpu);
521 extern bool default_check_apicid_used(physid_mask_t *map, int apicid);
522 extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap);
523 extern int default_cpu_present_to_apicid(int mps_cpu);
525 #else /* CONFIG_X86_LOCAL_APIC */
527 static inline unsigned int read_apic_id(void) { return 0; }
529 #endif /* !CONFIG_X86_LOCAL_APIC */
532 void apic_smt_update(void);
534 static inline void apic_smt_update(void) { }
540 extern void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg,
543 extern void ioapic_zap_locks(void);
545 #endif /* _ASM_X86_APIC_H */