1 /* SPDX-License-Identifier: GPL-2.0-only */
2 #ifndef _ASM_X86_APIC_H
3 #define _ASM_X86_APIC_H
5 #include <linux/cpumask.h>
6 #include <linux/static_call.h>
8 #include <asm/alternative.h>
9 #include <asm/cpufeature.h>
10 #include <asm/apicdef.h>
11 #include <linux/atomic.h>
12 #include <asm/fixmap.h>
13 #include <asm/mpspec.h>
15 #include <asm/hardirq.h>
17 #define ARCH_APICTIMER_STOPS_ON_C3 1
23 #define APIC_VERBOSE 1
26 /* Macros for apic_extnmi which controls external NMI masking */
27 #define APIC_EXTNMI_BSP 0 /* Default */
28 #define APIC_EXTNMI_ALL 1
29 #define APIC_EXTNMI_NONE 2
32 * Define the default level of output to be very little
33 * This can be turned up by using apic=verbose for more
34 * information and apic=debug for _lots_ of information.
35 * apic_verbosity is defined in apic.c
37 #define apic_printk(v, s, a...) do { \
38 if ((v) <= apic_verbosity) \
43 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
44 extern void x86_32_probe_apic(void);
46 static inline void x86_32_probe_apic(void) { }
49 extern u32 cpuid_to_apicid[];
51 #define CPU_ACPIID_INVALID U32_MAX
53 #ifdef CONFIG_X86_LOCAL_APIC
55 extern int apic_verbosity;
56 extern int local_apic_timer_c2_ok;
58 extern bool apic_is_disabled;
59 extern unsigned int lapic_timer_period;
61 extern enum apic_intr_mode_id apic_intr_mode;
62 enum apic_intr_mode_id {
65 APIC_VIRTUAL_WIRE_NO_CONFIG,
67 APIC_SYMMETRIC_IO_NO_ROUTING
71 * With 82489DX we can't rely on apic feature bit
72 * retrieved via cpuid but still have to deal with
73 * such an apic chip so we assume that SMP configuration
74 * is found from MP table (64bit case uses ACPI mostly
75 * which set smp presence flag as well so we are safe
76 * to use this helper too).
78 static inline bool apic_from_smp_config(void)
80 return smp_found_config && !apic_is_disabled;
84 * Basic functions accessing APICs.
86 #ifdef CONFIG_PARAVIRT
87 #include <asm/paravirt.h>
90 static inline void native_apic_mem_write(u32 reg, u32 v)
92 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
94 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP,
95 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
96 ASM_OUTPUT2("0" (v), "m" (*addr)));
99 static inline u32 native_apic_mem_read(u32 reg)
101 return *((volatile u32 *)(APIC_BASE + reg));
104 static inline void native_apic_mem_eoi(void)
106 native_apic_mem_write(APIC_EOI, APIC_EOI_ACK);
109 extern void native_apic_icr_write(u32 low, u32 id);
110 extern u64 native_apic_icr_read(void);
112 static inline bool apic_is_x2apic_enabled(void)
116 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr))
118 return msr & X2APIC_ENABLE;
121 extern void enable_IR_x2apic(void);
123 extern int get_physical_broadcast(void);
125 extern int lapic_get_maxlvt(void);
126 extern void clear_local_APIC(void);
127 extern void disconnect_bsp_APIC(int virt_wire_setup);
128 extern void disable_local_APIC(void);
129 extern void apic_soft_disable(void);
130 extern void lapic_shutdown(void);
131 extern void sync_Arb_IDs(void);
132 extern void init_bsp_APIC(void);
133 extern void apic_intr_mode_select(void);
134 extern void apic_intr_mode_init(void);
135 extern void init_apic_mappings(void);
136 void register_lapic_address(unsigned long address);
137 extern void setup_boot_APIC_clock(void);
138 extern void setup_secondary_APIC_clock(void);
139 extern void lapic_update_tsc_freq(void);
142 static inline bool apic_force_enable(unsigned long addr)
147 extern bool apic_force_enable(unsigned long addr);
150 extern void apic_ap_setup(void);
153 * On 32bit this is mach-xxx local
156 extern int apic_is_clustered_box(void);
158 static inline int apic_is_clustered_box(void)
164 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
165 extern void lapic_assign_system_vectors(void);
166 extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace);
167 extern void lapic_update_legacy_vectors(void);
168 extern void lapic_online(void);
169 extern void lapic_offline(void);
170 extern bool apic_needs_pit(void);
172 extern void apic_send_IPI_allbutself(unsigned int vector);
174 #else /* !CONFIG_X86_LOCAL_APIC */
175 static inline void lapic_shutdown(void) { }
176 #define local_apic_timer_c2_ok 1
177 static inline void init_apic_mappings(void) { }
178 static inline void disable_local_APIC(void) { }
179 # define setup_boot_APIC_clock x86_init_noop
180 # define setup_secondary_APIC_clock x86_init_noop
181 static inline void lapic_update_tsc_freq(void) { }
182 static inline void init_bsp_APIC(void) { }
183 static inline void apic_intr_mode_select(void) { }
184 static inline void apic_intr_mode_init(void) { }
185 static inline void lapic_assign_system_vectors(void) { }
186 static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { }
187 static inline bool apic_needs_pit(void) { return true; }
188 #endif /* !CONFIG_X86_LOCAL_APIC */
190 #ifdef CONFIG_X86_X2APIC
191 static inline void native_apic_msr_write(u32 reg, u32 v)
193 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
197 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
200 static inline void native_apic_msr_eoi(void)
202 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
205 static inline u32 native_apic_msr_read(u32 reg)
212 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
216 static inline void native_x2apic_icr_write(u32 low, u32 id)
218 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
221 static inline u64 native_x2apic_icr_read(void)
225 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
229 extern int x2apic_mode;
230 extern int x2apic_phys;
231 extern void __init x2apic_set_max_apicid(u32 apicid);
232 extern void x2apic_setup(void);
233 static inline int x2apic_enabled(void)
235 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled();
238 #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC))
239 #else /* !CONFIG_X86_X2APIC */
240 static inline void x2apic_setup(void) { }
241 static inline int x2apic_enabled(void) { return 0; }
242 static inline u32 native_apic_msr_read(u32 reg) { BUG(); }
243 #define x2apic_mode (0)
244 #define x2apic_supported() (0)
245 #endif /* !CONFIG_X86_X2APIC */
246 extern void __init check_x2apic(void);
251 * Copyright 2004 James Cleverdon, IBM.
253 * Generic APIC sub-arch data struct.
255 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
256 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
260 /* Hotpath functions first */
262 void (*native_eoi)(void);
263 void (*write)(u32 reg, u32 v);
264 u32 (*read)(u32 reg);
266 /* IPI related functions */
267 void (*wait_icr_idle)(void);
268 u32 (*safe_wait_icr_idle)(void);
270 void (*send_IPI)(int cpu, int vector);
271 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
272 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec);
273 void (*send_IPI_allbutself)(int vector);
274 void (*send_IPI_all)(int vector);
275 void (*send_IPI_self)(int vector);
278 dest_mode_logical : 1,
279 x2apic_set_max_apicid : 1,
280 nmi_to_offline_cpu : 1;
282 u32 (*calc_dest_apicid)(unsigned int cpu);
284 /* ICR related functions */
285 u64 (*icr_read)(void);
286 void (*icr_write)(u32 low, u32 high);
288 /* The limit of the APIC ID space. */
291 /* Probe, setup and smpboot functions */
293 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
295 void (*init_apic_ldr)(void);
296 u32 (*cpu_present_to_apicid)(int mps_cpu);
298 u32 (*get_apic_id)(u32 id);
300 /* wakeup_secondary_cpu */
301 int (*wakeup_secondary_cpu)(u32 apicid, unsigned long start_eip);
302 /* wakeup secondary CPU using 64-bit wakeup point */
303 int (*wakeup_secondary_cpu_64)(u32 apicid, unsigned long start_eip);
308 struct apic_override {
310 void (*native_eoi)(void);
311 void (*write)(u32 reg, u32 v);
312 u32 (*read)(u32 reg);
313 void (*send_IPI)(int cpu, int vector);
314 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
315 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec);
316 void (*send_IPI_allbutself)(int vector);
317 void (*send_IPI_all)(int vector);
318 void (*send_IPI_self)(int vector);
319 u64 (*icr_read)(void);
320 void (*icr_write)(u32 low, u32 high);
321 int (*wakeup_secondary_cpu)(u32 apicid, unsigned long start_eip);
322 int (*wakeup_secondary_cpu_64)(u32 apicid, unsigned long start_eip);
326 * Pointer to the local APIC driver in use on this system (there's
327 * always just one such driver in use - the kernel decides via an
328 * early probing process which one it picks - and then sticks to it):
330 extern struct apic *apic;
333 * APIC drivers are probed based on how they are listed in the .apicdrivers
334 * section. So the order is important and enforced by the ordering
335 * of different apic driver files in the Makefile.
337 * For the files having two apic drivers, we use apic_drivers()
338 * to enforce the order with in them.
340 #define apic_driver(sym) \
341 static const struct apic *__apicdrivers_##sym __used \
342 __aligned(sizeof(struct apic *)) \
343 __section(".apicdrivers") = { &sym }
345 #define apic_drivers(sym1, sym2) \
346 static struct apic *__apicdrivers_##sym1##sym2[2] __used \
347 __aligned(sizeof(struct apic *)) \
348 __section(".apicdrivers") = { &sym1, &sym2 }
350 extern struct apic *__apicdrivers[], *__apicdrivers_end[];
353 * APIC functionality to boot other CPUs - only used on SMP:
356 extern int lapic_can_unplug_cpu(void);
359 #ifdef CONFIG_X86_LOCAL_APIC
360 extern struct apic_override __x86_apic_override;
362 void __init apic_setup_apic_calls(void);
363 void __init apic_install_driver(struct apic *driver);
365 #define apic_update_callback(_callback, _fn) { \
366 __x86_apic_override._callback = _fn; \
367 apic->_callback = _fn; \
368 static_call_update(apic_call_##_callback, _fn); \
369 pr_info("APIC: %s() replaced with %ps()\n", #_callback, _fn); \
372 #define DECLARE_APIC_CALL(__cb) \
373 DECLARE_STATIC_CALL(apic_call_##__cb, *apic->__cb)
375 DECLARE_APIC_CALL(eoi);
376 DECLARE_APIC_CALL(native_eoi);
377 DECLARE_APIC_CALL(icr_read);
378 DECLARE_APIC_CALL(icr_write);
379 DECLARE_APIC_CALL(read);
380 DECLARE_APIC_CALL(send_IPI);
381 DECLARE_APIC_CALL(send_IPI_mask);
382 DECLARE_APIC_CALL(send_IPI_mask_allbutself);
383 DECLARE_APIC_CALL(send_IPI_allbutself);
384 DECLARE_APIC_CALL(send_IPI_all);
385 DECLARE_APIC_CALL(send_IPI_self);
386 DECLARE_APIC_CALL(wait_icr_idle);
387 DECLARE_APIC_CALL(wakeup_secondary_cpu);
388 DECLARE_APIC_CALL(wakeup_secondary_cpu_64);
389 DECLARE_APIC_CALL(write);
391 static __always_inline u32 apic_read(u32 reg)
393 return static_call(apic_call_read)(reg);
396 static __always_inline void apic_write(u32 reg, u32 val)
398 static_call(apic_call_write)(reg, val);
401 static __always_inline void apic_eoi(void)
403 static_call(apic_call_eoi)();
406 static __always_inline void apic_native_eoi(void)
408 static_call(apic_call_native_eoi)();
411 static __always_inline u64 apic_icr_read(void)
413 return static_call(apic_call_icr_read)();
416 static __always_inline void apic_icr_write(u32 low, u32 high)
418 static_call(apic_call_icr_write)(low, high);
421 static __always_inline void __apic_send_IPI(int cpu, int vector)
423 static_call(apic_call_send_IPI)(cpu, vector);
426 static __always_inline void __apic_send_IPI_mask(const struct cpumask *mask, int vector)
428 static_call_mod(apic_call_send_IPI_mask)(mask, vector);
431 static __always_inline void __apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
433 static_call(apic_call_send_IPI_mask_allbutself)(mask, vector);
436 static __always_inline void __apic_send_IPI_allbutself(int vector)
438 static_call(apic_call_send_IPI_allbutself)(vector);
441 static __always_inline void __apic_send_IPI_all(int vector)
443 static_call(apic_call_send_IPI_all)(vector);
446 static __always_inline void __apic_send_IPI_self(int vector)
448 static_call_mod(apic_call_send_IPI_self)(vector);
451 static __always_inline void apic_wait_icr_idle(void)
453 static_call_cond(apic_call_wait_icr_idle)();
456 static __always_inline u32 safe_apic_wait_icr_idle(void)
458 return apic->safe_wait_icr_idle ? apic->safe_wait_icr_idle() : 0;
461 static __always_inline bool apic_id_valid(u32 apic_id)
463 return apic_id <= apic->max_apic_id;
466 #else /* CONFIG_X86_LOCAL_APIC */
468 static inline u32 apic_read(u32 reg) { return 0; }
469 static inline void apic_write(u32 reg, u32 val) { }
470 static inline void apic_eoi(void) { }
471 static inline u64 apic_icr_read(void) { return 0; }
472 static inline void apic_icr_write(u32 low, u32 high) { }
473 static inline void apic_wait_icr_idle(void) { }
474 static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
475 static inline void apic_set_eoi_cb(void (*eoi)(void)) {}
476 static inline void apic_native_eoi(void) { WARN_ON_ONCE(1); }
477 static inline void apic_setup_apic_calls(void) { }
479 #define apic_update_callback(_callback, _fn) do { } while (0)
481 #endif /* CONFIG_X86_LOCAL_APIC */
483 extern void apic_ack_irq(struct irq_data *data);
485 static inline bool lapic_vector_set_in_irr(unsigned int vector)
487 u32 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
489 return !!(irr & (1U << (vector % 32)));
493 * Warm reset vector position:
495 #define TRAMPOLINE_PHYS_LOW 0x467
496 #define TRAMPOLINE_PHYS_HIGH 0x469
498 extern void generic_bigsmp_probe(void);
500 #ifdef CONFIG_X86_LOCAL_APIC
504 extern struct apic apic_noop;
506 static inline u32 read_apic_id(void)
508 u32 reg = apic_read(APIC_ID);
510 return apic->get_apic_id(reg);
514 typedef int (*wakeup_cpu_handler)(int apicid, unsigned long start_eip);
515 extern int default_acpi_madt_oem_check(char *, char *);
516 extern void x86_64_probe_apic(void);
518 static inline int default_acpi_madt_oem_check(char *a, char *b) { return 0; }
519 static inline void x86_64_probe_apic(void) { }
522 extern int default_apic_id_valid(u32 apicid);
524 extern u32 apic_default_calc_apicid(unsigned int cpu);
525 extern u32 apic_flat_calc_apicid(unsigned int cpu);
527 extern u32 default_cpu_present_to_apicid(int mps_cpu);
529 void apic_send_nmi_to_offline_cpu(unsigned int cpu);
531 #else /* CONFIG_X86_LOCAL_APIC */
533 static inline u32 read_apic_id(void) { return 0; }
535 #endif /* !CONFIG_X86_LOCAL_APIC */
538 void apic_smt_update(void);
540 static inline void apic_smt_update(void) { }
546 extern void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg,
549 extern void ioapic_zap_locks(void);
551 #endif /* _ASM_X86_APIC_H */