arch/x86/events/msr.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <linux/perf_event.h>
   3 #include <linux/sysfs.h>
   4 #include <linux/nospec.h>
   5 #include <asm/intel-family.h>
   6 #include "probe.h"
   7
   8 enum perf_msr_id {
   9         PERF_MSR_TSC                    = 0,
  10         PERF_MSR_APERF                  = 1,
  11         PERF_MSR_MPERF                  = 2,
  12         PERF_MSR_PPERF                  = 3,
  13         PERF_MSR_SMI                    = 4,
  14         PERF_MSR_PTSC                   = 5,
  15         PERF_MSR_IRPERF                 = 6,
  16         PERF_MSR_THERM                  = 7,
  17         PERF_MSR_EVENT_MAX,
  18 };
  19
  20 static bool test_aperfmperf(int idx, void *data)
  21 {
  22         return boot_cpu_has(X86_FEATURE_APERFMPERF);
  23 }
  24
  25 static bool test_ptsc(int idx, void *data)
  26 {
  27         return boot_cpu_has(X86_FEATURE_PTSC);
  28 }
  29
  30 static bool test_irperf(int idx, void *data)
  31 {
  32         return boot_cpu_has(X86_FEATURE_IRPERF);
  33 }
  34
  35 static bool test_therm_status(int idx, void *data)
  36 {
  37         return boot_cpu_has(X86_FEATURE_DTHERM);
  38 }
  39
  40 static bool test_intel(int idx, void *data)
  41 {
  42         if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
  43             boot_cpu_data.x86 != 6)
  44                 return false;
  45
  46         switch (boot_cpu_data.x86_model) {
  47         case INTEL_FAM6_NEHALEM:
  48         case INTEL_FAM6_NEHALEM_G:
  49         case INTEL_FAM6_NEHALEM_EP:
  50         case INTEL_FAM6_NEHALEM_EX:
  51
  52         case INTEL_FAM6_WESTMERE:
  53         case INTEL_FAM6_WESTMERE_EP:
  54         case INTEL_FAM6_WESTMERE_EX:
  55
  56         case INTEL_FAM6_SANDYBRIDGE:
  57         case INTEL_FAM6_SANDYBRIDGE_X:
  58
  59         case INTEL_FAM6_IVYBRIDGE:
  60         case INTEL_FAM6_IVYBRIDGE_X:
  61
  62         case INTEL_FAM6_HASWELL:
  63         case INTEL_FAM6_HASWELL_X:
  64         case INTEL_FAM6_HASWELL_L:
  65         case INTEL_FAM6_HASWELL_G:
  66
  67         case INTEL_FAM6_BROADWELL:
  68         case INTEL_FAM6_BROADWELL_D:
  69         case INTEL_FAM6_BROADWELL_G:
  70         case INTEL_FAM6_BROADWELL_X:
  71
  72         case INTEL_FAM6_ATOM_SILVERMONT:
  73         case INTEL_FAM6_ATOM_SILVERMONT_D:
  74         case INTEL_FAM6_ATOM_AIRMONT:
  75
  76         case INTEL_FAM6_ATOM_GOLDMONT:
  77         case INTEL_FAM6_ATOM_GOLDMONT_D:
  78
  79         case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
  80
  81         case INTEL_FAM6_XEON_PHI_KNL:
  82         case INTEL_FAM6_XEON_PHI_KNM:
  83                 if (idx == PERF_MSR_SMI)
  84                         return true;
  85                 break;
  86
  87         case INTEL_FAM6_SKYLAKE_L:
  88         case INTEL_FAM6_SKYLAKE:
  89         case INTEL_FAM6_SKYLAKE_X:
  90         case INTEL_FAM6_KABYLAKE_L:
  91         case INTEL_FAM6_KABYLAKE:
  92         case INTEL_FAM6_COMETLAKE_L:
  93         case INTEL_FAM6_COMETLAKE:
  94         case INTEL_FAM6_ICELAKE_L:
  95         case INTEL_FAM6_ICELAKE:
  96         case INTEL_FAM6_ICELAKE_X:
  97         case INTEL_FAM6_ICELAKE_D:
  98                 if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
  99                         return true;
 100                 break;
 101         }
 102
 103         return false;
 104 }
 105
 106 PMU_EVENT_ATTR_STRING(tsc,                              attr_tsc,               "event=0x00"    );
 107 PMU_EVENT_ATTR_STRING(aperf,                            attr_aperf,             "event=0x01"    );
 108 PMU_EVENT_ATTR_STRING(mperf,                            attr_mperf,             "event=0x02"    );
 109 PMU_EVENT_ATTR_STRING(pperf,                            attr_pperf,             "event=0x03"    );
 110 PMU_EVENT_ATTR_STRING(smi,                              attr_smi,               "event=0x04"    );
 111 PMU_EVENT_ATTR_STRING(ptsc,                             attr_ptsc,              "event=0x05"    );
 112 PMU_EVENT_ATTR_STRING(irperf,                           attr_irperf,            "event=0x06"    );
 113 PMU_EVENT_ATTR_STRING(cpu_thermal_margin,               attr_therm,             "event=0x07"    );
 114 PMU_EVENT_ATTR_STRING(cpu_thermal_margin.snapshot,      attr_therm_snap,        "1"             );
 115 PMU_EVENT_ATTR_STRING(cpu_thermal_margin.unit,          attr_therm_unit,        "C"             );
 116
 117 static unsigned long msr_mask;
 118
 119 PMU_EVENT_GROUP(events, aperf);
 120 PMU_EVENT_GROUP(events, mperf);
 121 PMU_EVENT_GROUP(events, pperf);
 122 PMU_EVENT_GROUP(events, smi);
 123 PMU_EVENT_GROUP(events, ptsc);
 124 PMU_EVENT_GROUP(events, irperf);
 125
 126 static struct attribute *attrs_therm[] = {
 127         &attr_therm.attr.attr,
 128         &attr_therm_snap.attr.attr,
 129         &attr_therm_unit.attr.attr,
 130         NULL,
 131 };
 132
 133 static struct attribute_group group_therm = {
 134         .name  = "events",
 135         .attrs = attrs_therm,
 136 };
 137
 138 static struct perf_msr msr[] = {
 139         [PERF_MSR_TSC]          = { .no_check = true,                                                           },
 140         [PERF_MSR_APERF]        = { MSR_IA32_APERF,             &group_aperf,           test_aperfmperf,        },
 141         [PERF_MSR_MPERF]        = { MSR_IA32_MPERF,             &group_mperf,           test_aperfmperf,        },
 142         [PERF_MSR_PPERF]        = { MSR_PPERF,                  &group_pperf,           test_intel,             },
 143         [PERF_MSR_SMI]          = { MSR_SMI_COUNT,              &group_smi,             test_intel,             },
 144         [PERF_MSR_PTSC]         = { MSR_F15H_PTSC,              &group_ptsc,            test_ptsc,              },
 145         [PERF_MSR_IRPERF]       = { MSR_F17H_IRPERF,            &group_irperf,          test_irperf,            },
 146         [PERF_MSR_THERM]        = { MSR_IA32_THERM_STATUS,      &group_therm,           test_therm_status,      },
 147 };
 148
 149 static struct attribute *events_attrs[] = {
 150         &attr_tsc.attr.attr,
 151         NULL,
 152 };
 153
 154 static struct attribute_group events_attr_group = {
 155         .name = "events",
 156         .attrs = events_attrs,
 157 };
 158
 159 PMU_FORMAT_ATTR(event, "config:0-63");
 160 static struct attribute *format_attrs[] = {
 161         &format_attr_event.attr,
 162         NULL,
 163 };
 164 static struct attribute_group format_attr_group = {
 165         .name = "format",
 166         .attrs = format_attrs,
 167 };
 168
 169 static const struct attribute_group *attr_groups[] = {
 170         &events_attr_group,
 171         &format_attr_group,
 172         NULL,
 173 };
 174
 175 static const struct attribute_group *attr_update[] = {
 176         &group_aperf,
 177         &group_mperf,
 178         &group_pperf,
 179         &group_smi,
 180         &group_ptsc,
 181         &group_irperf,
 182         &group_therm,
 183         NULL,
 184 };
 185
 186 static int msr_event_init(struct perf_event *event)
 187 {
 188         u64 cfg = event->attr.config;
 189
 190         if (event->attr.type != event->pmu->type)
 191                 return -ENOENT;
 192
 193         /* unsupported modes and filters */
 194         if (event->attr.sample_period) /* no sampling */
 195                 return -EINVAL;
 196
 197         if (cfg >= PERF_MSR_EVENT_MAX)
 198                 return -EINVAL;
 199
 200         cfg = array_index_nospec((unsigned long)cfg, PERF_MSR_EVENT_MAX);
 201
 202         if (!(msr_mask & (1 << cfg)))
 203                 return -EINVAL;
 204
 205         event->hw.idx           = -1;
 206         event->hw.event_base    = msr[cfg].msr;
 207         event->hw.config        = cfg;
 208
 209         return 0;
 210 }
 211
 212 static inline u64 msr_read_counter(struct perf_event *event)
 213 {
 214         u64 now;
 215
 216         if (event->hw.event_base)
 217                 rdmsrl(event->hw.event_base, now);
 218         else
 219                 now = rdtsc_ordered();
 220
 221         return now;
 222 }
 223
 224 static void msr_event_update(struct perf_event *event)
 225 {
 226         u64 prev, now;
 227         s64 delta;
 228
 229         /* Careful, an NMI might modify the previous event value: */
 230 again:
 231         prev = local64_read(&event->hw.prev_count);
 232         now = msr_read_counter(event);
 233
 234         if (local64_cmpxchg(&event->hw.prev_count, prev, now) != prev)
 235                 goto again;
 236
 237         delta = now - prev;
 238         if (unlikely(event->hw.event_base == MSR_SMI_COUNT)) {
 239                 delta = sign_extend64(delta, 31);
 240                 local64_add(delta, &event->count);
 241         } else if (unlikely(event->hw.event_base == MSR_IA32_THERM_STATUS)) {
 242                 /* If valid, extract digital readout, otherwise set to -1: */
 243                 now = now & (1ULL << 31) ? (now >> 16) & 0x3f :  -1;
 244                 local64_set(&event->count, now);
 245         } else {
 246                 local64_add(delta, &event->count);
 247         }
 248 }
 249
 250 static void msr_event_start(struct perf_event *event, int flags)
 251 {
 252         u64 now = msr_read_counter(event);
 253
 254         local64_set(&event->hw.prev_count, now);
 255 }
 256
 257 static void msr_event_stop(struct perf_event *event, int flags)
 258 {
 259         msr_event_update(event);
 260 }
 261
 262 static void msr_event_del(struct perf_event *event, int flags)
 263 {
 264         msr_event_stop(event, PERF_EF_UPDATE);
 265 }
 266
 267 static int msr_event_add(struct perf_event *event, int flags)
 268 {
 269         if (flags & PERF_EF_START)
 270                 msr_event_start(event, flags);
 271
 272         return 0;
 273 }
 274
 275 static struct pmu pmu_msr = {
 276         .task_ctx_nr    = perf_sw_context,
 277         .attr_groups    = attr_groups,
 278         .event_init     = msr_event_init,
 279         .add            = msr_event_add,
 280         .del            = msr_event_del,
 281         .start          = msr_event_start,
 282         .stop           = msr_event_stop,
 283         .read           = msr_event_update,
 284         .capabilities   = PERF_PMU_CAP_NO_INTERRUPT | PERF_PMU_CAP_NO_EXCLUDE,
 285         .attr_update    = attr_update,
 286 };
 287
 288 static int __init msr_init(void)
 289 {
 290         if (!boot_cpu_has(X86_FEATURE_TSC)) {
 291                 pr_cont("no MSR PMU driver.\n");
 292                 return 0;
 293         }
 294
 295         msr_mask = perf_msr_probe(msr, PERF_MSR_EVENT_MAX, true, NULL);
 296
 297         perf_pmu_register(&pmu_msr, "msr", -1);
 298
 299         return 0;
 300 }
 301 device_initcall(msr_init);