2 * Intel(R) Processor Trace PMU driver for perf
3 * Copyright (c) 2013-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * Intel PT is specified in the Intel Architecture Instruction Set Extensions
15 * Programming Reference:
16 * http://software.intel.com/en-us/intel-isa-extensions
19 #ifndef __INTEL_PT_H__
20 #define __INTEL_PT_H__
23 * PT MSR bit definitions
25 #define RTIT_CTL_TRACEEN BIT(0)
26 #define RTIT_CTL_CYCLEACC BIT(1)
27 #define RTIT_CTL_OS BIT(2)
28 #define RTIT_CTL_USR BIT(3)
29 #define RTIT_CTL_CR3EN BIT(7)
30 #define RTIT_CTL_TOPA BIT(8)
31 #define RTIT_CTL_MTC_EN BIT(9)
32 #define RTIT_CTL_TSC_EN BIT(10)
33 #define RTIT_CTL_DISRETC BIT(11)
34 #define RTIT_CTL_BRANCH_EN BIT(13)
35 #define RTIT_CTL_MTC_RANGE_OFFSET 14
36 #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
37 #define RTIT_CTL_CYC_THRESH_OFFSET 19
38 #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET)
39 #define RTIT_CTL_PSB_FREQ_OFFSET 24
40 #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET)
41 #define RTIT_STATUS_CONTEXTEN BIT(1)
42 #define RTIT_STATUS_TRIGGEREN BIT(2)
43 #define RTIT_STATUS_ERROR BIT(4)
44 #define RTIT_STATUS_STOPPED BIT(5)
47 * Single-entry ToPA: when this close to region boundary, switch
48 * buffers to avoid losing data.
50 #define TOPA_PMI_MARGIN 512
54 static inline unsigned int sizes(unsigned int tsz)
56 return 1 << (tsz + TOPA_SHIFT);
72 #define PT_CPUID_LEAVES 2
73 #define PT_CPUID_REGS_NUM 4 /* number of regsters (eax, ebx, ecx, edx) */
75 enum pt_capabilities {
76 PT_CAP_max_subleaf = 0,
81 PT_CAP_topa_multiple_entries,
82 PT_CAP_single_range_output,
85 PT_CAP_cycle_thresholds,
91 u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
96 * struct pt_buffer - buffer configuration; one buffer per task_struct or
97 * cpu, depending on perf event configuration
98 * @cpu: cpu for per-cpu allocation
99 * @tables: list of ToPA tables in this buffer
100 * @first: shorthand for first topa table
101 * @last: shorthand for last topa table
102 * @cur: current topa table
103 * @nr_pages: buffer size in pages
104 * @cur_idx: current output region's index within @cur table
105 * @output_off: offset within the current output region
106 * @data_size: running total of the amount of data in this buffer
107 * @lost: if data was lost/truncated
108 * @head: logical write offset inside the buffer
109 * @snapshot: if this is for a snapshot/overwrite counter
110 * @stop_pos: STOP topa entry in the buffer
111 * @intr_pos: INT topa entry in the buffer
112 * @data_pages: array of pages from perf
113 * @topa_index: table of topa entries indexed by page offset
117 struct list_head tables;
118 struct topa *first, *last, *cur;
119 unsigned int cur_idx;
121 unsigned long nr_pages;
126 unsigned long stop_pos, intr_pos;
128 struct topa_entry *topa_index[0];
132 * struct pt - per-cpu pt context
133 * @handle: perf output handle
134 * @handle_nmi: do handle PT PMI on this cpu, there's an active event
135 * @vmx_on: 1 if VMX is ON on this cpu
138 struct perf_output_handle handle;
143 #endif /* __INTEL_PT_H__ */