1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel(R) Processor Trace PMU driver for perf
4 * Copyright (c) 2013-2014, Intel Corporation.
6 * Intel PT is specified in the Intel Architecture Instruction Set Extensions
7 * Programming Reference:
8 * http://software.intel.com/en-us/intel-isa-extensions
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15 #include <linux/types.h>
16 #include <linux/slab.h>
17 #include <linux/device.h>
19 #include <asm/perf_event.h>
22 #include <asm/intel_pt.h>
23 #include <asm/intel-family.h>
25 #include "../perf_event.h"
28 static DEFINE_PER_CPU(struct pt, pt_ctx);
30 static struct pt_pmu pt_pmu;
33 * Capabilities of Intel PT hardware, such as number of address bits or
34 * supported output schemes, are cached and exported to userspace as "caps"
35 * attribute group of pt pmu device
36 * (/sys/bus/event_source/devices/intel_pt/caps/) so that userspace can store
37 * relevant bits together with intel_pt traces.
39 * These are necessary for both trace decoding (payloads_lip, contains address
40 * width encoded in IP-related packets), and event configuration (bitmasks with
41 * permitted values for certain bit fields).
43 #define PT_CAP(_n, _l, _r, _m) \
44 [PT_CAP_ ## _n] = { .name = __stringify(_n), .leaf = _l, \
45 .reg = _r, .mask = _m }
47 static struct pt_cap_desc {
53 PT_CAP(max_subleaf, 0, CPUID_EAX, 0xffffffff),
54 PT_CAP(cr3_filtering, 0, CPUID_EBX, BIT(0)),
55 PT_CAP(psb_cyc, 0, CPUID_EBX, BIT(1)),
56 PT_CAP(ip_filtering, 0, CPUID_EBX, BIT(2)),
57 PT_CAP(mtc, 0, CPUID_EBX, BIT(3)),
58 PT_CAP(ptwrite, 0, CPUID_EBX, BIT(4)),
59 PT_CAP(power_event_trace, 0, CPUID_EBX, BIT(5)),
60 PT_CAP(topa_output, 0, CPUID_ECX, BIT(0)),
61 PT_CAP(topa_multiple_entries, 0, CPUID_ECX, BIT(1)),
62 PT_CAP(single_range_output, 0, CPUID_ECX, BIT(2)),
63 PT_CAP(output_subsys, 0, CPUID_ECX, BIT(3)),
64 PT_CAP(payloads_lip, 0, CPUID_ECX, BIT(31)),
65 PT_CAP(num_address_ranges, 1, CPUID_EAX, 0x3),
66 PT_CAP(mtc_periods, 1, CPUID_EAX, 0xffff0000),
67 PT_CAP(cycle_thresholds, 1, CPUID_EBX, 0xffff),
68 PT_CAP(psb_periods, 1, CPUID_EBX, 0xffff0000),
71 u32 intel_pt_validate_cap(u32 *caps, enum pt_capabilities capability)
73 struct pt_cap_desc *cd = &pt_caps[capability];
74 u32 c = caps[cd->leaf * PT_CPUID_REGS_NUM + cd->reg];
75 unsigned int shift = __ffs(cd->mask);
77 return (c & cd->mask) >> shift;
79 EXPORT_SYMBOL_GPL(intel_pt_validate_cap);
81 u32 intel_pt_validate_hw_cap(enum pt_capabilities cap)
83 return intel_pt_validate_cap(pt_pmu.caps, cap);
85 EXPORT_SYMBOL_GPL(intel_pt_validate_hw_cap);
87 static ssize_t pt_cap_show(struct device *cdev,
88 struct device_attribute *attr,
91 struct dev_ext_attribute *ea =
92 container_of(attr, struct dev_ext_attribute, attr);
93 enum pt_capabilities cap = (long)ea->var;
95 return snprintf(buf, PAGE_SIZE, "%x\n", intel_pt_validate_hw_cap(cap));
98 static struct attribute_group pt_cap_group __ro_after_init = {
102 PMU_FORMAT_ATTR(pt, "config:0" );
103 PMU_FORMAT_ATTR(cyc, "config:1" );
104 PMU_FORMAT_ATTR(pwr_evt, "config:4" );
105 PMU_FORMAT_ATTR(fup_on_ptw, "config:5" );
106 PMU_FORMAT_ATTR(mtc, "config:9" );
107 PMU_FORMAT_ATTR(tsc, "config:10" );
108 PMU_FORMAT_ATTR(noretcomp, "config:11" );
109 PMU_FORMAT_ATTR(ptw, "config:12" );
110 PMU_FORMAT_ATTR(branch, "config:13" );
111 PMU_FORMAT_ATTR(mtc_period, "config:14-17" );
112 PMU_FORMAT_ATTR(cyc_thresh, "config:19-22" );
113 PMU_FORMAT_ATTR(psb_period, "config:24-27" );
115 static struct attribute *pt_formats_attr[] = {
116 &format_attr_pt.attr,
117 &format_attr_cyc.attr,
118 &format_attr_pwr_evt.attr,
119 &format_attr_fup_on_ptw.attr,
120 &format_attr_mtc.attr,
121 &format_attr_tsc.attr,
122 &format_attr_noretcomp.attr,
123 &format_attr_ptw.attr,
124 &format_attr_branch.attr,
125 &format_attr_mtc_period.attr,
126 &format_attr_cyc_thresh.attr,
127 &format_attr_psb_period.attr,
131 static struct attribute_group pt_format_group = {
133 .attrs = pt_formats_attr,
137 pt_timing_attr_show(struct device *dev, struct device_attribute *attr,
140 struct perf_pmu_events_attr *pmu_attr =
141 container_of(attr, struct perf_pmu_events_attr, attr);
143 switch (pmu_attr->id) {
145 return sprintf(page, "%lu\n", pt_pmu.max_nonturbo_ratio);
147 return sprintf(page, "%u:%u\n",
157 PMU_EVENT_ATTR(max_nonturbo_ratio, timing_attr_max_nonturbo_ratio, 0,
158 pt_timing_attr_show);
159 PMU_EVENT_ATTR(tsc_art_ratio, timing_attr_tsc_art_ratio, 1,
160 pt_timing_attr_show);
162 static struct attribute *pt_timing_attr[] = {
163 &timing_attr_max_nonturbo_ratio.attr.attr,
164 &timing_attr_tsc_art_ratio.attr.attr,
168 static struct attribute_group pt_timing_group = {
169 .attrs = pt_timing_attr,
172 static const struct attribute_group *pt_attr_groups[] = {
179 static int __init pt_pmu_hw_init(void)
181 struct dev_ext_attribute *de_attrs;
182 struct attribute **attrs;
188 rdmsrl(MSR_PLATFORM_INFO, reg);
189 pt_pmu.max_nonturbo_ratio = (reg & 0xff00) >> 8;
192 * if available, read in TSC to core crystal clock ratio,
193 * otherwise, zero for numerator stands for "not enumerated"
196 if (boot_cpu_data.cpuid_level >= CPUID_TSC_LEAF) {
197 u32 eax, ebx, ecx, edx;
199 cpuid(CPUID_TSC_LEAF, &eax, &ebx, &ecx, &edx);
201 pt_pmu.tsc_art_num = ebx;
202 pt_pmu.tsc_art_den = eax;
205 /* model-specific quirks */
206 switch (boot_cpu_data.x86_model) {
207 case INTEL_FAM6_BROADWELL:
208 case INTEL_FAM6_BROADWELL_D:
209 case INTEL_FAM6_BROADWELL_G:
210 case INTEL_FAM6_BROADWELL_X:
211 /* not setting BRANCH_EN will #GP, erratum BDM106 */
212 pt_pmu.branch_en_always_on = true;
218 if (boot_cpu_has(X86_FEATURE_VMX)) {
220 * Intel SDM, 36.5 "Tracing post-VMXON" says that
221 * "IA32_VMX_MISC[bit 14]" being 1 means PT can trace
224 rdmsrl(MSR_IA32_VMX_MISC, reg);
231 for (i = 0; i < PT_CPUID_LEAVES; i++) {
233 &pt_pmu.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM],
234 &pt_pmu.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM],
235 &pt_pmu.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM],
236 &pt_pmu.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM]);
240 size = sizeof(struct attribute *) * (ARRAY_SIZE(pt_caps)+1);
241 attrs = kzalloc(size, GFP_KERNEL);
245 size = sizeof(struct dev_ext_attribute) * (ARRAY_SIZE(pt_caps)+1);
246 de_attrs = kzalloc(size, GFP_KERNEL);
250 for (i = 0; i < ARRAY_SIZE(pt_caps); i++) {
251 struct dev_ext_attribute *de_attr = de_attrs + i;
253 de_attr->attr.attr.name = pt_caps[i].name;
255 sysfs_attr_init(&de_attr->attr.attr);
257 de_attr->attr.attr.mode = S_IRUGO;
258 de_attr->attr.show = pt_cap_show;
259 de_attr->var = (void *)i;
261 attrs[i] = &de_attr->attr.attr;
264 pt_cap_group.attrs = attrs;
274 #define RTIT_CTL_CYC_PSB (RTIT_CTL_CYCLEACC | \
275 RTIT_CTL_CYC_THRESH | \
278 #define RTIT_CTL_MTC (RTIT_CTL_MTC_EN | \
281 #define RTIT_CTL_PTW (RTIT_CTL_PTW_EN | \
285 * Bit 0 (TraceEn) in the attr.config is meaningless as the
286 * corresponding bit in the RTIT_CTL can only be controlled
287 * by the driver; therefore, repurpose it to mean: pass
288 * through the bit that was previously assumed to be always
289 * on for PT, thereby allowing the user to *not* set it if
290 * they so wish. See also pt_event_valid() and pt_config().
292 #define RTIT_CTL_PASSTHROUGH RTIT_CTL_TRACEEN
294 #define PT_CONFIG_MASK (RTIT_CTL_TRACEEN | \
297 RTIT_CTL_BRANCH_EN | \
300 RTIT_CTL_PWR_EVT_EN | \
301 RTIT_CTL_FUP_ON_PTW | \
304 static bool pt_event_valid(struct perf_event *event)
306 u64 config = event->attr.config;
307 u64 allowed, requested;
309 if ((config & PT_CONFIG_MASK) != config)
312 if (config & RTIT_CTL_CYC_PSB) {
313 if (!intel_pt_validate_hw_cap(PT_CAP_psb_cyc))
316 allowed = intel_pt_validate_hw_cap(PT_CAP_psb_periods);
317 requested = (config & RTIT_CTL_PSB_FREQ) >>
318 RTIT_CTL_PSB_FREQ_OFFSET;
319 if (requested && (!(allowed & BIT(requested))))
322 allowed = intel_pt_validate_hw_cap(PT_CAP_cycle_thresholds);
323 requested = (config & RTIT_CTL_CYC_THRESH) >>
324 RTIT_CTL_CYC_THRESH_OFFSET;
325 if (requested && (!(allowed & BIT(requested))))
329 if (config & RTIT_CTL_MTC) {
331 * In the unlikely case that CPUID lists valid mtc periods,
332 * but not the mtc capability, drop out here.
334 * Spec says that setting mtc period bits while mtc bit in
335 * CPUID is 0 will #GP, so better safe than sorry.
337 if (!intel_pt_validate_hw_cap(PT_CAP_mtc))
340 allowed = intel_pt_validate_hw_cap(PT_CAP_mtc_periods);
344 requested = (config & RTIT_CTL_MTC_RANGE) >>
345 RTIT_CTL_MTC_RANGE_OFFSET;
347 if (!(allowed & BIT(requested)))
351 if (config & RTIT_CTL_PWR_EVT_EN &&
352 !intel_pt_validate_hw_cap(PT_CAP_power_event_trace))
355 if (config & RTIT_CTL_PTW) {
356 if (!intel_pt_validate_hw_cap(PT_CAP_ptwrite))
359 /* FUPonPTW without PTW doesn't make sense */
360 if ((config & RTIT_CTL_FUP_ON_PTW) &&
361 !(config & RTIT_CTL_PTW_EN))
366 * Setting bit 0 (TraceEn in RTIT_CTL MSR) in the attr.config
367 * clears the assomption that BranchEn must always be enabled,
368 * as was the case with the first implementation of PT.
369 * If this bit is not set, the legacy behavior is preserved
370 * for compatibility with the older userspace.
372 * Re-using bit 0 for this purpose is fine because it is never
373 * directly set by the user; previous attempts at setting it in
374 * the attr.config resulted in -EINVAL.
376 if (config & RTIT_CTL_PASSTHROUGH) {
378 * Disallow not setting BRANCH_EN where BRANCH_EN is
381 if (pt_pmu.branch_en_always_on &&
382 !(config & RTIT_CTL_BRANCH_EN))
386 * Disallow BRANCH_EN without the PASSTHROUGH.
388 if (config & RTIT_CTL_BRANCH_EN)
396 * PT configuration helpers
397 * These all are cpu affine and operate on a local PT
400 /* Address ranges and their corresponding msr configuration registers */
401 static const struct pt_address_range {
404 unsigned int reg_off;
405 } pt_address_ranges[] = {
407 .msr_a = MSR_IA32_RTIT_ADDR0_A,
408 .msr_b = MSR_IA32_RTIT_ADDR0_B,
409 .reg_off = RTIT_CTL_ADDR0_OFFSET,
412 .msr_a = MSR_IA32_RTIT_ADDR1_A,
413 .msr_b = MSR_IA32_RTIT_ADDR1_B,
414 .reg_off = RTIT_CTL_ADDR1_OFFSET,
417 .msr_a = MSR_IA32_RTIT_ADDR2_A,
418 .msr_b = MSR_IA32_RTIT_ADDR2_B,
419 .reg_off = RTIT_CTL_ADDR2_OFFSET,
422 .msr_a = MSR_IA32_RTIT_ADDR3_A,
423 .msr_b = MSR_IA32_RTIT_ADDR3_B,
424 .reg_off = RTIT_CTL_ADDR3_OFFSET,
428 static u64 pt_config_filters(struct perf_event *event)
430 struct pt_filters *filters = event->hw.addr_filters;
431 struct pt *pt = this_cpu_ptr(&pt_ctx);
432 unsigned int range = 0;
438 perf_event_addr_filters_sync(event);
440 for (range = 0; range < filters->nr_filters; range++) {
441 struct pt_filter *filter = &filters->filter[range];
444 * Note, if the range has zero start/end addresses due
445 * to its dynamic object not being loaded yet, we just
446 * go ahead and program zeroed range, which will simply
447 * produce no data. Note^2: if executable code at 0x0
448 * is a concern, we can set up an "invalid" configuration
449 * such as msr_b < msr_a.
452 /* avoid redundant msr writes */
453 if (pt->filters.filter[range].msr_a != filter->msr_a) {
454 wrmsrl(pt_address_ranges[range].msr_a, filter->msr_a);
455 pt->filters.filter[range].msr_a = filter->msr_a;
458 if (pt->filters.filter[range].msr_b != filter->msr_b) {
459 wrmsrl(pt_address_ranges[range].msr_b, filter->msr_b);
460 pt->filters.filter[range].msr_b = filter->msr_b;
463 rtit_ctl |= filter->config << pt_address_ranges[range].reg_off;
469 static void pt_config(struct perf_event *event)
471 struct pt *pt = this_cpu_ptr(&pt_ctx);
474 /* First round: clear STATUS, in particular the PSB byte counter. */
475 if (!event->hw.config) {
476 perf_event_itrace_started(event);
477 wrmsrl(MSR_IA32_RTIT_STATUS, 0);
480 reg = pt_config_filters(event);
481 reg |= RTIT_CTL_TOPA | RTIT_CTL_TRACEEN;
484 * Previously, we had BRANCH_EN on by default, but now that PT has
485 * grown features outside of branch tracing, it is useful to allow
486 * the user to disable it. Setting bit 0 in the event's attr.config
487 * allows BRANCH_EN to pass through instead of being always on. See
488 * also the comment in pt_event_valid().
490 if (event->attr.config & BIT(0)) {
491 reg |= event->attr.config & RTIT_CTL_BRANCH_EN;
493 reg |= RTIT_CTL_BRANCH_EN;
496 if (!event->attr.exclude_kernel)
498 if (!event->attr.exclude_user)
501 reg |= (event->attr.config & PT_CONFIG_MASK);
503 event->hw.config = reg;
504 if (READ_ONCE(pt->vmx_on))
505 perf_aux_output_flag(&pt->handle, PERF_AUX_FLAG_PARTIAL);
507 wrmsrl(MSR_IA32_RTIT_CTL, reg);
510 static void pt_config_stop(struct perf_event *event)
512 struct pt *pt = this_cpu_ptr(&pt_ctx);
513 u64 ctl = READ_ONCE(event->hw.config);
515 /* may be already stopped by a PMI */
516 if (!(ctl & RTIT_CTL_TRACEEN))
519 ctl &= ~RTIT_CTL_TRACEEN;
520 if (!READ_ONCE(pt->vmx_on))
521 wrmsrl(MSR_IA32_RTIT_CTL, ctl);
523 WRITE_ONCE(event->hw.config, ctl);
526 * A wrmsr that disables trace generation serializes other PT
527 * registers and causes all data packets to be written to memory,
528 * but a fence is required for the data to become globally visible.
530 * The below WMB, separating data store and aux_head store matches
531 * the consumer's RMB that separates aux_head load and data load.
536 static void pt_config_buffer(void *buf, unsigned int topa_idx,
537 unsigned int output_off)
541 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, virt_to_phys(buf));
543 reg = 0x7f | ((u64)topa_idx << 7) | ((u64)output_off << 32);
545 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, reg);
549 * struct topa - ToPA metadata
550 * @list: linkage to struct pt_buffer's list of tables
551 * @offset: offset of the first entry in this table in the buffer
552 * @size: total size of all entries in this table
553 * @last: index of the last initialized entry in this table
554 * @z_count: how many times the first entry repeats
557 struct list_head list;
561 unsigned int z_count;
565 * Keep ToPA table-related metadata on the same page as the actual table,
566 * taking up a few words from the top
569 #define TENTS_PER_PAGE \
570 ((PAGE_SIZE - sizeof(struct topa)) / sizeof(struct topa_entry))
573 * struct topa_page - page-sized ToPA table with metadata at the top
574 * @table: actual ToPA table entries, as understood by PT hardware
578 struct topa_entry table[TENTS_PER_PAGE];
582 static inline struct topa_page *topa_to_page(struct topa *topa)
584 return container_of(topa, struct topa_page, topa);
587 static inline struct topa_page *topa_entry_to_page(struct topa_entry *te)
589 return (struct topa_page *)((unsigned long)te & PAGE_MASK);
592 static inline phys_addr_t topa_pfn(struct topa *topa)
594 return PFN_DOWN(virt_to_phys(topa_to_page(topa)));
597 /* make -1 stand for the last table entry */
598 #define TOPA_ENTRY(t, i) \
600 ? &topa_to_page(t)->table[(t)->last] \
601 : &topa_to_page(t)->table[(i)])
602 #define TOPA_ENTRY_SIZE(t, i) (sizes(TOPA_ENTRY((t), (i))->size))
603 #define TOPA_ENTRY_PAGES(t, i) (1 << TOPA_ENTRY((t), (i))->size)
606 * topa_alloc() - allocate page-sized ToPA table
607 * @cpu: CPU on which to allocate.
608 * @gfp: Allocation flags.
610 * Return: On success, return the pointer to ToPA table page.
612 static struct topa *topa_alloc(int cpu, gfp_t gfp)
614 int node = cpu_to_node(cpu);
615 struct topa_page *tp;
618 p = alloc_pages_node(node, gfp | __GFP_ZERO, 0);
622 tp = page_address(p);
626 * In case of singe-entry ToPA, always put the self-referencing END
627 * link as the 2nd entry in the table
629 if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries)) {
630 TOPA_ENTRY(&tp->topa, 1)->base = page_to_phys(p);
631 TOPA_ENTRY(&tp->topa, 1)->end = 1;
638 * topa_free() - free a page-sized ToPA table
639 * @topa: Table to deallocate.
641 static void topa_free(struct topa *topa)
643 free_page((unsigned long)topa);
647 * topa_insert_table() - insert a ToPA table into a buffer
648 * @buf: PT buffer that's being extended.
649 * @topa: New topa table to be inserted.
651 * If it's the first table in this buffer, set up buffer's pointers
652 * accordingly; otherwise, add a END=1 link entry to @topa to the current
653 * "last" table and adjust the last table pointer to @topa.
655 static void topa_insert_table(struct pt_buffer *buf, struct topa *topa)
657 struct topa *last = buf->last;
659 list_add_tail(&topa->list, &buf->tables);
662 buf->first = buf->last = buf->cur = topa;
666 topa->offset = last->offset + last->size;
669 if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries))
672 BUG_ON(last->last != TENTS_PER_PAGE - 1);
674 TOPA_ENTRY(last, -1)->base = topa_pfn(topa);
675 TOPA_ENTRY(last, -1)->end = 1;
679 * topa_table_full() - check if a ToPA table is filled up
682 static bool topa_table_full(struct topa *topa)
684 /* single-entry ToPA is a special case */
685 if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries))
688 return topa->last == TENTS_PER_PAGE - 1;
692 * topa_insert_pages() - create a list of ToPA tables
693 * @buf: PT buffer being initialized.
694 * @gfp: Allocation flags.
696 * This initializes a list of ToPA tables with entries from
697 * the data_pages provided by rb_alloc_aux().
699 * Return: 0 on success or error code.
701 static int topa_insert_pages(struct pt_buffer *buf, int cpu, gfp_t gfp)
703 struct topa *topa = buf->last;
707 p = virt_to_page(buf->data_pages[buf->nr_pages]);
709 order = page_private(p);
711 if (topa_table_full(topa)) {
712 topa = topa_alloc(cpu, gfp);
716 topa_insert_table(buf, topa);
719 if (topa->z_count == topa->last - 1) {
720 if (order == TOPA_ENTRY(topa, topa->last - 1)->size)
724 TOPA_ENTRY(topa, -1)->base = page_to_phys(p) >> TOPA_SHIFT;
725 TOPA_ENTRY(topa, -1)->size = order;
726 if (!buf->snapshot &&
727 !intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries)) {
728 TOPA_ENTRY(topa, -1)->intr = 1;
729 TOPA_ENTRY(topa, -1)->stop = 1;
733 topa->size += sizes(order);
735 buf->nr_pages += 1ul << order;
741 * pt_topa_dump() - print ToPA tables and their entries
744 static void pt_topa_dump(struct pt_buffer *buf)
748 list_for_each_entry(topa, &buf->tables, list) {
749 struct topa_page *tp = topa_to_page(topa);
752 pr_debug("# table @%p, off %llx size %zx\n", tp->table,
753 topa->offset, topa->size);
754 for (i = 0; i < TENTS_PER_PAGE; i++) {
755 pr_debug("# entry @%p (%lx sz %u %c%c%c) raw=%16llx\n",
757 (unsigned long)tp->table[i].base << TOPA_SHIFT,
758 sizes(tp->table[i].size),
759 tp->table[i].end ? 'E' : ' ',
760 tp->table[i].intr ? 'I' : ' ',
761 tp->table[i].stop ? 'S' : ' ',
762 *(u64 *)&tp->table[i]);
763 if ((intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries) &&
764 tp->table[i].stop) ||
767 if (!i && topa->z_count)
774 * pt_buffer_advance() - advance to the next output region
777 * Advance the current pointers in the buffer to the next ToPA entry.
779 static void pt_buffer_advance(struct pt_buffer *buf)
784 if (buf->cur_idx == buf->cur->last) {
785 if (buf->cur == buf->last)
786 buf->cur = buf->first;
788 buf->cur = list_entry(buf->cur->list.next, struct topa,
795 * pt_update_head() - calculate current offsets and sizes
796 * @pt: Per-cpu pt context.
798 * Update buffer's current write pointer position and data size.
800 static void pt_update_head(struct pt *pt)
802 struct pt_buffer *buf = perf_get_aux(&pt->handle);
803 u64 topa_idx, base, old;
805 /* offset of the first region in this table from the beginning of buf */
806 base = buf->cur->offset + buf->output_off;
808 /* offset of the current output region within this table */
809 for (topa_idx = 0; topa_idx < buf->cur_idx; topa_idx++)
810 base += TOPA_ENTRY_SIZE(buf->cur, topa_idx);
813 local_set(&buf->data_size, base);
815 old = (local64_xchg(&buf->head, base) &
816 ((buf->nr_pages << PAGE_SHIFT) - 1));
818 base += buf->nr_pages << PAGE_SHIFT;
820 local_add(base - old, &buf->data_size);
825 * pt_buffer_region() - obtain current output region's address
828 static void *pt_buffer_region(struct pt_buffer *buf)
830 return phys_to_virt(TOPA_ENTRY(buf->cur, buf->cur_idx)->base << TOPA_SHIFT);
834 * pt_buffer_region_size() - obtain current output region's size
837 static size_t pt_buffer_region_size(struct pt_buffer *buf)
839 return TOPA_ENTRY_SIZE(buf->cur, buf->cur_idx);
843 * pt_handle_status() - take care of possible status conditions
844 * @pt: Per-cpu pt context.
846 static void pt_handle_status(struct pt *pt)
848 struct pt_buffer *buf = perf_get_aux(&pt->handle);
852 rdmsrl(MSR_IA32_RTIT_STATUS, status);
854 if (status & RTIT_STATUS_ERROR) {
855 pr_err_ratelimited("ToPA ERROR encountered, trying to recover\n");
857 status &= ~RTIT_STATUS_ERROR;
860 if (status & RTIT_STATUS_STOPPED) {
861 status &= ~RTIT_STATUS_STOPPED;
864 * On systems that only do single-entry ToPA, hitting STOP
865 * means we are already losing data; need to let the decoder
868 if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries) ||
869 buf->output_off == pt_buffer_region_size(buf)) {
870 perf_aux_output_flag(&pt->handle,
871 PERF_AUX_FLAG_TRUNCATED);
877 * Also on single-entry ToPA implementations, interrupt will come
878 * before the output reaches its output region's boundary.
880 if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries) &&
882 pt_buffer_region_size(buf) - buf->output_off <= TOPA_PMI_MARGIN) {
883 void *head = pt_buffer_region(buf);
885 /* everything within this margin needs to be zeroed out */
886 memset(head + buf->output_off, 0,
887 pt_buffer_region_size(buf) -
893 pt_buffer_advance(buf);
895 wrmsrl(MSR_IA32_RTIT_STATUS, status);
899 * pt_read_offset() - translate registers into buffer pointers
902 * Set buffer's output pointers from MSR values.
904 static void pt_read_offset(struct pt_buffer *buf)
906 u64 offset, base_topa;
907 struct topa_page *tp;
909 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, base_topa);
910 tp = phys_to_virt(base_topa);
911 buf->cur = &tp->topa;
913 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, offset);
914 /* offset within current output region */
915 buf->output_off = offset >> 32;
916 /* index of current output region within this table */
917 buf->cur_idx = (offset & 0xffffff80) >> 7;
920 static struct topa_entry *
921 pt_topa_entry_for_page(struct pt_buffer *buf, unsigned int pg)
923 struct topa_page *tp;
925 unsigned int idx, cur_pg = 0, z_pg = 0, start_idx = 0;
928 * Indicates a bug in the caller.
930 if (WARN_ON_ONCE(pg >= buf->nr_pages))
934 * First, find the ToPA table where @pg fits. With high
935 * order allocations, there shouldn't be many of these.
937 list_for_each_entry(topa, &buf->tables, list) {
938 if (topa->offset + topa->size > pg << PAGE_SHIFT)
943 * Hitting this means we have a problem in the ToPA
952 * Indicates a problem in the ToPA allocation code.
954 if (WARN_ON_ONCE(topa->last == -1))
957 tp = topa_to_page(topa);
958 cur_pg = PFN_DOWN(topa->offset);
960 z_pg = TOPA_ENTRY_PAGES(topa, 0) * (topa->z_count + 1);
961 start_idx = topa->z_count + 1;
965 * Multiple entries at the beginning of the table have the same size,
966 * ideally all of them; if @pg falls there, the search is done.
968 if (pg >= cur_pg && pg < cur_pg + z_pg) {
969 idx = (pg - cur_pg) / TOPA_ENTRY_PAGES(topa, 0);
970 return &tp->table[idx];
974 * Otherwise, slow path: iterate through the remaining entries.
976 for (idx = start_idx, cur_pg += z_pg; idx < topa->last; idx++) {
977 if (cur_pg + TOPA_ENTRY_PAGES(topa, idx) > pg)
978 return &tp->table[idx];
980 cur_pg += TOPA_ENTRY_PAGES(topa, idx);
984 * Means we couldn't find a ToPA entry in the table that does match.
991 static struct topa_entry *
992 pt_topa_prev_entry(struct pt_buffer *buf, struct topa_entry *te)
994 unsigned long table = (unsigned long)te & ~(PAGE_SIZE - 1);
995 struct topa_page *tp;
998 tp = (struct topa_page *)table;
1003 if (topa == buf->first)
1006 topa = list_prev_entry(topa, list);
1008 tp = topa_to_page(topa);
1010 return &tp->table[topa->last - 1];
1014 * pt_buffer_reset_markers() - place interrupt and stop bits in the buffer
1016 * @handle: Current output handle.
1018 * Place INT and STOP marks to prevent overwriting old data that the consumer
1019 * hasn't yet collected and waking up the consumer after a certain fraction of
1020 * the buffer has filled up. Only needed and sensible for non-snapshot counters.
1022 * This obviously relies on buf::head to figure out buffer markers, so it has
1023 * to be called after pt_buffer_reset_offsets() and before the hardware tracing
1026 static int pt_buffer_reset_markers(struct pt_buffer *buf,
1027 struct perf_output_handle *handle)
1030 unsigned long head = local64_read(&buf->head);
1031 unsigned long idx, npages, wakeup;
1033 /* can't stop in the middle of an output region */
1034 if (buf->output_off + handle->size + 1 < pt_buffer_region_size(buf)) {
1035 perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
1040 /* single entry ToPA is handled by marking all regions STOP=1 INT=1 */
1041 if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries))
1044 /* clear STOP and INT from current entry */
1046 buf->stop_te->stop = 0;
1047 buf->stop_te->intr = 0;
1051 buf->intr_te->intr = 0;
1053 /* how many pages till the STOP marker */
1054 npages = handle->size >> PAGE_SHIFT;
1056 /* if it's on a page boundary, fill up one more page */
1057 if (!offset_in_page(head + handle->size + 1))
1060 idx = (head >> PAGE_SHIFT) + npages;
1061 idx &= buf->nr_pages - 1;
1063 if (idx != buf->stop_pos) {
1064 buf->stop_pos = idx;
1065 buf->stop_te = pt_topa_entry_for_page(buf, idx);
1066 buf->stop_te = pt_topa_prev_entry(buf, buf->stop_te);
1069 wakeup = handle->wakeup >> PAGE_SHIFT;
1071 /* in the worst case, wake up the consumer one page before hard stop */
1072 idx = (head >> PAGE_SHIFT) + npages - 1;
1076 idx &= buf->nr_pages - 1;
1077 if (idx != buf->intr_pos) {
1078 buf->intr_pos = idx;
1079 buf->intr_te = pt_topa_entry_for_page(buf, idx);
1080 buf->intr_te = pt_topa_prev_entry(buf, buf->intr_te);
1083 buf->stop_te->stop = 1;
1084 buf->stop_te->intr = 1;
1085 buf->intr_te->intr = 1;
1091 * pt_buffer_reset_offsets() - adjust buffer's write pointers from aux_head
1093 * @head: Write pointer (aux_head) from AUX buffer.
1095 * Find the ToPA table and entry corresponding to given @head and set buffer's
1096 * "current" pointers accordingly. This is done after we have obtained the
1097 * current aux_head position from a successful call to perf_aux_output_begin()
1098 * to make sure the hardware is writing to the right place.
1100 * This function modifies buf::{cur,cur_idx,output_off} that will be programmed
1101 * into PT msrs when the tracing is enabled and buf::head and buf::data_size,
1102 * which are used to determine INT and STOP markers' locations by a subsequent
1103 * call to pt_buffer_reset_markers().
1105 static void pt_buffer_reset_offsets(struct pt_buffer *buf, unsigned long head)
1107 struct topa_page *cur_tp;
1108 struct topa_entry *te;
1112 head &= (buf->nr_pages << PAGE_SHIFT) - 1;
1114 pg = (head >> PAGE_SHIFT) & (buf->nr_pages - 1);
1115 te = pt_topa_entry_for_page(buf, pg);
1117 cur_tp = topa_entry_to_page(te);
1118 buf->cur = &cur_tp->topa;
1119 buf->cur_idx = te - TOPA_ENTRY(buf->cur, 0);
1120 buf->output_off = head & (pt_buffer_region_size(buf) - 1);
1122 local64_set(&buf->head, head);
1123 local_set(&buf->data_size, 0);
1127 * pt_buffer_fini_topa() - deallocate ToPA structure of a buffer
1130 static void pt_buffer_fini_topa(struct pt_buffer *buf)
1132 struct topa *topa, *iter;
1134 list_for_each_entry_safe(topa, iter, &buf->tables, list) {
1136 * right now, this is in free_aux() path only, so
1137 * no need to unlink this table from the list
1144 * pt_buffer_init_topa() - initialize ToPA table for pt buffer
1146 * @size: Total size of all regions within this ToPA.
1147 * @gfp: Allocation flags.
1149 static int pt_buffer_init_topa(struct pt_buffer *buf, int cpu,
1150 unsigned long nr_pages, gfp_t gfp)
1155 topa = topa_alloc(cpu, gfp);
1159 topa_insert_table(buf, topa);
1161 while (buf->nr_pages < nr_pages) {
1162 err = topa_insert_pages(buf, cpu, gfp);
1164 pt_buffer_fini_topa(buf);
1169 /* link last table to the first one, unless we're double buffering */
1170 if (intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries)) {
1171 TOPA_ENTRY(buf->last, -1)->base = topa_pfn(buf->first);
1172 TOPA_ENTRY(buf->last, -1)->end = 1;
1180 * pt_buffer_setup_aux() - set up topa tables for a PT buffer
1181 * @cpu: Cpu on which to allocate, -1 means current.
1182 * @pages: Array of pointers to buffer pages passed from perf core.
1183 * @nr_pages: Number of pages in the buffer.
1184 * @snapshot: If this is a snapshot/overwrite counter.
1186 * This is a pmu::setup_aux callback that sets up ToPA tables and all the
1187 * bookkeeping for an AUX buffer.
1189 * Return: Our private PT buffer structure.
1192 pt_buffer_setup_aux(struct perf_event *event, void **pages,
1193 int nr_pages, bool snapshot)
1195 struct pt_buffer *buf;
1196 int node, ret, cpu = event->cpu;
1202 cpu = raw_smp_processor_id();
1203 node = cpu_to_node(cpu);
1205 buf = kzalloc_node(sizeof(struct pt_buffer), GFP_KERNEL, node);
1209 buf->snapshot = snapshot;
1210 buf->data_pages = pages;
1214 INIT_LIST_HEAD(&buf->tables);
1216 ret = pt_buffer_init_topa(buf, cpu, nr_pages, GFP_KERNEL);
1226 * pt_buffer_free_aux() - perf AUX deallocation path callback
1229 static void pt_buffer_free_aux(void *data)
1231 struct pt_buffer *buf = data;
1233 pt_buffer_fini_topa(buf);
1237 static int pt_addr_filters_init(struct perf_event *event)
1239 struct pt_filters *filters;
1240 int node = event->cpu == -1 ? -1 : cpu_to_node(event->cpu);
1242 if (!intel_pt_validate_hw_cap(PT_CAP_num_address_ranges))
1245 filters = kzalloc_node(sizeof(struct pt_filters), GFP_KERNEL, node);
1250 memcpy(filters, event->parent->hw.addr_filters,
1253 event->hw.addr_filters = filters;
1258 static void pt_addr_filters_fini(struct perf_event *event)
1260 kfree(event->hw.addr_filters);
1261 event->hw.addr_filters = NULL;
1264 static inline bool valid_kernel_ip(unsigned long ip)
1266 return virt_addr_valid(ip) && kernel_ip(ip);
1269 static int pt_event_addr_filters_validate(struct list_head *filters)
1271 struct perf_addr_filter *filter;
1274 list_for_each_entry(filter, filters, entry) {
1276 * PT doesn't support single address triggers and
1279 if (!filter->size ||
1280 filter->action == PERF_ADDR_FILTER_ACTION_START)
1283 if (!filter->path.dentry) {
1284 if (!valid_kernel_ip(filter->offset))
1287 if (!valid_kernel_ip(filter->offset + filter->size))
1291 if (++range > intel_pt_validate_hw_cap(PT_CAP_num_address_ranges))
1298 static void pt_event_addr_filters_sync(struct perf_event *event)
1300 struct perf_addr_filters_head *head = perf_event_addr_filters(event);
1301 unsigned long msr_a, msr_b;
1302 struct perf_addr_filter_range *fr = event->addr_filter_ranges;
1303 struct pt_filters *filters = event->hw.addr_filters;
1304 struct perf_addr_filter *filter;
1310 list_for_each_entry(filter, &head->list, entry) {
1311 if (filter->path.dentry && !fr[range].start) {
1314 /* apply the offset */
1315 msr_a = fr[range].start;
1316 msr_b = msr_a + fr[range].size - 1;
1319 filters->filter[range].msr_a = msr_a;
1320 filters->filter[range].msr_b = msr_b;
1321 if (filter->action == PERF_ADDR_FILTER_ACTION_FILTER)
1322 filters->filter[range].config = 1;
1324 filters->filter[range].config = 2;
1328 filters->nr_filters = range;
1332 * intel_pt_interrupt() - PT PMI handler
1334 void intel_pt_interrupt(void)
1336 struct pt *pt = this_cpu_ptr(&pt_ctx);
1337 struct pt_buffer *buf;
1338 struct perf_event *event = pt->handle.event;
1341 * There may be a dangling PT bit in the interrupt status register
1342 * after PT has been disabled by pt_event_stop(). Make sure we don't
1343 * do anything (particularly, re-enable) for this event here.
1345 if (!READ_ONCE(pt->handle_nmi))
1351 pt_config_stop(event);
1353 buf = perf_get_aux(&pt->handle);
1357 pt_read_offset(buf);
1359 pt_handle_status(pt);
1363 perf_aux_output_end(&pt->handle, local_xchg(&buf->data_size, 0));
1365 if (!event->hw.state) {
1368 buf = perf_aux_output_begin(&pt->handle, event);
1370 event->hw.state = PERF_HES_STOPPED;
1374 pt_buffer_reset_offsets(buf, pt->handle.head);
1375 /* snapshot counters don't use PMI, so it's safe */
1376 ret = pt_buffer_reset_markers(buf, &pt->handle);
1378 perf_aux_output_end(&pt->handle, 0);
1382 pt_config_buffer(topa_to_page(buf->cur)->table, buf->cur_idx,
1388 void intel_pt_handle_vmx(int on)
1390 struct pt *pt = this_cpu_ptr(&pt_ctx);
1391 struct perf_event *event;
1392 unsigned long flags;
1394 /* PT plays nice with VMX, do nothing */
1399 * VMXON will clear RTIT_CTL.TraceEn; we need to make
1400 * sure to not try to set it while VMX is on. Disable
1401 * interrupts to avoid racing with pmu callbacks;
1402 * concurrent PMI should be handled fine.
1404 local_irq_save(flags);
1405 WRITE_ONCE(pt->vmx_on, on);
1408 * If an AUX transaction is in progress, it will contain
1409 * gap(s), so flag it PARTIAL to inform the user.
1411 event = pt->handle.event;
1413 perf_aux_output_flag(&pt->handle,
1414 PERF_AUX_FLAG_PARTIAL);
1416 /* Turn PTs back on */
1418 wrmsrl(MSR_IA32_RTIT_CTL, event->hw.config);
1420 local_irq_restore(flags);
1422 EXPORT_SYMBOL_GPL(intel_pt_handle_vmx);
1428 static void pt_event_start(struct perf_event *event, int mode)
1430 struct hw_perf_event *hwc = &event->hw;
1431 struct pt *pt = this_cpu_ptr(&pt_ctx);
1432 struct pt_buffer *buf;
1434 buf = perf_aux_output_begin(&pt->handle, event);
1438 pt_buffer_reset_offsets(buf, pt->handle.head);
1439 if (!buf->snapshot) {
1440 if (pt_buffer_reset_markers(buf, &pt->handle))
1444 WRITE_ONCE(pt->handle_nmi, 1);
1447 pt_config_buffer(topa_to_page(buf->cur)->table, buf->cur_idx,
1454 perf_aux_output_end(&pt->handle, 0);
1456 hwc->state = PERF_HES_STOPPED;
1459 static void pt_event_stop(struct perf_event *event, int mode)
1461 struct pt *pt = this_cpu_ptr(&pt_ctx);
1464 * Protect against the PMI racing with disabling wrmsr,
1465 * see comment in intel_pt_interrupt().
1467 WRITE_ONCE(pt->handle_nmi, 0);
1469 pt_config_stop(event);
1471 if (event->hw.state == PERF_HES_STOPPED)
1474 event->hw.state = PERF_HES_STOPPED;
1476 if (mode & PERF_EF_UPDATE) {
1477 struct pt_buffer *buf = perf_get_aux(&pt->handle);
1482 if (WARN_ON_ONCE(pt->handle.event != event))
1485 pt_read_offset(buf);
1487 pt_handle_status(pt);
1493 local_xchg(&buf->data_size,
1494 buf->nr_pages << PAGE_SHIFT);
1495 perf_aux_output_end(&pt->handle, local_xchg(&buf->data_size, 0));
1499 static void pt_event_del(struct perf_event *event, int mode)
1501 pt_event_stop(event, PERF_EF_UPDATE);
1504 static int pt_event_add(struct perf_event *event, int mode)
1506 struct pt *pt = this_cpu_ptr(&pt_ctx);
1507 struct hw_perf_event *hwc = &event->hw;
1510 if (pt->handle.event)
1513 if (mode & PERF_EF_START) {
1514 pt_event_start(event, 0);
1516 if (hwc->state == PERF_HES_STOPPED)
1519 hwc->state = PERF_HES_STOPPED;
1528 static void pt_event_read(struct perf_event *event)
1532 static void pt_event_destroy(struct perf_event *event)
1534 pt_addr_filters_fini(event);
1535 x86_del_exclusive(x86_lbr_exclusive_pt);
1538 static int pt_event_init(struct perf_event *event)
1540 if (event->attr.type != pt_pmu.pmu.type)
1543 if (!pt_event_valid(event))
1546 if (x86_add_exclusive(x86_lbr_exclusive_pt))
1549 if (pt_addr_filters_init(event)) {
1550 x86_del_exclusive(x86_lbr_exclusive_pt);
1554 event->destroy = pt_event_destroy;
1559 void cpu_emergency_stop_pt(void)
1561 struct pt *pt = this_cpu_ptr(&pt_ctx);
1563 if (pt->handle.event)
1564 pt_event_stop(pt->handle.event, PERF_EF_UPDATE);
1567 int is_intel_pt_event(struct perf_event *event)
1569 return event->pmu == &pt_pmu.pmu;
1572 static __init int pt_init(void)
1574 int ret, cpu, prior_warn = 0;
1576 BUILD_BUG_ON(sizeof(struct topa) > PAGE_SIZE);
1578 if (!boot_cpu_has(X86_FEATURE_INTEL_PT))
1582 for_each_online_cpu(cpu) {
1585 ret = rdmsrl_safe_on_cpu(cpu, MSR_IA32_RTIT_CTL, &ctl);
1586 if (!ret && (ctl & RTIT_CTL_TRACEEN))
1592 x86_add_exclusive(x86_lbr_exclusive_pt);
1593 pr_warn("PT is enabled at boot time, doing nothing\n");
1598 ret = pt_pmu_hw_init();
1602 if (!intel_pt_validate_hw_cap(PT_CAP_topa_output)) {
1603 pr_warn("ToPA output is not supported on this CPU\n");
1607 if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries))
1608 pt_pmu.pmu.capabilities = PERF_PMU_CAP_AUX_NO_SG;
1610 pt_pmu.pmu.capabilities |= PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE;
1611 pt_pmu.pmu.attr_groups = pt_attr_groups;
1612 pt_pmu.pmu.task_ctx_nr = perf_sw_context;
1613 pt_pmu.pmu.event_init = pt_event_init;
1614 pt_pmu.pmu.add = pt_event_add;
1615 pt_pmu.pmu.del = pt_event_del;
1616 pt_pmu.pmu.start = pt_event_start;
1617 pt_pmu.pmu.stop = pt_event_stop;
1618 pt_pmu.pmu.read = pt_event_read;
1619 pt_pmu.pmu.setup_aux = pt_buffer_setup_aux;
1620 pt_pmu.pmu.free_aux = pt_buffer_free_aux;
1621 pt_pmu.pmu.addr_filters_sync = pt_event_addr_filters_sync;
1622 pt_pmu.pmu.addr_filters_validate = pt_event_addr_filters_validate;
1623 pt_pmu.pmu.nr_addr_filters =
1624 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges);
1626 ret = perf_pmu_register(&pt_pmu.pmu, "intel_pt", -1);
1630 arch_initcall(pt_init);