1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/perf_event.h>
3 #include <linux/types.h>
5 #include <asm/perf_event.h>
9 #include "../perf_event.h"
13 LBR_FORMAT_LIP = 0x01,
14 LBR_FORMAT_EIP = 0x02,
15 LBR_FORMAT_EIP_FLAGS = 0x03,
16 LBR_FORMAT_EIP_FLAGS2 = 0x04,
17 LBR_FORMAT_INFO = 0x05,
18 LBR_FORMAT_TIME = 0x06,
19 LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_TIME,
25 } lbr_desc[LBR_FORMAT_MAX_KNOWN + 1] = {
26 [LBR_FORMAT_EIP_FLAGS] = LBR_EIP_FLAGS,
27 [LBR_FORMAT_EIP_FLAGS2] = LBR_EIP_FLAGS | LBR_TSX,
31 * Intel LBR_SELECT bits
32 * Intel Vol3a, April 2011, Section 16.7 Table 16-10
34 * Hardware branch filter (not available on all CPUs)
36 #define LBR_KERNEL_BIT 0 /* do not capture at ring0 */
37 #define LBR_USER_BIT 1 /* do not capture at ring > 0 */
38 #define LBR_JCC_BIT 2 /* do not capture conditional branches */
39 #define LBR_REL_CALL_BIT 3 /* do not capture relative calls */
40 #define LBR_IND_CALL_BIT 4 /* do not capture indirect calls */
41 #define LBR_RETURN_BIT 5 /* do not capture near returns */
42 #define LBR_IND_JMP_BIT 6 /* do not capture indirect jumps */
43 #define LBR_REL_JMP_BIT 7 /* do not capture relative jumps */
44 #define LBR_FAR_BIT 8 /* do not capture far branches */
45 #define LBR_CALL_STACK_BIT 9 /* enable call stack */
48 * Following bit only exists in Linux; we mask it out before writing it to
49 * the actual MSR. But it helps the constraint perf code to understand
50 * that this is a separate configuration.
52 #define LBR_NO_INFO_BIT 63 /* don't read LBR_INFO. */
54 #define LBR_KERNEL (1 << LBR_KERNEL_BIT)
55 #define LBR_USER (1 << LBR_USER_BIT)
56 #define LBR_JCC (1 << LBR_JCC_BIT)
57 #define LBR_REL_CALL (1 << LBR_REL_CALL_BIT)
58 #define LBR_IND_CALL (1 << LBR_IND_CALL_BIT)
59 #define LBR_RETURN (1 << LBR_RETURN_BIT)
60 #define LBR_REL_JMP (1 << LBR_REL_JMP_BIT)
61 #define LBR_IND_JMP (1 << LBR_IND_JMP_BIT)
62 #define LBR_FAR (1 << LBR_FAR_BIT)
63 #define LBR_CALL_STACK (1 << LBR_CALL_STACK_BIT)
64 #define LBR_NO_INFO (1ULL << LBR_NO_INFO_BIT)
66 #define LBR_PLM (LBR_KERNEL | LBR_USER)
68 #define LBR_SEL_MASK 0x3ff /* valid bits in LBR_SELECT */
69 #define LBR_NOT_SUPP -1 /* LBR filter not supported */
70 #define LBR_IGN 0 /* ignored */
81 #define LBR_FROM_FLAG_MISPRED BIT_ULL(63)
82 #define LBR_FROM_FLAG_IN_TX BIT_ULL(62)
83 #define LBR_FROM_FLAG_ABORT BIT_ULL(61)
85 #define LBR_FROM_SIGNEXT_2MSB (BIT_ULL(60) | BIT_ULL(59))
88 * x86control flow change classification
89 * x86control flow changes include branches, interrupts, traps, faults
92 X86_BR_NONE = 0, /* unknown */
94 X86_BR_USER = 1 << 0, /* branch target is user */
95 X86_BR_KERNEL = 1 << 1, /* branch target is kernel */
97 X86_BR_CALL = 1 << 2, /* call */
98 X86_BR_RET = 1 << 3, /* return */
99 X86_BR_SYSCALL = 1 << 4, /* syscall */
100 X86_BR_SYSRET = 1 << 5, /* syscall return */
101 X86_BR_INT = 1 << 6, /* sw interrupt */
102 X86_BR_IRET = 1 << 7, /* return from interrupt */
103 X86_BR_JCC = 1 << 8, /* conditional */
104 X86_BR_JMP = 1 << 9, /* jump */
105 X86_BR_IRQ = 1 << 10,/* hw interrupt or trap or fault */
106 X86_BR_IND_CALL = 1 << 11,/* indirect calls */
107 X86_BR_ABORT = 1 << 12,/* transaction abort */
108 X86_BR_IN_TX = 1 << 13,/* in transaction */
109 X86_BR_NO_TX = 1 << 14,/* not in transaction */
110 X86_BR_ZERO_CALL = 1 << 15,/* zero length call */
111 X86_BR_CALL_STACK = 1 << 16,/* call stack */
112 X86_BR_IND_JMP = 1 << 17,/* indirect jump */
114 X86_BR_TYPE_SAVE = 1 << 18,/* indicate to save branch type */
118 #define X86_BR_PLM (X86_BR_USER | X86_BR_KERNEL)
119 #define X86_BR_ANYTX (X86_BR_NO_TX | X86_BR_IN_TX)
136 #define X86_BR_ALL (X86_BR_PLM | X86_BR_ANY)
138 #define X86_BR_ANY_CALL \
146 static void intel_pmu_lbr_filter(struct cpu_hw_events *cpuc);
149 * We only support LBR implementations that have FREEZE_LBRS_ON_PMI
150 * otherwise it becomes near impossible to get a reliable stack.
153 static void __intel_pmu_lbr_enable(bool pmi)
155 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
156 u64 debugctl, lbr_select = 0, orig_debugctl;
159 * No need to unfreeze manually, as v4 can do that as part
160 * of the GLOBAL_STATUS ack.
162 if (pmi && x86_pmu.version >= 4)
166 * No need to reprogram LBR_SELECT in a PMI, as it
170 lbr_select = cpuc->lbr_sel->config & x86_pmu.lbr_sel_mask;
171 if (!pmi && cpuc->lbr_sel)
172 wrmsrl(MSR_LBR_SELECT, lbr_select);
174 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
175 orig_debugctl = debugctl;
176 debugctl |= DEBUGCTLMSR_LBR;
178 * LBR callstack does not work well with FREEZE_LBRS_ON_PMI.
179 * If FREEZE_LBRS_ON_PMI is set, PMI near call/return instructions
180 * may cause superfluous increase/decrease of LBR_TOS.
182 if (!(lbr_select & LBR_CALL_STACK))
183 debugctl |= DEBUGCTLMSR_FREEZE_LBRS_ON_PMI;
184 if (orig_debugctl != debugctl)
185 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
188 static void __intel_pmu_lbr_disable(void)
192 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
193 debugctl &= ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
194 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
197 static void intel_pmu_lbr_reset_32(void)
201 for (i = 0; i < x86_pmu.lbr_nr; i++)
202 wrmsrl(x86_pmu.lbr_from + i, 0);
205 static void intel_pmu_lbr_reset_64(void)
209 for (i = 0; i < x86_pmu.lbr_nr; i++) {
210 wrmsrl(x86_pmu.lbr_from + i, 0);
211 wrmsrl(x86_pmu.lbr_to + i, 0);
212 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO)
213 wrmsrl(MSR_LBR_INFO_0 + i, 0);
217 void intel_pmu_lbr_reset(void)
219 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
224 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32)
225 intel_pmu_lbr_reset_32();
227 intel_pmu_lbr_reset_64();
229 cpuc->last_task_ctx = NULL;
230 cpuc->last_log_id = 0;
234 * TOS = most recently recorded branch
236 static inline u64 intel_pmu_lbr_tos(void)
240 rdmsrl(x86_pmu.lbr_tos, tos);
250 * For formats with LBR_TSX flags (e.g. LBR_FORMAT_EIP_FLAGS2), bits 61:62 in
251 * MSR_LAST_BRANCH_FROM_x are the TSX flags when TSX is supported, but when
252 * TSX is not supported they have no consistent behavior:
254 * - For wrmsr(), bits 61:62 are considered part of the sign extension.
255 * - For HW updates (branch captures) bits 61:62 are always OFF and are not
256 * part of the sign extension.
260 * 1) LBR has TSX format
261 * 2) CPU has no TSX support enabled
263 * ... then any value passed to wrmsr() must be sign extended to 63 bits and any
264 * value from rdmsr() must be converted to have a 61 bits sign extension,
265 * ignoring the TSX flags.
267 static inline bool lbr_from_signext_quirk_needed(void)
269 int lbr_format = x86_pmu.intel_cap.lbr_format;
270 bool tsx_support = boot_cpu_has(X86_FEATURE_HLE) ||
271 boot_cpu_has(X86_FEATURE_RTM);
273 return !tsx_support && (lbr_desc[lbr_format] & LBR_TSX);
276 DEFINE_STATIC_KEY_FALSE(lbr_from_quirk_key);
278 /* If quirk is enabled, ensure sign extension is 63 bits: */
279 inline u64 lbr_from_signext_quirk_wr(u64 val)
281 if (static_branch_unlikely(&lbr_from_quirk_key)) {
283 * Sign extend into bits 61:62 while preserving bit 63.
285 * Quirk is enabled when TSX is disabled. Therefore TSX bits
286 * in val are always OFF and must be changed to be sign
287 * extension bits. Since bits 59:60 are guaranteed to be
288 * part of the sign extension bits, we can just copy them
291 val |= (LBR_FROM_SIGNEXT_2MSB & val) << 2;
297 * If quirk is needed, ensure sign extension is 61 bits:
299 static u64 lbr_from_signext_quirk_rd(u64 val)
301 if (static_branch_unlikely(&lbr_from_quirk_key)) {
303 * Quirk is on when TSX is not enabled. Therefore TSX
304 * flags must be read as OFF.
306 val &= ~(LBR_FROM_FLAG_IN_TX | LBR_FROM_FLAG_ABORT);
311 static inline void wrlbr_from(unsigned int idx, u64 val)
313 val = lbr_from_signext_quirk_wr(val);
314 wrmsrl(x86_pmu.lbr_from + idx, val);
317 static inline void wrlbr_to(unsigned int idx, u64 val)
319 wrmsrl(x86_pmu.lbr_to + idx, val);
322 static inline u64 rdlbr_from(unsigned int idx)
326 rdmsrl(x86_pmu.lbr_from + idx, val);
328 return lbr_from_signext_quirk_rd(val);
331 static inline u64 rdlbr_to(unsigned int idx)
335 rdmsrl(x86_pmu.lbr_to + idx, val);
340 static void __intel_pmu_lbr_restore(struct x86_perf_task_context *task_ctx)
342 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
344 unsigned lbr_idx, mask;
347 if (task_ctx->lbr_callstack_users == 0 ||
348 task_ctx->lbr_stack_state == LBR_NONE) {
349 intel_pmu_lbr_reset();
355 * Does not restore the LBR registers, if
356 * - No one else touched them, and
359 if ((task_ctx == cpuc->last_task_ctx) &&
360 (task_ctx->log_id == cpuc->last_log_id) &&
362 task_ctx->lbr_stack_state = LBR_NONE;
366 mask = x86_pmu.lbr_nr - 1;
367 for (i = 0; i < task_ctx->valid_lbrs; i++) {
368 lbr_idx = (tos - i) & mask;
369 wrlbr_from(lbr_idx, task_ctx->lbr_from[i]);
370 wrlbr_to (lbr_idx, task_ctx->lbr_to[i]);
372 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO)
373 wrmsrl(MSR_LBR_INFO_0 + lbr_idx, task_ctx->lbr_info[i]);
376 for (; i < x86_pmu.lbr_nr; i++) {
377 lbr_idx = (tos - i) & mask;
378 wrlbr_from(lbr_idx, 0);
379 wrlbr_to(lbr_idx, 0);
380 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO)
381 wrmsrl(MSR_LBR_INFO_0 + lbr_idx, 0);
384 wrmsrl(x86_pmu.lbr_tos, tos);
385 task_ctx->lbr_stack_state = LBR_NONE;
388 static void __intel_pmu_lbr_save(struct x86_perf_task_context *task_ctx)
390 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
391 unsigned lbr_idx, mask;
395 if (task_ctx->lbr_callstack_users == 0) {
396 task_ctx->lbr_stack_state = LBR_NONE;
400 mask = x86_pmu.lbr_nr - 1;
401 tos = intel_pmu_lbr_tos();
402 for (i = 0; i < x86_pmu.lbr_nr; i++) {
403 lbr_idx = (tos - i) & mask;
404 from = rdlbr_from(lbr_idx);
407 task_ctx->lbr_from[i] = from;
408 task_ctx->lbr_to[i] = rdlbr_to(lbr_idx);
409 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO)
410 rdmsrl(MSR_LBR_INFO_0 + lbr_idx, task_ctx->lbr_info[i]);
412 task_ctx->valid_lbrs = i;
414 task_ctx->lbr_stack_state = LBR_VALID;
416 cpuc->last_task_ctx = task_ctx;
417 cpuc->last_log_id = ++task_ctx->log_id;
420 void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in)
422 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
423 struct x86_perf_task_context *task_ctx;
425 if (!cpuc->lbr_users)
429 * If LBR callstack feature is enabled and the stack was saved when
430 * the task was scheduled out, restore the stack. Otherwise flush
433 task_ctx = ctx ? ctx->task_ctx_data : NULL;
436 __intel_pmu_lbr_restore(task_ctx);
438 __intel_pmu_lbr_save(task_ctx);
443 * Since a context switch can flip the address space and LBR entries
444 * are not tagged with an identifier, we need to wipe the LBR, even for
445 * per-cpu events. You simply cannot resolve the branches from the old
449 intel_pmu_lbr_reset();
452 static inline bool branch_user_callstack(unsigned br_sel)
454 return (br_sel & X86_BR_USER) && (br_sel & X86_BR_CALL_STACK);
457 void intel_pmu_lbr_add(struct perf_event *event)
459 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
460 struct x86_perf_task_context *task_ctx;
465 cpuc->br_sel = event->hw.branch_reg.reg;
467 if (branch_user_callstack(cpuc->br_sel) && event->ctx->task_ctx_data) {
468 task_ctx = event->ctx->task_ctx_data;
469 task_ctx->lbr_callstack_users++;
473 * Request pmu::sched_task() callback, which will fire inside the
474 * regular perf event scheduling, so that call will:
476 * - restore or wipe; when LBR-callstack,
479 * when this is from __perf_event_task_sched_in().
481 * However, if this is from perf_install_in_context(), no such callback
482 * will follow and we'll need to reset the LBR here if this is the
485 * The problem is, we cannot tell these cases apart... but we can
486 * exclude the biggest chunk of cases by looking at
487 * event->total_time_running. An event that has accrued runtime cannot
488 * be 'new'. Conversely, a new event can get installed through the
489 * context switch path for the first time.
491 perf_sched_cb_inc(event->ctx->pmu);
492 if (!cpuc->lbr_users++ && !event->total_time_running)
493 intel_pmu_lbr_reset();
496 void intel_pmu_lbr_del(struct perf_event *event)
498 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
499 struct x86_perf_task_context *task_ctx;
504 if (branch_user_callstack(cpuc->br_sel) &&
505 event->ctx->task_ctx_data) {
506 task_ctx = event->ctx->task_ctx_data;
507 task_ctx->lbr_callstack_users--;
511 WARN_ON_ONCE(cpuc->lbr_users < 0);
512 perf_sched_cb_dec(event->ctx->pmu);
515 void intel_pmu_lbr_enable_all(bool pmi)
517 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
520 __intel_pmu_lbr_enable(pmi);
523 void intel_pmu_lbr_disable_all(void)
525 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
528 __intel_pmu_lbr_disable();
531 static void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc)
533 unsigned long mask = x86_pmu.lbr_nr - 1;
534 u64 tos = intel_pmu_lbr_tos();
537 for (i = 0; i < x86_pmu.lbr_nr; i++) {
538 unsigned long lbr_idx = (tos - i) & mask;
547 rdmsrl(x86_pmu.lbr_from + lbr_idx, msr_lastbranch.lbr);
549 cpuc->lbr_entries[i].from = msr_lastbranch.from;
550 cpuc->lbr_entries[i].to = msr_lastbranch.to;
551 cpuc->lbr_entries[i].mispred = 0;
552 cpuc->lbr_entries[i].predicted = 0;
553 cpuc->lbr_entries[i].in_tx = 0;
554 cpuc->lbr_entries[i].abort = 0;
555 cpuc->lbr_entries[i].cycles = 0;
556 cpuc->lbr_entries[i].type = 0;
557 cpuc->lbr_entries[i].reserved = 0;
559 cpuc->lbr_stack.nr = i;
563 * Due to lack of segmentation in Linux the effective address (offset)
564 * is the same as the linear address, allowing us to merge the LIP and EIP
567 static void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc)
569 bool need_info = false, call_stack = false;
570 unsigned long mask = x86_pmu.lbr_nr - 1;
571 int lbr_format = x86_pmu.intel_cap.lbr_format;
572 u64 tos = intel_pmu_lbr_tos();
575 int num = x86_pmu.lbr_nr;
578 need_info = !(cpuc->lbr_sel->config & LBR_NO_INFO);
579 if (cpuc->lbr_sel->config & LBR_CALL_STACK)
583 for (i = 0; i < num; i++) {
584 unsigned long lbr_idx = (tos - i) & mask;
585 u64 from, to, mis = 0, pred = 0, in_tx = 0, abort = 0;
588 int lbr_flags = lbr_desc[lbr_format];
590 from = rdlbr_from(lbr_idx);
591 to = rdlbr_to(lbr_idx);
594 * Read LBR call stack entries
595 * until invalid entry (0s) is detected.
597 if (call_stack && !from)
600 if (lbr_format == LBR_FORMAT_INFO && need_info) {
603 rdmsrl(MSR_LBR_INFO_0 + lbr_idx, info);
604 mis = !!(info & LBR_INFO_MISPRED);
606 in_tx = !!(info & LBR_INFO_IN_TX);
607 abort = !!(info & LBR_INFO_ABORT);
608 cycles = (info & LBR_INFO_CYCLES);
611 if (lbr_format == LBR_FORMAT_TIME) {
612 mis = !!(from & LBR_FROM_FLAG_MISPRED);
615 cycles = ((to >> 48) & LBR_INFO_CYCLES);
617 to = (u64)((((s64)to) << 16) >> 16);
620 if (lbr_flags & LBR_EIP_FLAGS) {
621 mis = !!(from & LBR_FROM_FLAG_MISPRED);
625 if (lbr_flags & LBR_TSX) {
626 in_tx = !!(from & LBR_FROM_FLAG_IN_TX);
627 abort = !!(from & LBR_FROM_FLAG_ABORT);
630 from = (u64)((((s64)from) << skip) >> skip);
633 * Some CPUs report duplicated abort records,
634 * with the second entry not having an abort bit set.
635 * Skip them here. This loop runs backwards,
636 * so we need to undo the previous record.
637 * If the abort just happened outside the window
638 * the extra entry cannot be removed.
640 if (abort && x86_pmu.lbr_double_abort && out > 0)
643 cpuc->lbr_entries[out].from = from;
644 cpuc->lbr_entries[out].to = to;
645 cpuc->lbr_entries[out].mispred = mis;
646 cpuc->lbr_entries[out].predicted = pred;
647 cpuc->lbr_entries[out].in_tx = in_tx;
648 cpuc->lbr_entries[out].abort = abort;
649 cpuc->lbr_entries[out].cycles = cycles;
650 cpuc->lbr_entries[out].type = 0;
651 cpuc->lbr_entries[out].reserved = 0;
654 cpuc->lbr_stack.nr = out;
657 void intel_pmu_lbr_read(void)
659 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
661 if (!cpuc->lbr_users)
664 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32)
665 intel_pmu_lbr_read_32(cpuc);
667 intel_pmu_lbr_read_64(cpuc);
669 intel_pmu_lbr_filter(cpuc);
674 * - in case there is no HW filter
675 * - in case the HW filter has errata or limitations
677 static int intel_pmu_setup_sw_lbr_filter(struct perf_event *event)
679 u64 br_type = event->attr.branch_sample_type;
682 if (br_type & PERF_SAMPLE_BRANCH_USER)
685 if (br_type & PERF_SAMPLE_BRANCH_KERNEL)
686 mask |= X86_BR_KERNEL;
688 /* we ignore BRANCH_HV here */
690 if (br_type & PERF_SAMPLE_BRANCH_ANY)
693 if (br_type & PERF_SAMPLE_BRANCH_ANY_CALL)
694 mask |= X86_BR_ANY_CALL;
696 if (br_type & PERF_SAMPLE_BRANCH_ANY_RETURN)
697 mask |= X86_BR_RET | X86_BR_IRET | X86_BR_SYSRET;
699 if (br_type & PERF_SAMPLE_BRANCH_IND_CALL)
700 mask |= X86_BR_IND_CALL;
702 if (br_type & PERF_SAMPLE_BRANCH_ABORT_TX)
703 mask |= X86_BR_ABORT;
705 if (br_type & PERF_SAMPLE_BRANCH_IN_TX)
706 mask |= X86_BR_IN_TX;
708 if (br_type & PERF_SAMPLE_BRANCH_NO_TX)
709 mask |= X86_BR_NO_TX;
711 if (br_type & PERF_SAMPLE_BRANCH_COND)
714 if (br_type & PERF_SAMPLE_BRANCH_CALL_STACK) {
715 if (!x86_pmu_has_lbr_callstack())
717 if (mask & ~(X86_BR_USER | X86_BR_KERNEL))
719 mask |= X86_BR_CALL | X86_BR_IND_CALL | X86_BR_RET |
723 if (br_type & PERF_SAMPLE_BRANCH_IND_JUMP)
724 mask |= X86_BR_IND_JMP;
726 if (br_type & PERF_SAMPLE_BRANCH_CALL)
727 mask |= X86_BR_CALL | X86_BR_ZERO_CALL;
729 if (br_type & PERF_SAMPLE_BRANCH_TYPE_SAVE)
730 mask |= X86_BR_TYPE_SAVE;
733 * stash actual user request into reg, it may
734 * be used by fixup code for some CPU
736 event->hw.branch_reg.reg = mask;
741 * setup the HW LBR filter
742 * Used only when available, may not be enough to disambiguate
743 * all branches, may need the help of the SW filter
745 static int intel_pmu_setup_hw_lbr_filter(struct perf_event *event)
747 struct hw_perf_event_extra *reg;
748 u64 br_type = event->attr.branch_sample_type;
752 for (i = 0; i < PERF_SAMPLE_BRANCH_MAX_SHIFT; i++) {
753 if (!(br_type & (1ULL << i)))
756 v = x86_pmu.lbr_sel_map[i];
757 if (v == LBR_NOT_SUPP)
764 reg = &event->hw.branch_reg;
765 reg->idx = EXTRA_REG_LBR;
768 * The first 9 bits (LBR_SEL_MASK) in LBR_SELECT operate
769 * in suppress mode. So LBR_SELECT should be set to
770 * (~mask & LBR_SEL_MASK) | (mask & ~LBR_SEL_MASK)
771 * But the 10th bit LBR_CALL_STACK does not operate
774 reg->config = mask ^ (x86_pmu.lbr_sel_mask & ~LBR_CALL_STACK);
776 if ((br_type & PERF_SAMPLE_BRANCH_NO_CYCLES) &&
777 (br_type & PERF_SAMPLE_BRANCH_NO_FLAGS) &&
778 (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO))
779 reg->config |= LBR_NO_INFO;
784 int intel_pmu_setup_lbr_filter(struct perf_event *event)
795 * setup SW LBR filter
797 ret = intel_pmu_setup_sw_lbr_filter(event);
802 * setup HW LBR filter, if any
804 if (x86_pmu.lbr_sel_map)
805 ret = intel_pmu_setup_hw_lbr_filter(event);
811 * return the type of control flow change at address "from"
812 * instruction is not necessarily a branch (in case of interrupt).
814 * The branch type returned also includes the priv level of the
815 * target of the control flow change (X86_BR_USER, X86_BR_KERNEL).
817 * If a branch type is unknown OR the instruction cannot be
818 * decoded (e.g., text page not present), then X86_BR_NONE is
821 static int branch_type(unsigned long from, unsigned long to, int abort)
825 int bytes_read, bytes_left;
826 int ret = X86_BR_NONE;
827 int ext, to_plm, from_plm;
828 u8 buf[MAX_INSN_SIZE];
831 to_plm = kernel_ip(to) ? X86_BR_KERNEL : X86_BR_USER;
832 from_plm = kernel_ip(from) ? X86_BR_KERNEL : X86_BR_USER;
835 * maybe zero if lbr did not fill up after a reset by the time
836 * we get a PMU interrupt
838 if (from == 0 || to == 0)
842 return X86_BR_ABORT | to_plm;
844 if (from_plm == X86_BR_USER) {
846 * can happen if measuring at the user level only
847 * and we interrupt in a kernel thread, e.g., idle.
852 /* may fail if text not present */
853 bytes_left = copy_from_user_nmi(buf, (void __user *)from,
855 bytes_read = MAX_INSN_SIZE - bytes_left;
862 * The LBR logs any address in the IP, even if the IP just
863 * faulted. This means userspace can control the from address.
864 * Ensure we don't blindy read any address by validating it is
865 * a known text address.
867 if (kernel_text_address(from)) {
870 * Assume we can get the maximum possible size
871 * when grabbing kernel data. This is not
872 * _strictly_ true since we could possibly be
873 * executing up next to a memory hole, but
874 * it is very unlikely to be a problem.
876 bytes_read = MAX_INSN_SIZE;
883 * decoder needs to know the ABI especially
884 * on 64-bit systems running 32-bit apps
887 is64 = kernel_ip((unsigned long)addr) || !test_thread_flag(TIF_IA32);
889 insn_init(&insn, addr, bytes_read, is64);
890 insn_get_opcode(&insn);
891 if (!insn.opcode.got)
894 switch (insn.opcode.bytes[0]) {
896 switch (insn.opcode.bytes[1]) {
897 case 0x05: /* syscall */
898 case 0x34: /* sysenter */
899 ret = X86_BR_SYSCALL;
901 case 0x07: /* sysret */
902 case 0x35: /* sysexit */
905 case 0x80 ... 0x8f: /* conditional */
912 case 0x70 ... 0x7f: /* conditional */
915 case 0xc2: /* near ret */
916 case 0xc3: /* near ret */
917 case 0xca: /* far ret */
918 case 0xcb: /* far ret */
921 case 0xcf: /* iret */
924 case 0xcc ... 0xce: /* int */
927 case 0xe8: /* call near rel */
928 insn_get_immediate(&insn);
929 if (insn.immediate1.value == 0) {
930 /* zero length call */
931 ret = X86_BR_ZERO_CALL;
934 case 0x9a: /* call far absolute */
937 case 0xe0 ... 0xe3: /* loop jmp */
940 case 0xe9 ... 0xeb: /* jmp */
943 case 0xff: /* call near absolute, call far absolute ind */
944 insn_get_modrm(&insn);
945 ext = (insn.modrm.bytes[0] >> 3) & 0x7;
947 case 2: /* near ind call */
948 case 3: /* far ind call */
949 ret = X86_BR_IND_CALL;
953 ret = X86_BR_IND_JMP;
961 * interrupts, traps, faults (and thus ring transition) may
962 * occur on any instructions. Thus, to classify them correctly,
963 * we need to first look at the from and to priv levels. If they
964 * are different and to is in the kernel, then it indicates
965 * a ring transition. If the from instruction is not a ring
966 * transition instr (syscall, systenter, int), then it means
967 * it was a irq, trap or fault.
969 * we have no way of detecting kernel to kernel faults.
971 if (from_plm == X86_BR_USER && to_plm == X86_BR_KERNEL
972 && ret != X86_BR_SYSCALL && ret != X86_BR_INT)
976 * branch priv level determined by target as
977 * is done by HW when LBR_SELECT is implemented
979 if (ret != X86_BR_NONE)
985 #define X86_BR_TYPE_MAP_MAX 16
987 static int branch_map[X86_BR_TYPE_MAP_MAX] = {
988 PERF_BR_CALL, /* X86_BR_CALL */
989 PERF_BR_RET, /* X86_BR_RET */
990 PERF_BR_SYSCALL, /* X86_BR_SYSCALL */
991 PERF_BR_SYSRET, /* X86_BR_SYSRET */
992 PERF_BR_UNKNOWN, /* X86_BR_INT */
993 PERF_BR_UNKNOWN, /* X86_BR_IRET */
994 PERF_BR_COND, /* X86_BR_JCC */
995 PERF_BR_UNCOND, /* X86_BR_JMP */
996 PERF_BR_UNKNOWN, /* X86_BR_IRQ */
997 PERF_BR_IND_CALL, /* X86_BR_IND_CALL */
998 PERF_BR_UNKNOWN, /* X86_BR_ABORT */
999 PERF_BR_UNKNOWN, /* X86_BR_IN_TX */
1000 PERF_BR_UNKNOWN, /* X86_BR_NO_TX */
1001 PERF_BR_CALL, /* X86_BR_ZERO_CALL */
1002 PERF_BR_UNKNOWN, /* X86_BR_CALL_STACK */
1003 PERF_BR_IND, /* X86_BR_IND_JMP */
1007 common_branch_type(int type)
1011 type >>= 2; /* skip X86_BR_USER and X86_BR_KERNEL */
1015 if (i < X86_BR_TYPE_MAP_MAX)
1016 return branch_map[i];
1019 return PERF_BR_UNKNOWN;
1023 * implement actual branch filter based on user demand.
1024 * Hardware may not exactly satisfy that request, thus
1025 * we need to inspect opcodes. Mismatched branches are
1026 * discarded. Therefore, the number of branches returned
1027 * in PERF_SAMPLE_BRANCH_STACK sample may vary.
1030 intel_pmu_lbr_filter(struct cpu_hw_events *cpuc)
1033 int br_sel = cpuc->br_sel;
1035 bool compress = false;
1037 /* if sampling all branches, then nothing to filter */
1038 if (((br_sel & X86_BR_ALL) == X86_BR_ALL) &&
1039 ((br_sel & X86_BR_TYPE_SAVE) != X86_BR_TYPE_SAVE))
1042 for (i = 0; i < cpuc->lbr_stack.nr; i++) {
1044 from = cpuc->lbr_entries[i].from;
1045 to = cpuc->lbr_entries[i].to;
1047 type = branch_type(from, to, cpuc->lbr_entries[i].abort);
1048 if (type != X86_BR_NONE && (br_sel & X86_BR_ANYTX)) {
1049 if (cpuc->lbr_entries[i].in_tx)
1050 type |= X86_BR_IN_TX;
1052 type |= X86_BR_NO_TX;
1055 /* if type does not correspond, then discard */
1056 if (type == X86_BR_NONE || (br_sel & type) != type) {
1057 cpuc->lbr_entries[i].from = 0;
1061 if ((br_sel & X86_BR_TYPE_SAVE) == X86_BR_TYPE_SAVE)
1062 cpuc->lbr_entries[i].type = common_branch_type(type);
1068 /* remove all entries with from=0 */
1069 for (i = 0; i < cpuc->lbr_stack.nr; ) {
1070 if (!cpuc->lbr_entries[i].from) {
1072 while (++j < cpuc->lbr_stack.nr)
1073 cpuc->lbr_entries[j-1] = cpuc->lbr_entries[j];
1074 cpuc->lbr_stack.nr--;
1075 if (!cpuc->lbr_entries[i].from)
1083 * Map interface branch filters onto LBR filters
1085 static const int nhm_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = {
1086 [PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_ANY,
1087 [PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_USER,
1088 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_KERNEL,
1089 [PERF_SAMPLE_BRANCH_HV_SHIFT] = LBR_IGN,
1090 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = LBR_RETURN | LBR_REL_JMP
1091 | LBR_IND_JMP | LBR_FAR,
1093 * NHM/WSM erratum: must include REL_JMP+IND_JMP to get CALL branches
1095 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] =
1096 LBR_REL_CALL | LBR_IND_CALL | LBR_REL_JMP | LBR_IND_JMP | LBR_FAR,
1098 * NHM/WSM erratum: must include IND_JMP to capture IND_CALL
1100 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_IND_CALL | LBR_IND_JMP,
1101 [PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_JCC,
1102 [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = LBR_IND_JMP,
1105 static const int snb_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = {
1106 [PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_ANY,
1107 [PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_USER,
1108 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_KERNEL,
1109 [PERF_SAMPLE_BRANCH_HV_SHIFT] = LBR_IGN,
1110 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = LBR_RETURN | LBR_FAR,
1111 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] = LBR_REL_CALL | LBR_IND_CALL
1113 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_IND_CALL,
1114 [PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_JCC,
1115 [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = LBR_IND_JMP,
1116 [PERF_SAMPLE_BRANCH_CALL_SHIFT] = LBR_REL_CALL,
1119 static const int hsw_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = {
1120 [PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_ANY,
1121 [PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_USER,
1122 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_KERNEL,
1123 [PERF_SAMPLE_BRANCH_HV_SHIFT] = LBR_IGN,
1124 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = LBR_RETURN | LBR_FAR,
1125 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] = LBR_REL_CALL | LBR_IND_CALL
1127 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_IND_CALL,
1128 [PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_JCC,
1129 [PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] = LBR_REL_CALL | LBR_IND_CALL
1130 | LBR_RETURN | LBR_CALL_STACK,
1131 [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = LBR_IND_JMP,
1132 [PERF_SAMPLE_BRANCH_CALL_SHIFT] = LBR_REL_CALL,
1136 void __init intel_pmu_lbr_init_core(void)
1139 x86_pmu.lbr_tos = MSR_LBR_TOS;
1140 x86_pmu.lbr_from = MSR_LBR_CORE_FROM;
1141 x86_pmu.lbr_to = MSR_LBR_CORE_TO;
1144 * SW branch filter usage:
1145 * - compensate for lack of HW filter
1149 /* nehalem/westmere */
1150 void __init intel_pmu_lbr_init_nhm(void)
1152 x86_pmu.lbr_nr = 16;
1153 x86_pmu.lbr_tos = MSR_LBR_TOS;
1154 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
1155 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
1157 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1158 x86_pmu.lbr_sel_map = nhm_lbr_sel_map;
1161 * SW branch filter usage:
1162 * - workaround LBR_SEL errata (see above)
1163 * - support syscall, sysret capture.
1164 * That requires LBR_FAR but that means far
1165 * jmp need to be filtered out
1170 void __init intel_pmu_lbr_init_snb(void)
1172 x86_pmu.lbr_nr = 16;
1173 x86_pmu.lbr_tos = MSR_LBR_TOS;
1174 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
1175 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
1177 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1178 x86_pmu.lbr_sel_map = snb_lbr_sel_map;
1181 * SW branch filter usage:
1182 * - support syscall, sysret capture.
1183 * That requires LBR_FAR but that means far
1184 * jmp need to be filtered out
1189 void intel_pmu_lbr_init_hsw(void)
1191 x86_pmu.lbr_nr = 16;
1192 x86_pmu.lbr_tos = MSR_LBR_TOS;
1193 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
1194 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
1196 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1197 x86_pmu.lbr_sel_map = hsw_lbr_sel_map;
1199 if (lbr_from_signext_quirk_needed())
1200 static_branch_enable(&lbr_from_quirk_key);
1204 __init void intel_pmu_lbr_init_skl(void)
1206 x86_pmu.lbr_nr = 32;
1207 x86_pmu.lbr_tos = MSR_LBR_TOS;
1208 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
1209 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
1211 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1212 x86_pmu.lbr_sel_map = hsw_lbr_sel_map;
1215 * SW branch filter usage:
1216 * - support syscall, sysret capture.
1217 * That requires LBR_FAR but that means far
1218 * jmp need to be filtered out
1223 void __init intel_pmu_lbr_init_atom(void)
1226 * only models starting at stepping 10 seems
1227 * to have an operational LBR which can freeze
1230 if (boot_cpu_data.x86_model == 28
1231 && boot_cpu_data.x86_stepping < 10) {
1232 pr_cont("LBR disabled due to erratum");
1237 x86_pmu.lbr_tos = MSR_LBR_TOS;
1238 x86_pmu.lbr_from = MSR_LBR_CORE_FROM;
1239 x86_pmu.lbr_to = MSR_LBR_CORE_TO;
1242 * SW branch filter usage:
1243 * - compensate for lack of HW filter
1248 void __init intel_pmu_lbr_init_slm(void)
1251 x86_pmu.lbr_tos = MSR_LBR_TOS;
1252 x86_pmu.lbr_from = MSR_LBR_CORE_FROM;
1253 x86_pmu.lbr_to = MSR_LBR_CORE_TO;
1255 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1256 x86_pmu.lbr_sel_map = nhm_lbr_sel_map;
1259 * SW branch filter usage:
1260 * - compensate for lack of HW filter
1262 pr_cont("8-deep LBR, ");
1265 /* Knights Landing */
1266 void intel_pmu_lbr_init_knl(void)
1269 x86_pmu.lbr_tos = MSR_LBR_TOS;
1270 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
1271 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
1273 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1274 x86_pmu.lbr_sel_map = snb_lbr_sel_map;
1276 /* Knights Landing does have MISPREDICT bit */
1277 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_LIP)
1278 x86_pmu.intel_cap.lbr_format = LBR_FORMAT_EIP_FLAGS;