1 #include <linux/bitops.h>
2 #include <linux/types.h>
3 #include <linux/slab.h>
5 #include <asm/perf_event.h>
8 #include "../perf_event.h"
10 /* The size of a BTS record in bytes: */
11 #define BTS_RECORD_SIZE 24
13 #define BTS_BUFFER_SIZE (PAGE_SIZE << 4)
14 #define PEBS_BUFFER_SIZE (PAGE_SIZE << 4)
15 #define PEBS_FIXUP_SIZE PAGE_SIZE
18 * pebs_record_32 for p4 and core not supported
20 struct pebs_record_32 {
28 union intel_x86_pebs_dse {
31 unsigned int ld_dse:4;
32 unsigned int ld_stlb_miss:1;
33 unsigned int ld_locked:1;
34 unsigned int ld_reserved:26;
37 unsigned int st_l1d_hit:1;
38 unsigned int st_reserved1:3;
39 unsigned int st_stlb_miss:1;
40 unsigned int st_locked:1;
41 unsigned int st_reserved2:26;
47 * Map PEBS Load Latency Data Source encodings to generic
48 * memory data source information
50 #define P(a, b) PERF_MEM_S(a, b)
51 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
52 #define LEVEL(x) P(LVLNUM, x)
53 #define REM P(REMOTE, REMOTE)
54 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
56 /* Version for Sandy Bridge and later */
57 static u64 pebs_data_source[] = {
58 P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
59 OP_LH | P(LVL, L1) | LEVEL(L1) | P(SNOOP, NONE), /* 0x01: L1 local */
60 OP_LH | P(LVL, LFB) | LEVEL(LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */
61 OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* 0x03: L2 hit */
62 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
63 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
64 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
65 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
66 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
67 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
68 OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */
69 OP_LH | P(LVL, REM_RAM1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
70 OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | SNOOP_NONE_MISS, /* 0x0c: L3 miss, excl */
71 OP_LH | P(LVL, REM_RAM1) | LEVEL(RAM) | REM | SNOOP_NONE_MISS, /* 0x0d: L3 miss, excl */
72 OP_LH | P(LVL, IO) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0e: I/O */
73 OP_LH | P(LVL, UNC) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0f: uncached */
76 /* Patch up minor differences in the bits */
77 void __init intel_pmu_pebs_data_source_nhm(void)
79 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT);
80 pebs_data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
81 pebs_data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
84 void __init intel_pmu_pebs_data_source_skl(bool pmem)
86 u64 pmem_or_l4 = pmem ? LEVEL(PMEM) : LEVEL(L4);
88 pebs_data_source[0x08] = OP_LH | pmem_or_l4 | P(SNOOP, HIT);
89 pebs_data_source[0x09] = OP_LH | pmem_or_l4 | REM | P(SNOOP, HIT);
90 pebs_data_source[0x0b] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE);
91 pebs_data_source[0x0c] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOPX, FWD);
92 pebs_data_source[0x0d] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOP, HITM);
95 static u64 precise_store_data(u64 status)
97 union intel_x86_pebs_dse dse;
98 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
104 * 1 = stored missed 2nd level TLB
106 * so it either hit the walker or the OS
107 * otherwise hit 2nd level TLB
109 if (dse.st_stlb_miss)
115 * bit 0: hit L1 data cache
116 * if not set, then all we know is that
125 * bit 5: Locked prefix
128 val |= P(LOCK, LOCKED);
133 static u64 precise_datala_hsw(struct perf_event *event, u64 status)
135 union perf_mem_data_src dse;
137 dse.val = PERF_MEM_NA;
139 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
140 dse.mem_op = PERF_MEM_OP_STORE;
141 else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW)
142 dse.mem_op = PERF_MEM_OP_LOAD;
145 * L1 info only valid for following events:
147 * MEM_UOPS_RETIRED.STLB_MISS_STORES
148 * MEM_UOPS_RETIRED.LOCK_STORES
149 * MEM_UOPS_RETIRED.SPLIT_STORES
150 * MEM_UOPS_RETIRED.ALL_STORES
152 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) {
154 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
156 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS;
161 static u64 load_latency_data(u64 status)
163 union intel_x86_pebs_dse dse;
169 * use the mapping table for bit 0-3
171 val = pebs_data_source[dse.ld_dse];
174 * Nehalem models do not support TLB, Lock infos
176 if (x86_pmu.pebs_no_tlb) {
177 val |= P(TLB, NA) | P(LOCK, NA);
182 * 0 = did not miss 2nd level TLB
183 * 1 = missed 2nd level TLB
185 if (dse.ld_stlb_miss)
186 val |= P(TLB, MISS) | P(TLB, L2);
188 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
191 * bit 5: locked prefix
194 val |= P(LOCK, LOCKED);
199 struct pebs_record_core {
203 u64 r8, r9, r10, r11;
204 u64 r12, r13, r14, r15;
207 struct pebs_record_nhm {
211 u64 r8, r9, r10, r11;
212 u64 r12, r13, r14, r15;
213 u64 status, dla, dse, lat;
217 * Same as pebs_record_nhm, with two additional fields.
219 struct pebs_record_hsw {
223 u64 r8, r9, r10, r11;
224 u64 r12, r13, r14, r15;
225 u64 status, dla, dse, lat;
226 u64 real_ip, tsx_tuning;
229 union hsw_tsx_tuning {
231 u32 cycles_last_block : 32,
234 instruction_abort : 1,
235 non_instruction_abort : 1,
244 #define PEBS_HSW_TSX_FLAGS 0xff00000000ULL
246 /* Same as HSW, plus TSC */
248 struct pebs_record_skl {
252 u64 r8, r9, r10, r11;
253 u64 r12, r13, r14, r15;
254 u64 status, dla, dse, lat;
255 u64 real_ip, tsx_tuning;
259 void init_debug_store_on_cpu(int cpu)
261 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
266 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
267 (u32)((u64)(unsigned long)ds),
268 (u32)((u64)(unsigned long)ds >> 32));
271 void fini_debug_store_on_cpu(int cpu)
273 if (!per_cpu(cpu_hw_events, cpu).ds)
276 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
279 static DEFINE_PER_CPU(void *, insn_buffer);
281 static int alloc_pebs_buffer(int cpu)
283 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
284 int node = cpu_to_node(cpu);
286 void *buffer, *ibuffer;
291 buffer = kzalloc_node(x86_pmu.pebs_buffer_size, GFP_KERNEL, node);
292 if (unlikely(!buffer))
296 * HSW+ already provides us the eventing ip; no need to allocate this
299 if (x86_pmu.intel_cap.pebs_format < 2) {
300 ibuffer = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node);
305 per_cpu(insn_buffer, cpu) = ibuffer;
308 max = x86_pmu.pebs_buffer_size / x86_pmu.pebs_record_size;
310 ds->pebs_buffer_base = (u64)(unsigned long)buffer;
311 ds->pebs_index = ds->pebs_buffer_base;
312 ds->pebs_absolute_maximum = ds->pebs_buffer_base +
313 max * x86_pmu.pebs_record_size;
318 static void release_pebs_buffer(int cpu)
320 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
322 if (!ds || !x86_pmu.pebs)
325 kfree(per_cpu(insn_buffer, cpu));
326 per_cpu(insn_buffer, cpu) = NULL;
328 kfree((void *)(unsigned long)ds->pebs_buffer_base);
329 ds->pebs_buffer_base = 0;
332 static int alloc_bts_buffer(int cpu)
334 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
335 int node = cpu_to_node(cpu);
342 buffer = kzalloc_node(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, node);
343 if (unlikely(!buffer)) {
344 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__);
348 max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
351 ds->bts_buffer_base = (u64)(unsigned long)buffer;
352 ds->bts_index = ds->bts_buffer_base;
353 ds->bts_absolute_maximum = ds->bts_buffer_base +
354 max * BTS_RECORD_SIZE;
355 ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
356 thresh * BTS_RECORD_SIZE;
361 static void release_bts_buffer(int cpu)
363 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
365 if (!ds || !x86_pmu.bts)
368 kfree((void *)(unsigned long)ds->bts_buffer_base);
369 ds->bts_buffer_base = 0;
372 static int alloc_ds_buffer(int cpu)
374 int node = cpu_to_node(cpu);
375 struct debug_store *ds;
377 ds = kzalloc_node(sizeof(*ds), GFP_KERNEL, node);
381 per_cpu(cpu_hw_events, cpu).ds = ds;
386 static void release_ds_buffer(int cpu)
388 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
393 per_cpu(cpu_hw_events, cpu).ds = NULL;
397 void release_ds_buffers(void)
401 if (!x86_pmu.bts && !x86_pmu.pebs)
405 for_each_online_cpu(cpu)
406 fini_debug_store_on_cpu(cpu);
408 for_each_possible_cpu(cpu) {
409 release_pebs_buffer(cpu);
410 release_bts_buffer(cpu);
411 release_ds_buffer(cpu);
416 void reserve_ds_buffers(void)
418 int bts_err = 0, pebs_err = 0;
421 x86_pmu.bts_active = 0;
422 x86_pmu.pebs_active = 0;
424 if (!x86_pmu.bts && !x86_pmu.pebs)
435 for_each_possible_cpu(cpu) {
436 if (alloc_ds_buffer(cpu)) {
441 if (!bts_err && alloc_bts_buffer(cpu))
444 if (!pebs_err && alloc_pebs_buffer(cpu))
447 if (bts_err && pebs_err)
452 for_each_possible_cpu(cpu)
453 release_bts_buffer(cpu);
457 for_each_possible_cpu(cpu)
458 release_pebs_buffer(cpu);
461 if (bts_err && pebs_err) {
462 for_each_possible_cpu(cpu)
463 release_ds_buffer(cpu);
465 if (x86_pmu.bts && !bts_err)
466 x86_pmu.bts_active = 1;
468 if (x86_pmu.pebs && !pebs_err)
469 x86_pmu.pebs_active = 1;
471 for_each_online_cpu(cpu)
472 init_debug_store_on_cpu(cpu);
482 struct event_constraint bts_constraint =
483 EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
485 void intel_pmu_enable_bts(u64 config)
487 unsigned long debugctlmsr;
489 debugctlmsr = get_debugctlmsr();
491 debugctlmsr |= DEBUGCTLMSR_TR;
492 debugctlmsr |= DEBUGCTLMSR_BTS;
493 if (config & ARCH_PERFMON_EVENTSEL_INT)
494 debugctlmsr |= DEBUGCTLMSR_BTINT;
496 if (!(config & ARCH_PERFMON_EVENTSEL_OS))
497 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
499 if (!(config & ARCH_PERFMON_EVENTSEL_USR))
500 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
502 update_debugctlmsr(debugctlmsr);
505 void intel_pmu_disable_bts(void)
507 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
508 unsigned long debugctlmsr;
513 debugctlmsr = get_debugctlmsr();
516 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
517 DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
519 update_debugctlmsr(debugctlmsr);
522 int intel_pmu_drain_bts_buffer(void)
524 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
525 struct debug_store *ds = cpuc->ds;
531 struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
532 struct bts_record *at, *base, *top;
533 struct perf_output_handle handle;
534 struct perf_event_header header;
535 struct perf_sample_data data;
536 unsigned long skip = 0;
542 if (!x86_pmu.bts_active)
545 base = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
546 top = (struct bts_record *)(unsigned long)ds->bts_index;
551 memset(®s, 0, sizeof(regs));
553 ds->bts_index = ds->bts_buffer_base;
555 perf_sample_data_init(&data, 0, event->hw.last_period);
558 * BTS leaks kernel addresses in branches across the cpl boundary,
559 * such as traps or system calls, so unless the user is asking for
560 * kernel tracing (and right now it's not possible), we'd need to
561 * filter them out. But first we need to count how many of those we
562 * have in the current batch. This is an extra O(n) pass, however,
563 * it's much faster than the other one especially considering that
564 * n <= 2560 (BTS_BUFFER_SIZE / BTS_RECORD_SIZE * 15/16; see the
565 * alloc_bts_buffer()).
567 for (at = base; at < top; at++) {
569 * Note that right now *this* BTS code only works if
570 * attr::exclude_kernel is set, but let's keep this extra
571 * check here in case that changes.
573 if (event->attr.exclude_kernel &&
574 (kernel_ip(at->from) || kernel_ip(at->to)))
579 * Prepare a generic sample, i.e. fill in the invariant fields.
580 * We will overwrite the from and to address before we output
584 perf_prepare_sample(&header, &data, event, ®s);
586 if (perf_output_begin(&handle, event, header.size *
587 (top - base - skip)))
590 for (at = base; at < top; at++) {
591 /* Filter out any records that contain kernel addresses. */
592 if (event->attr.exclude_kernel &&
593 (kernel_ip(at->from) || kernel_ip(at->to)))
599 perf_output_sample(&handle, &header, &data, event);
602 perf_output_end(&handle);
604 /* There's new data available. */
605 event->hw.interrupts++;
606 event->pending_kill = POLL_IN;
612 static inline void intel_pmu_drain_pebs_buffer(void)
616 x86_pmu.drain_pebs(®s);
622 struct event_constraint intel_core2_pebs_event_constraints[] = {
623 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
624 INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
625 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
626 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
627 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
628 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
629 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
633 struct event_constraint intel_atom_pebs_event_constraints[] = {
634 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
635 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
636 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
637 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
638 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
639 /* Allow all events as PEBS with no flags */
640 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
644 struct event_constraint intel_slm_pebs_event_constraints[] = {
645 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
646 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x1),
647 /* Allow all events as PEBS with no flags */
648 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
652 struct event_constraint intel_glm_pebs_event_constraints[] = {
653 /* Allow all events as PEBS with no flags */
654 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
658 struct event_constraint intel_glp_pebs_event_constraints[] = {
659 /* Allow all events as PEBS with no flags */
660 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
664 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
665 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
666 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
667 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
668 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */
669 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
670 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
671 INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
672 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
673 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
674 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
675 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
676 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
677 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
681 struct event_constraint intel_westmere_pebs_event_constraints[] = {
682 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
683 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
684 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
685 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */
686 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
687 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
688 INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
689 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
690 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
691 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
692 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
693 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
694 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
698 struct event_constraint intel_snb_pebs_event_constraints[] = {
699 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
700 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
701 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
702 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
703 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
704 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
705 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
706 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
707 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
708 /* Allow all events as PEBS with no flags */
709 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
713 struct event_constraint intel_ivb_pebs_event_constraints[] = {
714 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
715 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
716 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
717 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
718 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
719 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
720 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
721 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
722 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
723 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
724 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
725 /* Allow all events as PEBS with no flags */
726 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
730 struct event_constraint intel_hsw_pebs_event_constraints[] = {
731 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
732 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
733 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
734 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
735 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
736 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
737 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
738 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
739 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
740 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
741 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
742 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
743 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
744 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
745 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
746 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
747 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
748 /* Allow all events as PEBS with no flags */
749 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
753 struct event_constraint intel_bdw_pebs_event_constraints[] = {
754 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
755 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
756 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
757 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
758 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
759 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
760 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
761 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
762 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
763 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
764 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
765 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
766 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
767 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
768 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
769 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
770 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
771 /* Allow all events as PEBS with no flags */
772 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
777 struct event_constraint intel_skl_pebs_event_constraints[] = {
778 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
779 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
780 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
781 /* INST_RETIRED.TOTAL_CYCLES_PS (inv=1, cmask=16) (cycles:p). */
782 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
783 INTEL_PLD_CONSTRAINT(0x1cd, 0xf), /* MEM_TRANS_RETIRED.* */
784 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
785 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
786 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
787 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x22d0, 0xf), /* MEM_INST_RETIRED.LOCK_STORES */
788 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
789 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
790 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
791 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
792 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
793 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
794 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_L3_MISS_RETIRED.* */
795 /* Allow all events as PEBS with no flags */
796 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
800 struct event_constraint *intel_pebs_constraints(struct perf_event *event)
802 struct event_constraint *c;
804 if (!event->attr.precise_ip)
807 if (x86_pmu.pebs_constraints) {
808 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
809 if ((event->hw.config & c->cmask) == c->code) {
810 event->hw.flags |= c->flags;
816 return &emptyconstraint;
820 * We need the sched_task callback even for per-cpu events when we use
821 * the large interrupt threshold, such that we can provide PID and TID
824 static inline bool pebs_needs_sched_cb(struct cpu_hw_events *cpuc)
826 return cpuc->n_pebs && (cpuc->n_pebs == cpuc->n_large_pebs);
829 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in)
831 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
833 if (!sched_in && pebs_needs_sched_cb(cpuc))
834 intel_pmu_drain_pebs_buffer();
837 static inline void pebs_update_threshold(struct cpu_hw_events *cpuc)
839 struct debug_store *ds = cpuc->ds;
842 if (cpuc->n_pebs == cpuc->n_large_pebs) {
843 threshold = ds->pebs_absolute_maximum -
844 x86_pmu.max_pebs_events * x86_pmu.pebs_record_size;
846 threshold = ds->pebs_buffer_base + x86_pmu.pebs_record_size;
849 ds->pebs_interrupt_threshold = threshold;
853 pebs_update_state(bool needed_cb, struct cpu_hw_events *cpuc, struct pmu *pmu)
856 * Make sure we get updated with the first PEBS
857 * event. It will trigger also during removal, but
858 * that does not hurt:
860 bool update = cpuc->n_pebs == 1;
862 if (needed_cb != pebs_needs_sched_cb(cpuc)) {
864 perf_sched_cb_inc(pmu);
866 perf_sched_cb_dec(pmu);
872 pebs_update_threshold(cpuc);
875 void intel_pmu_pebs_add(struct perf_event *event)
877 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
878 struct hw_perf_event *hwc = &event->hw;
879 bool needed_cb = pebs_needs_sched_cb(cpuc);
882 if (hwc->flags & PERF_X86_EVENT_FREERUNNING)
883 cpuc->n_large_pebs++;
885 pebs_update_state(needed_cb, cpuc, event->ctx->pmu);
888 void intel_pmu_pebs_enable(struct perf_event *event)
890 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
891 struct hw_perf_event *hwc = &event->hw;
892 struct debug_store *ds = cpuc->ds;
894 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
896 cpuc->pebs_enabled |= 1ULL << hwc->idx;
898 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
899 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
900 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
901 cpuc->pebs_enabled |= 1ULL << 63;
904 * Use auto-reload if possible to save a MSR write in the PMI.
905 * This must be done in pmu::start(), because PERF_EVENT_IOC_PERIOD.
907 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
908 ds->pebs_event_reset[hwc->idx] =
909 (u64)(-hwc->sample_period) & x86_pmu.cntval_mask;
911 ds->pebs_event_reset[hwc->idx] = 0;
915 void intel_pmu_pebs_del(struct perf_event *event)
917 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
918 struct hw_perf_event *hwc = &event->hw;
919 bool needed_cb = pebs_needs_sched_cb(cpuc);
922 if (hwc->flags & PERF_X86_EVENT_FREERUNNING)
923 cpuc->n_large_pebs--;
925 pebs_update_state(needed_cb, cpuc, event->ctx->pmu);
928 void intel_pmu_pebs_disable(struct perf_event *event)
930 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
931 struct hw_perf_event *hwc = &event->hw;
933 if (cpuc->n_pebs == cpuc->n_large_pebs)
934 intel_pmu_drain_pebs_buffer();
936 cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
938 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
939 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
940 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
941 cpuc->pebs_enabled &= ~(1ULL << 63);
944 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
946 hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
949 void intel_pmu_pebs_enable_all(void)
951 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
953 if (cpuc->pebs_enabled)
954 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
957 void intel_pmu_pebs_disable_all(void)
959 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
961 if (cpuc->pebs_enabled)
962 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
965 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
967 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
968 unsigned long from = cpuc->lbr_entries[0].from;
969 unsigned long old_to, to = cpuc->lbr_entries[0].to;
970 unsigned long ip = regs->ip;
976 * We don't need to fixup if the PEBS assist is fault like
978 if (!x86_pmu.intel_cap.pebs_trap)
982 * No LBR entry, no basic block, no rewinding
984 if (!cpuc->lbr_stack.nr || !from || !to)
988 * Basic blocks should never cross user/kernel boundaries
990 if (kernel_ip(ip) != kernel_ip(to))
994 * unsigned math, either ip is before the start (impossible) or
995 * the basic block is larger than 1 page (sanity)
997 if ((ip - to) > PEBS_FIXUP_SIZE)
1001 * We sampled a branch insn, rewind using the LBR stack
1004 set_linear_ip(regs, from);
1009 if (!kernel_ip(ip)) {
1011 u8 *buf = this_cpu_read(insn_buffer);
1013 /* 'size' must fit our buffer, see above */
1014 bytes = copy_from_user_nmi(buf, (void __user *)to, size);
1028 #ifdef CONFIG_X86_64
1029 is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
1031 insn_init(&insn, kaddr, size, is_64bit);
1032 insn_get_length(&insn);
1034 * Make sure there was not a problem decoding the
1035 * instruction and getting the length. This is
1036 * doubly important because we have an infinite
1037 * loop if insn.length=0.
1043 kaddr += insn.length;
1044 size -= insn.length;
1048 set_linear_ip(regs, old_to);
1053 * Even though we decoded the basic block, the instruction stream
1054 * never matched the given IP, either the TO or the IP got corrupted.
1059 static inline u64 intel_hsw_weight(struct pebs_record_skl *pebs)
1061 if (pebs->tsx_tuning) {
1062 union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning };
1063 return tsx.cycles_last_block;
1068 static inline u64 intel_hsw_transaction(struct pebs_record_skl *pebs)
1070 u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
1072 /* For RTM XABORTs also log the abort code from AX */
1073 if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1))
1074 txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
1078 static void setup_pebs_sample_data(struct perf_event *event,
1079 struct pt_regs *iregs, void *__pebs,
1080 struct perf_sample_data *data,
1081 struct pt_regs *regs)
1083 #define PERF_X86_EVENT_PEBS_HSW_PREC \
1084 (PERF_X86_EVENT_PEBS_ST_HSW | \
1085 PERF_X86_EVENT_PEBS_LD_HSW | \
1086 PERF_X86_EVENT_PEBS_NA_HSW)
1088 * We cast to the biggest pebs_record but are careful not to
1089 * unconditionally access the 'extra' entries.
1091 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1092 struct pebs_record_skl *pebs = __pebs;
1095 int fl = event->hw.flags;
1100 sample_type = event->attr.sample_type;
1101 dsrc = sample_type & PERF_SAMPLE_DATA_SRC;
1103 fll = fl & PERF_X86_EVENT_PEBS_LDLAT;
1104 fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC);
1106 perf_sample_data_init(data, 0, event->hw.last_period);
1108 data->period = event->hw.last_period;
1111 * Use latency for weight (only avail with PEBS-LL)
1113 if (fll && (sample_type & PERF_SAMPLE_WEIGHT))
1114 data->weight = pebs->lat;
1117 * data.data_src encodes the data source
1120 u64 val = PERF_MEM_NA;
1122 val = load_latency_data(pebs->dse);
1123 else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC))
1124 val = precise_datala_hsw(event, pebs->dse);
1126 val = precise_store_data(pebs->dse);
1127 data->data_src.val = val;
1131 * We use the interrupt regs as a base because the PEBS record does not
1132 * contain a full regs set, specifically it seems to lack segment
1133 * descriptors, which get used by things like user_mode().
1135 * In the simple case fix up only the IP for PERF_SAMPLE_IP.
1137 * We must however always use BP,SP from iregs for the unwinder to stay
1138 * sane; the record BP,SP can point into thin air when the record is
1139 * from a previous PMI context or an (I)RET happend between the record
1143 regs->flags = pebs->flags;
1144 set_linear_ip(regs, pebs->ip);
1146 if (sample_type & PERF_SAMPLE_REGS_INTR) {
1147 regs->ax = pebs->ax;
1148 regs->bx = pebs->bx;
1149 regs->cx = pebs->cx;
1150 regs->dx = pebs->dx;
1151 regs->si = pebs->si;
1152 regs->di = pebs->di;
1155 * Per the above; only set BP,SP if we don't need callchains.
1157 * XXX: does this make sense?
1159 if (!(sample_type & PERF_SAMPLE_CALLCHAIN)) {
1160 regs->bp = pebs->bp;
1161 regs->sp = pebs->sp;
1165 * Preserve PERF_EFLAGS_VM from set_linear_ip().
1167 regs->flags = pebs->flags | (regs->flags & PERF_EFLAGS_VM);
1168 #ifndef CONFIG_X86_32
1169 regs->r8 = pebs->r8;
1170 regs->r9 = pebs->r9;
1171 regs->r10 = pebs->r10;
1172 regs->r11 = pebs->r11;
1173 regs->r12 = pebs->r12;
1174 regs->r13 = pebs->r13;
1175 regs->r14 = pebs->r14;
1176 regs->r15 = pebs->r15;
1180 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) {
1181 regs->ip = pebs->real_ip;
1182 regs->flags |= PERF_EFLAGS_EXACT;
1183 } else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(regs))
1184 regs->flags |= PERF_EFLAGS_EXACT;
1186 regs->flags &= ~PERF_EFLAGS_EXACT;
1188 if ((sample_type & PERF_SAMPLE_ADDR) &&
1189 x86_pmu.intel_cap.pebs_format >= 1)
1190 data->addr = pebs->dla;
1192 if (x86_pmu.intel_cap.pebs_format >= 2) {
1193 /* Only set the TSX weight when no memory weight. */
1194 if ((sample_type & PERF_SAMPLE_WEIGHT) && !fll)
1195 data->weight = intel_hsw_weight(pebs);
1197 if (sample_type & PERF_SAMPLE_TRANSACTION)
1198 data->txn = intel_hsw_transaction(pebs);
1202 * v3 supplies an accurate time stamp, so we use that
1203 * for the time stamp.
1205 * We can only do this for the default trace clock.
1207 if (x86_pmu.intel_cap.pebs_format >= 3 &&
1208 event->attr.use_clockid == 0)
1209 data->time = native_sched_clock_from_tsc(pebs->tsc);
1211 if (has_branch_stack(event))
1212 data->br_stack = &cpuc->lbr_stack;
1215 static inline void *
1216 get_next_pebs_record_by_bit(void *base, void *top, int bit)
1218 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1223 * fmt0 does not have a status bitfield (does not use
1224 * perf_record_nhm format)
1226 if (x86_pmu.intel_cap.pebs_format < 1)
1232 for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1233 struct pebs_record_nhm *p = at;
1235 if (test_bit(bit, (unsigned long *)&p->status)) {
1236 /* PEBS v3 has accurate status bits */
1237 if (x86_pmu.intel_cap.pebs_format >= 3)
1240 if (p->status == (1 << bit))
1243 /* clear non-PEBS bit and re-check */
1244 pebs_status = p->status & cpuc->pebs_enabled;
1245 pebs_status &= PEBS_COUNTER_MASK;
1246 if (pebs_status == (1 << bit))
1253 static void __intel_pmu_pebs_event(struct perf_event *event,
1254 struct pt_regs *iregs,
1255 void *base, void *top,
1258 struct perf_sample_data data;
1259 struct pt_regs regs;
1260 void *at = get_next_pebs_record_by_bit(base, top, bit);
1262 if (!intel_pmu_save_and_restart(event) &&
1263 !(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD))
1267 setup_pebs_sample_data(event, iregs, at, &data, ®s);
1268 perf_event_output(event, &data, ®s);
1269 at += x86_pmu.pebs_record_size;
1270 at = get_next_pebs_record_by_bit(at, top, bit);
1274 setup_pebs_sample_data(event, iregs, at, &data, ®s);
1277 * All but the last records are processed.
1278 * The last one is left to be able to call the overflow handler.
1280 if (perf_event_overflow(event, &data, ®s)) {
1281 x86_pmu_stop(event, 0);
1287 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
1289 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1290 struct debug_store *ds = cpuc->ds;
1291 struct perf_event *event = cpuc->events[0]; /* PMC0 only */
1292 struct pebs_record_core *at, *top;
1295 if (!x86_pmu.pebs_active)
1298 at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
1299 top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
1302 * Whatever else happens, drain the thing
1304 ds->pebs_index = ds->pebs_buffer_base;
1306 if (!test_bit(0, cpuc->active_mask))
1309 WARN_ON_ONCE(!event);
1311 if (!event->attr.precise_ip)
1318 __intel_pmu_pebs_event(event, iregs, at, top, 0, n);
1321 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
1323 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1324 struct debug_store *ds = cpuc->ds;
1325 struct perf_event *event;
1326 void *base, *at, *top;
1327 short counts[MAX_PEBS_EVENTS] = {};
1328 short error[MAX_PEBS_EVENTS] = {};
1331 if (!x86_pmu.pebs_active)
1334 base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
1335 top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
1337 ds->pebs_index = ds->pebs_buffer_base;
1339 if (unlikely(base >= top))
1342 for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1343 struct pebs_record_nhm *p = at;
1346 pebs_status = p->status & cpuc->pebs_enabled;
1347 pebs_status &= (1ULL << x86_pmu.max_pebs_events) - 1;
1349 /* PEBS v3 has more accurate status bits */
1350 if (x86_pmu.intel_cap.pebs_format >= 3) {
1351 for_each_set_bit(bit, (unsigned long *)&pebs_status,
1352 x86_pmu.max_pebs_events)
1359 * On some CPUs the PEBS status can be zero when PEBS is
1360 * racing with clearing of GLOBAL_STATUS.
1362 * Normally we would drop that record, but in the
1363 * case when there is only a single active PEBS event
1364 * we can assume it's for that event.
1366 if (!pebs_status && cpuc->pebs_enabled &&
1367 !(cpuc->pebs_enabled & (cpuc->pebs_enabled-1)))
1368 pebs_status = cpuc->pebs_enabled;
1370 bit = find_first_bit((unsigned long *)&pebs_status,
1371 x86_pmu.max_pebs_events);
1372 if (bit >= x86_pmu.max_pebs_events)
1376 * The PEBS hardware does not deal well with the situation
1377 * when events happen near to each other and multiple bits
1378 * are set. But it should happen rarely.
1380 * If these events include one PEBS and multiple non-PEBS
1381 * events, it doesn't impact PEBS record. The record will
1382 * be handled normally. (slow path)
1384 * If these events include two or more PEBS events, the
1385 * records for the events can be collapsed into a single
1386 * one, and it's not possible to reconstruct all events
1387 * that caused the PEBS record. It's called collision.
1388 * If collision happened, the record will be dropped.
1390 if (p->status != (1ULL << bit)) {
1391 for_each_set_bit(i, (unsigned long *)&pebs_status,
1392 x86_pmu.max_pebs_events)
1400 for (bit = 0; bit < x86_pmu.max_pebs_events; bit++) {
1401 if ((counts[bit] == 0) && (error[bit] == 0))
1404 event = cpuc->events[bit];
1405 if (WARN_ON_ONCE(!event))
1408 if (WARN_ON_ONCE(!event->attr.precise_ip))
1411 /* log dropped samples number */
1413 perf_log_lost_samples(event, error[bit]);
1415 if (perf_event_account_interrupt(event))
1416 x86_pmu_stop(event, 0);
1420 __intel_pmu_pebs_event(event, iregs, base,
1421 top, bit, counts[bit]);
1427 * BTS, PEBS probe and setup
1430 void __init intel_ds_init(void)
1433 * No support for 32bit formats
1435 if (!boot_cpu_has(X86_FEATURE_DTES64))
1438 x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS);
1439 x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
1440 x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
1442 char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-';
1443 int format = x86_pmu.intel_cap.pebs_format;
1447 pr_cont("PEBS fmt0%c, ", pebs_type);
1448 x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
1450 * Using >PAGE_SIZE buffers makes the WRMSR to
1451 * PERF_GLOBAL_CTRL in intel_pmu_enable_all()
1452 * mysteriously hang on Core2.
1454 * As a workaround, we don't do this.
1456 x86_pmu.pebs_buffer_size = PAGE_SIZE;
1457 x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
1461 pr_cont("PEBS fmt1%c, ", pebs_type);
1462 x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
1463 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1467 pr_cont("PEBS fmt2%c, ", pebs_type);
1468 x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
1469 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1473 pr_cont("PEBS fmt3%c, ", pebs_type);
1474 x86_pmu.pebs_record_size =
1475 sizeof(struct pebs_record_skl);
1476 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1477 x86_pmu.free_running_flags |= PERF_SAMPLE_TIME;
1481 pr_cont("no PEBS fmt%d%c, ", format, pebs_type);
1487 void perf_restore_debug_store(void)
1489 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1491 if (!x86_pmu.bts && !x86_pmu.pebs)
1494 wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);