2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/export.h>
21 #include <linux/init.h>
22 #include <linux/kdebug.h>
23 #include <linux/sched.h>
24 #include <linux/uaccess.h>
25 #include <linux/slab.h>
26 #include <linux/cpu.h>
27 #include <linux/bitops.h>
28 #include <linux/device.h>
31 #include <asm/stacktrace.h>
34 #include <asm/alternative.h>
35 #include <asm/mmu_context.h>
36 #include <asm/tlbflush.h>
37 #include <asm/timer.h>
41 #include "perf_event.h"
43 struct x86_pmu x86_pmu __read_mostly;
45 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
49 struct static_key rdpmc_always_available = STATIC_KEY_INIT_FALSE;
51 u64 __read_mostly hw_cache_event_ids
52 [PERF_COUNT_HW_CACHE_MAX]
53 [PERF_COUNT_HW_CACHE_OP_MAX]
54 [PERF_COUNT_HW_CACHE_RESULT_MAX];
55 u64 __read_mostly hw_cache_extra_regs
56 [PERF_COUNT_HW_CACHE_MAX]
57 [PERF_COUNT_HW_CACHE_OP_MAX]
58 [PERF_COUNT_HW_CACHE_RESULT_MAX];
61 * Propagate event elapsed time into the generic event.
62 * Can only be executed on the CPU where the event is active.
63 * Returns the delta events processed.
65 u64 x86_perf_event_update(struct perf_event *event)
67 struct hw_perf_event *hwc = &event->hw;
68 int shift = 64 - x86_pmu.cntval_bits;
69 u64 prev_raw_count, new_raw_count;
73 if (idx == INTEL_PMC_IDX_FIXED_BTS)
77 * Careful: an NMI might modify the previous event value.
79 * Our tactic to handle this is to first atomically read and
80 * exchange a new raw count - then add that new-prev delta
81 * count to the generic event atomically:
84 prev_raw_count = local64_read(&hwc->prev_count);
85 rdpmcl(hwc->event_base_rdpmc, new_raw_count);
87 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
88 new_raw_count) != prev_raw_count)
92 * Now we have the new raw value and have updated the prev
93 * timestamp already. We can now calculate the elapsed delta
94 * (event-)time and add that to the generic event.
96 * Careful, not all hw sign-extends above the physical width
99 delta = (new_raw_count << shift) - (prev_raw_count << shift);
102 local64_add(delta, &event->count);
103 local64_sub(delta, &hwc->period_left);
105 return new_raw_count;
109 * Find and validate any extra registers to set up.
111 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
113 struct hw_perf_event_extra *reg;
114 struct extra_reg *er;
116 reg = &event->hw.extra_reg;
118 if (!x86_pmu.extra_regs)
121 for (er = x86_pmu.extra_regs; er->msr; er++) {
122 if (er->event != (config & er->config_mask))
124 if (event->attr.config1 & ~er->valid_mask)
126 /* Check if the extra msrs can be safely accessed*/
127 if (!er->extra_msr_access)
131 reg->config = event->attr.config1;
138 static atomic_t active_events;
139 static atomic_t pmc_refcount;
140 static DEFINE_MUTEX(pmc_reserve_mutex);
142 #ifdef CONFIG_X86_LOCAL_APIC
144 static bool reserve_pmc_hardware(void)
148 for (i = 0; i < x86_pmu.num_counters; i++) {
149 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
153 for (i = 0; i < x86_pmu.num_counters; i++) {
154 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
161 for (i--; i >= 0; i--)
162 release_evntsel_nmi(x86_pmu_config_addr(i));
164 i = x86_pmu.num_counters;
167 for (i--; i >= 0; i--)
168 release_perfctr_nmi(x86_pmu_event_addr(i));
173 static void release_pmc_hardware(void)
177 for (i = 0; i < x86_pmu.num_counters; i++) {
178 release_perfctr_nmi(x86_pmu_event_addr(i));
179 release_evntsel_nmi(x86_pmu_config_addr(i));
185 static bool reserve_pmc_hardware(void) { return true; }
186 static void release_pmc_hardware(void) {}
190 static bool check_hw_exists(void)
192 u64 val, val_fail, val_new= ~0;
193 int i, reg, reg_fail, ret = 0;
198 * Check to see if the BIOS enabled any of the counters, if so
201 for (i = 0; i < x86_pmu.num_counters; i++) {
202 reg = x86_pmu_config_addr(i);
203 ret = rdmsrl_safe(reg, &val);
206 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
215 if (x86_pmu.num_counters_fixed) {
216 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
217 ret = rdmsrl_safe(reg, &val);
220 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
221 if (val & (0x03 << i*4)) {
230 * If all the counters are enabled, the below test will always
231 * fail. The tools will also become useless in this scenario.
232 * Just fail and disable the hardware counters.
235 if (reg_safe == -1) {
241 * Read the current value, change it and read it back to see if it
242 * matches, this is needed to detect certain hardware emulators
243 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
245 reg = x86_pmu_event_addr(reg_safe);
246 if (rdmsrl_safe(reg, &val))
249 ret = wrmsrl_safe(reg, val);
250 ret |= rdmsrl_safe(reg, &val_new);
251 if (ret || val != val_new)
255 * We still allow the PMU driver to operate:
258 pr_cont("Broken BIOS detected, complain to your hardware vendor.\n");
259 pr_err(FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n",
266 pr_cont("Broken PMU hardware detected, using software events only.\n");
267 printk("%sFailed to access perfctr msr (MSR %x is %Lx)\n",
268 boot_cpu_has(X86_FEATURE_HYPERVISOR) ? KERN_INFO : KERN_ERR,
274 static void hw_perf_event_destroy(struct perf_event *event)
276 x86_release_hardware();
277 atomic_dec(&active_events);
280 void hw_perf_lbr_event_destroy(struct perf_event *event)
282 hw_perf_event_destroy(event);
284 /* undo the lbr/bts event accounting */
285 x86_del_exclusive(x86_lbr_exclusive_lbr);
288 static inline int x86_pmu_initialized(void)
290 return x86_pmu.handle_irq != NULL;
294 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
296 struct perf_event_attr *attr = &event->attr;
297 unsigned int cache_type, cache_op, cache_result;
300 config = attr->config;
302 cache_type = (config >> 0) & 0xff;
303 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
306 cache_op = (config >> 8) & 0xff;
307 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
310 cache_result = (config >> 16) & 0xff;
311 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
314 val = hw_cache_event_ids[cache_type][cache_op][cache_result];
323 attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
324 return x86_pmu_extra_regs(val, event);
327 int x86_reserve_hardware(void)
331 if (!atomic_inc_not_zero(&pmc_refcount)) {
332 mutex_lock(&pmc_reserve_mutex);
333 if (atomic_read(&pmc_refcount) == 0) {
334 if (!reserve_pmc_hardware())
337 reserve_ds_buffers();
340 atomic_inc(&pmc_refcount);
341 mutex_unlock(&pmc_reserve_mutex);
347 void x86_release_hardware(void)
349 if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) {
350 release_pmc_hardware();
351 release_ds_buffers();
352 mutex_unlock(&pmc_reserve_mutex);
357 * Check if we can create event of a certain type (that no conflicting events
360 int x86_add_exclusive(unsigned int what)
364 if (x86_pmu.lbr_pt_coexist)
367 if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
368 mutex_lock(&pmc_reserve_mutex);
369 for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) {
370 if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i]))
373 atomic_inc(&x86_pmu.lbr_exclusive[what]);
374 mutex_unlock(&pmc_reserve_mutex);
377 atomic_inc(&active_events);
381 mutex_unlock(&pmc_reserve_mutex);
385 void x86_del_exclusive(unsigned int what)
387 if (x86_pmu.lbr_pt_coexist)
390 atomic_dec(&x86_pmu.lbr_exclusive[what]);
391 atomic_dec(&active_events);
394 int x86_setup_perfctr(struct perf_event *event)
396 struct perf_event_attr *attr = &event->attr;
397 struct hw_perf_event *hwc = &event->hw;
400 if (!is_sampling_event(event)) {
401 hwc->sample_period = x86_pmu.max_period;
402 hwc->last_period = hwc->sample_period;
403 local64_set(&hwc->period_left, hwc->sample_period);
406 if (attr->type == PERF_TYPE_RAW)
407 return x86_pmu_extra_regs(event->attr.config, event);
409 if (attr->type == PERF_TYPE_HW_CACHE)
410 return set_ext_hw_attr(hwc, event);
412 if (attr->config >= x86_pmu.max_events)
418 config = x86_pmu.event_map(attr->config);
429 if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
430 !attr->freq && hwc->sample_period == 1) {
431 /* BTS is not supported by this architecture. */
432 if (!x86_pmu.bts_active)
435 /* BTS is currently only allowed for user-mode. */
436 if (!attr->exclude_kernel)
439 /* disallow bts if conflicting events are present */
440 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
443 event->destroy = hw_perf_lbr_event_destroy;
446 hwc->config |= config;
452 * check that branch_sample_type is compatible with
453 * settings needed for precise_ip > 1 which implies
454 * using the LBR to capture ALL taken branches at the
455 * priv levels of the measurement
457 static inline int precise_br_compat(struct perf_event *event)
459 u64 m = event->attr.branch_sample_type;
462 /* must capture all branches */
463 if (!(m & PERF_SAMPLE_BRANCH_ANY))
466 m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
468 if (!event->attr.exclude_user)
469 b |= PERF_SAMPLE_BRANCH_USER;
471 if (!event->attr.exclude_kernel)
472 b |= PERF_SAMPLE_BRANCH_KERNEL;
475 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
481 int x86_pmu_hw_config(struct perf_event *event)
483 if (event->attr.precise_ip) {
486 /* Support for constant skid */
487 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
490 /* Support for IP fixup */
491 if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
494 if (x86_pmu.pebs_prec_dist)
498 if (event->attr.precise_ip > precise)
502 * check that PEBS LBR correction does not conflict with
503 * whatever the user is asking with attr->branch_sample_type
505 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) {
506 u64 *br_type = &event->attr.branch_sample_type;
508 if (has_branch_stack(event)) {
509 if (!precise_br_compat(event))
512 /* branch_sample_type is compatible */
516 * user did not specify branch_sample_type
518 * For PEBS fixups, we capture all
519 * the branches at the priv level of the
522 *br_type = PERF_SAMPLE_BRANCH_ANY;
524 if (!event->attr.exclude_user)
525 *br_type |= PERF_SAMPLE_BRANCH_USER;
527 if (!event->attr.exclude_kernel)
528 *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
532 if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK)
533 event->attach_state |= PERF_ATTACH_TASK_DATA;
537 * (keep 'enabled' bit clear for now)
539 event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
542 * Count user and OS events unless requested not to
544 if (!event->attr.exclude_user)
545 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
546 if (!event->attr.exclude_kernel)
547 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
549 if (event->attr.type == PERF_TYPE_RAW)
550 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
552 if (event->attr.sample_period && x86_pmu.limit_period) {
553 if (x86_pmu.limit_period(event, event->attr.sample_period) >
554 event->attr.sample_period)
558 return x86_setup_perfctr(event);
562 * Setup the hardware configuration for a given attr_type
564 static int __x86_pmu_event_init(struct perf_event *event)
568 if (!x86_pmu_initialized())
571 err = x86_reserve_hardware();
575 atomic_inc(&active_events);
576 event->destroy = hw_perf_event_destroy;
579 event->hw.last_cpu = -1;
580 event->hw.last_tag = ~0ULL;
583 event->hw.extra_reg.idx = EXTRA_REG_NONE;
584 event->hw.branch_reg.idx = EXTRA_REG_NONE;
586 return x86_pmu.hw_config(event);
589 void x86_pmu_disable_all(void)
591 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
594 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
597 if (!test_bit(idx, cpuc->active_mask))
599 rdmsrl(x86_pmu_config_addr(idx), val);
600 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
602 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
603 wrmsrl(x86_pmu_config_addr(idx), val);
608 * There may be PMI landing after enabled=0. The PMI hitting could be before or
611 * If PMI hits before disable_all, the PMU will be disabled in the NMI handler.
612 * It will not be re-enabled in the NMI handler again, because enabled=0. After
613 * handling the NMI, disable_all will be called, which will not change the
614 * state either. If PMI hits after disable_all, the PMU is already disabled
615 * before entering NMI handler. The NMI handler will not change the state
618 * So either situation is harmless.
620 static void x86_pmu_disable(struct pmu *pmu)
622 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
624 if (!x86_pmu_initialized())
634 x86_pmu.disable_all();
637 void x86_pmu_enable_all(int added)
639 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
642 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
643 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
645 if (!test_bit(idx, cpuc->active_mask))
648 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
652 static struct pmu pmu;
654 static inline int is_x86_event(struct perf_event *event)
656 return event->pmu == &pmu;
660 * Event scheduler state:
662 * Assign events iterating over all events and counters, beginning
663 * with events with least weights first. Keep the current iterator
664 * state in struct sched_state.
668 int event; /* event index */
669 int counter; /* counter index */
670 int unassigned; /* number of events to be assigned left */
671 int nr_gp; /* number of GP counters used */
672 unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
675 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
676 #define SCHED_STATES_MAX 2
683 struct event_constraint **constraints;
684 struct sched_state state;
685 struct sched_state saved[SCHED_STATES_MAX];
689 * Initialize interator that runs through all events and counters.
691 static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints,
692 int num, int wmin, int wmax, int gpmax)
696 memset(sched, 0, sizeof(*sched));
697 sched->max_events = num;
698 sched->max_weight = wmax;
699 sched->max_gp = gpmax;
700 sched->constraints = constraints;
702 for (idx = 0; idx < num; idx++) {
703 if (constraints[idx]->weight == wmin)
707 sched->state.event = idx; /* start with min weight */
708 sched->state.weight = wmin;
709 sched->state.unassigned = num;
712 static void perf_sched_save_state(struct perf_sched *sched)
714 if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
717 sched->saved[sched->saved_states] = sched->state;
718 sched->saved_states++;
721 static bool perf_sched_restore_state(struct perf_sched *sched)
723 if (!sched->saved_states)
726 sched->saved_states--;
727 sched->state = sched->saved[sched->saved_states];
729 /* continue with next counter: */
730 clear_bit(sched->state.counter++, sched->state.used);
736 * Select a counter for the current event to schedule. Return true on
739 static bool __perf_sched_find_counter(struct perf_sched *sched)
741 struct event_constraint *c;
744 if (!sched->state.unassigned)
747 if (sched->state.event >= sched->max_events)
750 c = sched->constraints[sched->state.event];
751 /* Prefer fixed purpose counters */
752 if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
753 idx = INTEL_PMC_IDX_FIXED;
754 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
755 if (!__test_and_set_bit(idx, sched->state.used))
760 /* Grab the first unused counter starting with idx */
761 idx = sched->state.counter;
762 for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
763 if (!__test_and_set_bit(idx, sched->state.used)) {
764 if (sched->state.nr_gp++ >= sched->max_gp)
774 sched->state.counter = idx;
777 perf_sched_save_state(sched);
782 static bool perf_sched_find_counter(struct perf_sched *sched)
784 while (!__perf_sched_find_counter(sched)) {
785 if (!perf_sched_restore_state(sched))
793 * Go through all unassigned events and find the next one to schedule.
794 * Take events with the least weight first. Return true on success.
796 static bool perf_sched_next_event(struct perf_sched *sched)
798 struct event_constraint *c;
800 if (!sched->state.unassigned || !--sched->state.unassigned)
805 sched->state.event++;
806 if (sched->state.event >= sched->max_events) {
808 sched->state.event = 0;
809 sched->state.weight++;
810 if (sched->state.weight > sched->max_weight)
813 c = sched->constraints[sched->state.event];
814 } while (c->weight != sched->state.weight);
816 sched->state.counter = 0; /* start with first counter */
822 * Assign a counter for each event.
824 int perf_assign_events(struct event_constraint **constraints, int n,
825 int wmin, int wmax, int gpmax, int *assign)
827 struct perf_sched sched;
829 perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax);
832 if (!perf_sched_find_counter(&sched))
835 assign[sched.state.event] = sched.state.counter;
836 } while (perf_sched_next_event(&sched));
838 return sched.state.unassigned;
840 EXPORT_SYMBOL_GPL(perf_assign_events);
842 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
844 struct event_constraint *c;
845 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
846 struct perf_event *e;
847 int i, wmin, wmax, unsched = 0;
848 struct hw_perf_event *hwc;
850 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
852 if (x86_pmu.start_scheduling)
853 x86_pmu.start_scheduling(cpuc);
855 for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
856 cpuc->event_constraint[i] = NULL;
857 c = x86_pmu.get_event_constraints(cpuc, i, cpuc->event_list[i]);
858 cpuc->event_constraint[i] = c;
860 wmin = min(wmin, c->weight);
861 wmax = max(wmax, c->weight);
865 * fastpath, try to reuse previous register
867 for (i = 0; i < n; i++) {
868 hwc = &cpuc->event_list[i]->hw;
869 c = cpuc->event_constraint[i];
875 /* constraint still honored */
876 if (!test_bit(hwc->idx, c->idxmsk))
879 /* not already used */
880 if (test_bit(hwc->idx, used_mask))
883 __set_bit(hwc->idx, used_mask);
885 assign[i] = hwc->idx;
890 int gpmax = x86_pmu.num_counters;
893 * Do not allow scheduling of more than half the available
896 * This helps avoid counter starvation of sibling thread by
897 * ensuring at most half the counters cannot be in exclusive
898 * mode. There is no designated counters for the limits. Any
899 * N/2 counters can be used. This helps with events with
900 * specific counter constraints.
902 if (is_ht_workaround_enabled() && !cpuc->is_fake &&
903 READ_ONCE(cpuc->excl_cntrs->exclusive_present))
906 unsched = perf_assign_events(cpuc->event_constraint, n, wmin,
907 wmax, gpmax, assign);
911 * In case of success (unsched = 0), mark events as committed,
912 * so we do not put_constraint() in case new events are added
913 * and fail to be scheduled
915 * We invoke the lower level commit callback to lock the resource
917 * We do not need to do all of this in case we are called to
918 * validate an event group (assign == NULL)
920 if (!unsched && assign) {
921 for (i = 0; i < n; i++) {
922 e = cpuc->event_list[i];
923 e->hw.flags |= PERF_X86_EVENT_COMMITTED;
924 if (x86_pmu.commit_scheduling)
925 x86_pmu.commit_scheduling(cpuc, i, assign[i]);
928 for (i = 0; i < n; i++) {
929 e = cpuc->event_list[i];
931 * do not put_constraint() on comitted events,
932 * because they are good to go
934 if ((e->hw.flags & PERF_X86_EVENT_COMMITTED))
938 * release events that failed scheduling
940 if (x86_pmu.put_event_constraints)
941 x86_pmu.put_event_constraints(cpuc, e);
945 if (x86_pmu.stop_scheduling)
946 x86_pmu.stop_scheduling(cpuc);
948 return unsched ? -EINVAL : 0;
952 * dogrp: true if must collect siblings events (group)
953 * returns total number of events and error code
955 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
957 struct perf_event *event;
960 max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
962 /* current number of events already accepted */
965 if (is_x86_event(leader)) {
968 cpuc->event_list[n] = leader;
974 list_for_each_entry(event, &leader->sibling_list, group_entry) {
975 if (!is_x86_event(event) ||
976 event->state <= PERF_EVENT_STATE_OFF)
982 cpuc->event_list[n] = event;
988 static inline void x86_assign_hw_event(struct perf_event *event,
989 struct cpu_hw_events *cpuc, int i)
991 struct hw_perf_event *hwc = &event->hw;
993 hwc->idx = cpuc->assign[i];
994 hwc->last_cpu = smp_processor_id();
995 hwc->last_tag = ++cpuc->tags[i];
997 if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) {
998 hwc->config_base = 0;
1000 } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
1001 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
1002 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED);
1003 hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30;
1005 hwc->config_base = x86_pmu_config_addr(hwc->idx);
1006 hwc->event_base = x86_pmu_event_addr(hwc->idx);
1007 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
1011 static inline int match_prev_assignment(struct hw_perf_event *hwc,
1012 struct cpu_hw_events *cpuc,
1015 return hwc->idx == cpuc->assign[i] &&
1016 hwc->last_cpu == smp_processor_id() &&
1017 hwc->last_tag == cpuc->tags[i];
1020 static void x86_pmu_start(struct perf_event *event, int flags);
1022 static void x86_pmu_enable(struct pmu *pmu)
1024 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1025 struct perf_event *event;
1026 struct hw_perf_event *hwc;
1027 int i, added = cpuc->n_added;
1029 if (!x86_pmu_initialized())
1035 if (cpuc->n_added) {
1036 int n_running = cpuc->n_events - cpuc->n_added;
1038 * apply assignment obtained either from
1039 * hw_perf_group_sched_in() or x86_pmu_enable()
1041 * step1: save events moving to new counters
1043 for (i = 0; i < n_running; i++) {
1044 event = cpuc->event_list[i];
1048 * we can avoid reprogramming counter if:
1049 * - assigned same counter as last time
1050 * - running on same CPU as last time
1051 * - no other event has used the counter since
1053 if (hwc->idx == -1 ||
1054 match_prev_assignment(hwc, cpuc, i))
1058 * Ensure we don't accidentally enable a stopped
1059 * counter simply because we rescheduled.
1061 if (hwc->state & PERF_HES_STOPPED)
1062 hwc->state |= PERF_HES_ARCH;
1064 x86_pmu_stop(event, PERF_EF_UPDATE);
1068 * step2: reprogram moved events into new counters
1070 for (i = 0; i < cpuc->n_events; i++) {
1071 event = cpuc->event_list[i];
1074 if (!match_prev_assignment(hwc, cpuc, i))
1075 x86_assign_hw_event(event, cpuc, i);
1076 else if (i < n_running)
1079 if (hwc->state & PERF_HES_ARCH)
1082 x86_pmu_start(event, PERF_EF_RELOAD);
1085 perf_events_lapic_init();
1091 x86_pmu.enable_all(added);
1094 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1097 * Set the next IRQ period, based on the hwc->period_left value.
1098 * To be called with the event disabled in hw:
1100 int x86_perf_event_set_period(struct perf_event *event)
1102 struct hw_perf_event *hwc = &event->hw;
1103 s64 left = local64_read(&hwc->period_left);
1104 s64 period = hwc->sample_period;
1105 int ret = 0, idx = hwc->idx;
1107 if (idx == INTEL_PMC_IDX_FIXED_BTS)
1111 * If we are way outside a reasonable range then just skip forward:
1113 if (unlikely(left <= -period)) {
1115 local64_set(&hwc->period_left, left);
1116 hwc->last_period = period;
1120 if (unlikely(left <= 0)) {
1122 local64_set(&hwc->period_left, left);
1123 hwc->last_period = period;
1127 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1129 if (unlikely(left < 2))
1132 if (left > x86_pmu.max_period)
1133 left = x86_pmu.max_period;
1135 if (x86_pmu.limit_period)
1136 left = x86_pmu.limit_period(event, left);
1138 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1140 if (!(hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) ||
1141 local64_read(&hwc->prev_count) != (u64)-left) {
1143 * The hw event starts counting from this event offset,
1144 * mark it to be able to extra future deltas:
1146 local64_set(&hwc->prev_count, (u64)-left);
1148 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1152 * Due to erratum on certan cpu we need
1153 * a second write to be sure the register
1154 * is updated properly
1156 if (x86_pmu.perfctr_second_write) {
1157 wrmsrl(hwc->event_base,
1158 (u64)(-left) & x86_pmu.cntval_mask);
1161 perf_event_update_userpage(event);
1166 void x86_pmu_enable_event(struct perf_event *event)
1168 if (__this_cpu_read(cpu_hw_events.enabled))
1169 __x86_pmu_enable_event(&event->hw,
1170 ARCH_PERFMON_EVENTSEL_ENABLE);
1174 * Add a single event to the PMU.
1176 * The event is added to the group of enabled events
1177 * but only if it can be scehduled with existing events.
1179 static int x86_pmu_add(struct perf_event *event, int flags)
1181 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1182 struct hw_perf_event *hwc;
1183 int assign[X86_PMC_IDX_MAX];
1188 n0 = cpuc->n_events;
1189 ret = n = collect_events(cpuc, event, false);
1193 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1194 if (!(flags & PERF_EF_START))
1195 hwc->state |= PERF_HES_ARCH;
1198 * If group events scheduling transaction was started,
1199 * skip the schedulability test here, it will be performed
1200 * at commit time (->commit_txn) as a whole.
1202 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1205 ret = x86_pmu.schedule_events(cpuc, n, assign);
1209 * copy new assignment, now we know it is possible
1210 * will be used by hw_perf_enable()
1212 memcpy(cpuc->assign, assign, n*sizeof(int));
1216 * Commit the collect_events() state. See x86_pmu_del() and
1220 cpuc->n_added += n - n0;
1221 cpuc->n_txn += n - n0;
1228 static void x86_pmu_start(struct perf_event *event, int flags)
1230 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1231 int idx = event->hw.idx;
1233 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1236 if (WARN_ON_ONCE(idx == -1))
1239 if (flags & PERF_EF_RELOAD) {
1240 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1241 x86_perf_event_set_period(event);
1244 event->hw.state = 0;
1246 cpuc->events[idx] = event;
1247 __set_bit(idx, cpuc->active_mask);
1248 __set_bit(idx, cpuc->running);
1249 x86_pmu.enable(event);
1250 perf_event_update_userpage(event);
1253 void perf_event_print_debug(void)
1255 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1257 struct cpu_hw_events *cpuc;
1258 unsigned long flags;
1261 if (!x86_pmu.num_counters)
1264 local_irq_save(flags);
1266 cpu = smp_processor_id();
1267 cpuc = &per_cpu(cpu_hw_events, cpu);
1269 if (x86_pmu.version >= 2) {
1270 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1271 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1272 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1273 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1276 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1277 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1278 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1279 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1280 if (x86_pmu.pebs_constraints) {
1281 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1282 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
1284 if (x86_pmu.lbr_nr) {
1285 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1286 pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl);
1289 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1291 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1292 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1293 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1295 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1297 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1298 cpu, idx, pmc_ctrl);
1299 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1300 cpu, idx, pmc_count);
1301 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1302 cpu, idx, prev_left);
1304 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1305 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1307 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1308 cpu, idx, pmc_count);
1310 local_irq_restore(flags);
1313 void x86_pmu_stop(struct perf_event *event, int flags)
1315 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1316 struct hw_perf_event *hwc = &event->hw;
1318 if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1319 x86_pmu.disable(event);
1320 cpuc->events[hwc->idx] = NULL;
1321 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1322 hwc->state |= PERF_HES_STOPPED;
1325 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1327 * Drain the remaining delta count out of a event
1328 * that we are disabling:
1330 x86_perf_event_update(event);
1331 hwc->state |= PERF_HES_UPTODATE;
1335 static void x86_pmu_del(struct perf_event *event, int flags)
1337 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1341 * event is descheduled
1343 event->hw.flags &= ~PERF_X86_EVENT_COMMITTED;
1346 * If we're called during a txn, we don't need to do anything.
1347 * The events never got scheduled and ->cancel_txn will truncate
1350 * XXX assumes any ->del() called during a TXN will only be on
1351 * an event added during that same TXN.
1353 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1357 * Not a TXN, therefore cleanup properly.
1359 x86_pmu_stop(event, PERF_EF_UPDATE);
1361 for (i = 0; i < cpuc->n_events; i++) {
1362 if (event == cpuc->event_list[i])
1366 if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
1369 /* If we have a newly added event; make sure to decrease n_added. */
1370 if (i >= cpuc->n_events - cpuc->n_added)
1373 if (x86_pmu.put_event_constraints)
1374 x86_pmu.put_event_constraints(cpuc, event);
1376 /* Delete the array entry. */
1377 while (++i < cpuc->n_events) {
1378 cpuc->event_list[i-1] = cpuc->event_list[i];
1379 cpuc->event_constraint[i-1] = cpuc->event_constraint[i];
1383 perf_event_update_userpage(event);
1386 int x86_pmu_handle_irq(struct pt_regs *regs)
1388 struct perf_sample_data data;
1389 struct cpu_hw_events *cpuc;
1390 struct perf_event *event;
1391 int idx, handled = 0;
1394 cpuc = this_cpu_ptr(&cpu_hw_events);
1397 * Some chipsets need to unmask the LVTPC in a particular spot
1398 * inside the nmi handler. As a result, the unmasking was pushed
1399 * into all the nmi handlers.
1401 * This generic handler doesn't seem to have any issues where the
1402 * unmasking occurs so it was left at the top.
1404 apic_write(APIC_LVTPC, APIC_DM_NMI);
1406 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1407 if (!test_bit(idx, cpuc->active_mask)) {
1409 * Though we deactivated the counter some cpus
1410 * might still deliver spurious interrupts still
1411 * in flight. Catch them:
1413 if (__test_and_clear_bit(idx, cpuc->running))
1418 event = cpuc->events[idx];
1420 val = x86_perf_event_update(event);
1421 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1428 perf_sample_data_init(&data, 0, event->hw.last_period);
1430 if (!x86_perf_event_set_period(event))
1433 if (perf_event_overflow(event, &data, regs))
1434 x86_pmu_stop(event, 0);
1438 inc_irq_stat(apic_perf_irqs);
1443 void perf_events_lapic_init(void)
1445 if (!x86_pmu.apic || !x86_pmu_initialized())
1449 * Always use NMI for PMU
1451 apic_write(APIC_LVTPC, APIC_DM_NMI);
1455 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1462 * All PMUs/events that share this PMI handler should make sure to
1463 * increment active_events for their events.
1465 if (!atomic_read(&active_events))
1468 start_clock = sched_clock();
1469 ret = x86_pmu.handle_irq(regs);
1470 finish_clock = sched_clock();
1472 perf_sample_event_took(finish_clock - start_clock);
1476 NOKPROBE_SYMBOL(perf_event_nmi_handler);
1478 struct event_constraint emptyconstraint;
1479 struct event_constraint unconstrained;
1481 static int x86_pmu_prepare_cpu(unsigned int cpu)
1483 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1486 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++)
1487 cpuc->kfree_on_online[i] = NULL;
1488 if (x86_pmu.cpu_prepare)
1489 return x86_pmu.cpu_prepare(cpu);
1493 static int x86_pmu_dead_cpu(unsigned int cpu)
1495 if (x86_pmu.cpu_dead)
1496 x86_pmu.cpu_dead(cpu);
1500 static int x86_pmu_online_cpu(unsigned int cpu)
1502 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1505 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) {
1506 kfree(cpuc->kfree_on_online[i]);
1507 cpuc->kfree_on_online[i] = NULL;
1512 static int x86_pmu_starting_cpu(unsigned int cpu)
1514 if (x86_pmu.cpu_starting)
1515 x86_pmu.cpu_starting(cpu);
1519 static int x86_pmu_dying_cpu(unsigned int cpu)
1521 if (x86_pmu.cpu_dying)
1522 x86_pmu.cpu_dying(cpu);
1526 static void __init pmu_check_apic(void)
1528 if (boot_cpu_has(X86_FEATURE_APIC))
1532 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1533 pr_info("no hardware sampling interrupt available.\n");
1536 * If we have a PMU initialized but no APIC
1537 * interrupts, we cannot sample hardware
1538 * events (user-space has to fall back and
1539 * sample via a hrtimer based software event):
1541 pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1545 static struct attribute_group x86_pmu_format_group = {
1551 * Remove all undefined events (x86_pmu.event_map(id) == 0)
1552 * out of events_attr attributes.
1554 static void __init filter_events(struct attribute **attrs)
1556 struct device_attribute *d;
1557 struct perf_pmu_events_attr *pmu_attr;
1561 for (i = 0; attrs[i]; i++) {
1562 d = (struct device_attribute *)attrs[i];
1563 pmu_attr = container_of(d, struct perf_pmu_events_attr, attr);
1565 if (pmu_attr->event_str)
1567 if (x86_pmu.event_map(i + offset))
1570 for (j = i; attrs[j]; j++)
1571 attrs[j] = attrs[j + 1];
1573 /* Check the shifted attr. */
1577 * event_map() is index based, the attrs array is organized
1578 * by increasing event index. If we shift the events, then
1579 * we need to compensate for the event_map(), otherwise
1580 * we are looking up the wrong event in the map
1586 /* Merge two pointer arrays */
1587 __init struct attribute **merge_attr(struct attribute **a, struct attribute **b)
1589 struct attribute **new;
1592 for (j = 0; a[j]; j++)
1594 for (i = 0; b[i]; i++)
1598 new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL);
1603 for (i = 0; a[i]; i++)
1605 for (i = 0; b[i]; i++)
1612 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, char *page)
1614 struct perf_pmu_events_attr *pmu_attr = \
1615 container_of(attr, struct perf_pmu_events_attr, attr);
1616 u64 config = x86_pmu.event_map(pmu_attr->id);
1618 /* string trumps id */
1619 if (pmu_attr->event_str)
1620 return sprintf(page, "%s", pmu_attr->event_str);
1622 return x86_pmu.events_sysfs_show(page, config);
1624 EXPORT_SYMBOL_GPL(events_sysfs_show);
1626 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr,
1629 struct perf_pmu_events_ht_attr *pmu_attr =
1630 container_of(attr, struct perf_pmu_events_ht_attr, attr);
1633 * Report conditional events depending on Hyper-Threading.
1635 * This is overly conservative as usually the HT special
1636 * handling is not needed if the other CPU thread is idle.
1638 * Note this does not (and cannot) handle the case when thread
1639 * siblings are invisible, for example with virtualization
1640 * if they are owned by some other guest. The user tool
1641 * has to re-read when a thread sibling gets onlined later.
1643 return sprintf(page, "%s",
1644 topology_max_smt_threads() > 1 ?
1645 pmu_attr->event_str_ht :
1646 pmu_attr->event_str_noht);
1649 EVENT_ATTR(cpu-cycles, CPU_CYCLES );
1650 EVENT_ATTR(instructions, INSTRUCTIONS );
1651 EVENT_ATTR(cache-references, CACHE_REFERENCES );
1652 EVENT_ATTR(cache-misses, CACHE_MISSES );
1653 EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS );
1654 EVENT_ATTR(branch-misses, BRANCH_MISSES );
1655 EVENT_ATTR(bus-cycles, BUS_CYCLES );
1656 EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND );
1657 EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND );
1658 EVENT_ATTR(ref-cycles, REF_CPU_CYCLES );
1660 static struct attribute *empty_attrs;
1662 static struct attribute *events_attr[] = {
1663 EVENT_PTR(CPU_CYCLES),
1664 EVENT_PTR(INSTRUCTIONS),
1665 EVENT_PTR(CACHE_REFERENCES),
1666 EVENT_PTR(CACHE_MISSES),
1667 EVENT_PTR(BRANCH_INSTRUCTIONS),
1668 EVENT_PTR(BRANCH_MISSES),
1669 EVENT_PTR(BUS_CYCLES),
1670 EVENT_PTR(STALLED_CYCLES_FRONTEND),
1671 EVENT_PTR(STALLED_CYCLES_BACKEND),
1672 EVENT_PTR(REF_CPU_CYCLES),
1676 static struct attribute_group x86_pmu_events_group = {
1678 .attrs = events_attr,
1681 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1683 u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1684 u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1685 bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1686 bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1687 bool any = (config & ARCH_PERFMON_EVENTSEL_ANY);
1688 bool inv = (config & ARCH_PERFMON_EVENTSEL_INV);
1692 * We have whole page size to spend and just little data
1693 * to write, so we can safely use sprintf.
1695 ret = sprintf(page, "event=0x%02llx", event);
1698 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1701 ret += sprintf(page + ret, ",edge");
1704 ret += sprintf(page + ret, ",pc");
1707 ret += sprintf(page + ret, ",any");
1710 ret += sprintf(page + ret, ",inv");
1713 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
1715 ret += sprintf(page + ret, "\n");
1720 static int __init init_hw_perf_events(void)
1722 struct x86_pmu_quirk *quirk;
1725 pr_info("Performance Events: ");
1727 switch (boot_cpu_data.x86_vendor) {
1728 case X86_VENDOR_INTEL:
1729 err = intel_pmu_init();
1731 case X86_VENDOR_AMD:
1732 err = amd_pmu_init();
1738 pr_cont("no PMU driver, software events only.\n");
1744 /* sanity check that the hardware exists or is emulated */
1745 if (!check_hw_exists())
1748 pr_cont("%s PMU driver.\n", x86_pmu.name);
1750 x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
1752 for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
1755 if (!x86_pmu.intel_ctrl)
1756 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1758 perf_events_lapic_init();
1759 register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1761 unconstrained = (struct event_constraint)
1762 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1763 0, x86_pmu.num_counters, 0, 0);
1765 x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1767 if (x86_pmu.event_attrs)
1768 x86_pmu_events_group.attrs = x86_pmu.event_attrs;
1770 if (!x86_pmu.events_sysfs_show)
1771 x86_pmu_events_group.attrs = &empty_attrs;
1773 filter_events(x86_pmu_events_group.attrs);
1775 if (x86_pmu.cpu_events) {
1776 struct attribute **tmp;
1778 tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events);
1780 x86_pmu_events_group.attrs = tmp;
1783 pr_info("... version: %d\n", x86_pmu.version);
1784 pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
1785 pr_info("... generic registers: %d\n", x86_pmu.num_counters);
1786 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask);
1787 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
1788 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed);
1789 pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl);
1792 * Install callbacks. Core will call them for each online
1795 err = cpuhp_setup_state(CPUHP_PERF_X86_PREPARE, "PERF_X86_PREPARE",
1796 x86_pmu_prepare_cpu, x86_pmu_dead_cpu);
1800 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_STARTING,
1801 "AP_PERF_X86_STARTING", x86_pmu_starting_cpu,
1806 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_ONLINE, "AP_PERF_X86_ONLINE",
1807 x86_pmu_online_cpu, NULL);
1811 err = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1818 cpuhp_remove_state(CPUHP_AP_PERF_X86_ONLINE);
1820 cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING);
1822 cpuhp_remove_state(CPUHP_PERF_X86_PREPARE);
1825 early_initcall(init_hw_perf_events);
1827 static inline void x86_pmu_read(struct perf_event *event)
1829 x86_perf_event_update(event);
1833 * Start group events scheduling transaction
1834 * Set the flag to make pmu::enable() not perform the
1835 * schedulability test, it will be performed at commit time
1837 * We only support PERF_PMU_TXN_ADD transactions. Save the
1838 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
1841 static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
1843 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1845 WARN_ON_ONCE(cpuc->txn_flags); /* txn already in flight */
1847 cpuc->txn_flags = txn_flags;
1848 if (txn_flags & ~PERF_PMU_TXN_ADD)
1851 perf_pmu_disable(pmu);
1852 __this_cpu_write(cpu_hw_events.n_txn, 0);
1856 * Stop group events scheduling transaction
1857 * Clear the flag and pmu::enable() will perform the
1858 * schedulability test.
1860 static void x86_pmu_cancel_txn(struct pmu *pmu)
1862 unsigned int txn_flags;
1863 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1865 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
1867 txn_flags = cpuc->txn_flags;
1868 cpuc->txn_flags = 0;
1869 if (txn_flags & ~PERF_PMU_TXN_ADD)
1873 * Truncate collected array by the number of events added in this
1874 * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1876 __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1877 __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1878 perf_pmu_enable(pmu);
1882 * Commit group events scheduling transaction
1883 * Perform the group schedulability test as a whole
1884 * Return 0 if success
1886 * Does not cancel the transaction on failure; expects the caller to do this.
1888 static int x86_pmu_commit_txn(struct pmu *pmu)
1890 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1891 int assign[X86_PMC_IDX_MAX];
1894 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
1896 if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) {
1897 cpuc->txn_flags = 0;
1903 if (!x86_pmu_initialized())
1906 ret = x86_pmu.schedule_events(cpuc, n, assign);
1911 * copy new assignment, now we know it is possible
1912 * will be used by hw_perf_enable()
1914 memcpy(cpuc->assign, assign, n*sizeof(int));
1916 cpuc->txn_flags = 0;
1917 perf_pmu_enable(pmu);
1921 * a fake_cpuc is used to validate event groups. Due to
1922 * the extra reg logic, we need to also allocate a fake
1923 * per_core and per_cpu structure. Otherwise, group events
1924 * using extra reg may conflict without the kernel being
1925 * able to catch this when the last event gets added to
1928 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
1930 kfree(cpuc->shared_regs);
1934 static struct cpu_hw_events *allocate_fake_cpuc(void)
1936 struct cpu_hw_events *cpuc;
1937 int cpu = raw_smp_processor_id();
1939 cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
1941 return ERR_PTR(-ENOMEM);
1943 /* only needed, if we have extra_regs */
1944 if (x86_pmu.extra_regs) {
1945 cpuc->shared_regs = allocate_shared_regs(cpu);
1946 if (!cpuc->shared_regs)
1952 free_fake_cpuc(cpuc);
1953 return ERR_PTR(-ENOMEM);
1957 * validate that we can schedule this event
1959 static int validate_event(struct perf_event *event)
1961 struct cpu_hw_events *fake_cpuc;
1962 struct event_constraint *c;
1965 fake_cpuc = allocate_fake_cpuc();
1966 if (IS_ERR(fake_cpuc))
1967 return PTR_ERR(fake_cpuc);
1969 c = x86_pmu.get_event_constraints(fake_cpuc, -1, event);
1971 if (!c || !c->weight)
1974 if (x86_pmu.put_event_constraints)
1975 x86_pmu.put_event_constraints(fake_cpuc, event);
1977 free_fake_cpuc(fake_cpuc);
1983 * validate a single event group
1985 * validation include:
1986 * - check events are compatible which each other
1987 * - events do not compete for the same counter
1988 * - number of events <= number of counters
1990 * validation ensures the group can be loaded onto the
1991 * PMU if it was the only group available.
1993 static int validate_group(struct perf_event *event)
1995 struct perf_event *leader = event->group_leader;
1996 struct cpu_hw_events *fake_cpuc;
1997 int ret = -EINVAL, n;
1999 fake_cpuc = allocate_fake_cpuc();
2000 if (IS_ERR(fake_cpuc))
2001 return PTR_ERR(fake_cpuc);
2003 * the event is not yet connected with its
2004 * siblings therefore we must first collect
2005 * existing siblings, then add the new event
2006 * before we can simulate the scheduling
2008 n = collect_events(fake_cpuc, leader, true);
2012 fake_cpuc->n_events = n;
2013 n = collect_events(fake_cpuc, event, false);
2017 fake_cpuc->n_events = n;
2019 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
2022 free_fake_cpuc(fake_cpuc);
2026 static int x86_pmu_event_init(struct perf_event *event)
2031 switch (event->attr.type) {
2033 case PERF_TYPE_HARDWARE:
2034 case PERF_TYPE_HW_CACHE:
2041 err = __x86_pmu_event_init(event);
2044 * we temporarily connect event to its pmu
2045 * such that validate_group() can classify
2046 * it as an x86 event using is_x86_event()
2051 if (event->group_leader != event)
2052 err = validate_group(event);
2054 err = validate_event(event);
2060 event->destroy(event);
2063 if (ACCESS_ONCE(x86_pmu.attr_rdpmc))
2064 event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED;
2069 static void refresh_pce(void *ignored)
2072 load_mm_cr4(current->mm);
2075 static void x86_pmu_event_mapped(struct perf_event *event)
2077 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2080 if (atomic_inc_return(¤t->mm->context.perf_rdpmc_allowed) == 1)
2081 on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1);
2084 static void x86_pmu_event_unmapped(struct perf_event *event)
2089 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2092 if (atomic_dec_and_test(¤t->mm->context.perf_rdpmc_allowed))
2093 on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1);
2096 static int x86_pmu_event_idx(struct perf_event *event)
2098 int idx = event->hw.idx;
2100 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2103 if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) {
2104 idx -= INTEL_PMC_IDX_FIXED;
2111 static ssize_t get_attr_rdpmc(struct device *cdev,
2112 struct device_attribute *attr,
2115 return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
2118 static ssize_t set_attr_rdpmc(struct device *cdev,
2119 struct device_attribute *attr,
2120 const char *buf, size_t count)
2125 ret = kstrtoul(buf, 0, &val);
2132 if (x86_pmu.attr_rdpmc_broken)
2135 if ((val == 2) != (x86_pmu.attr_rdpmc == 2)) {
2137 * Changing into or out of always available, aka
2138 * perf-event-bypassing mode. This path is extremely slow,
2139 * but only root can trigger it, so it's okay.
2142 static_key_slow_inc(&rdpmc_always_available);
2144 static_key_slow_dec(&rdpmc_always_available);
2145 on_each_cpu(refresh_pce, NULL, 1);
2148 x86_pmu.attr_rdpmc = val;
2153 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
2155 static struct attribute *x86_pmu_attrs[] = {
2156 &dev_attr_rdpmc.attr,
2160 static struct attribute_group x86_pmu_attr_group = {
2161 .attrs = x86_pmu_attrs,
2164 static const struct attribute_group *x86_pmu_attr_groups[] = {
2165 &x86_pmu_attr_group,
2166 &x86_pmu_format_group,
2167 &x86_pmu_events_group,
2171 static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
2173 if (x86_pmu.sched_task)
2174 x86_pmu.sched_task(ctx, sched_in);
2177 void perf_check_microcode(void)
2179 if (x86_pmu.check_microcode)
2180 x86_pmu.check_microcode();
2182 EXPORT_SYMBOL_GPL(perf_check_microcode);
2184 static struct pmu pmu = {
2185 .pmu_enable = x86_pmu_enable,
2186 .pmu_disable = x86_pmu_disable,
2188 .attr_groups = x86_pmu_attr_groups,
2190 .event_init = x86_pmu_event_init,
2192 .event_mapped = x86_pmu_event_mapped,
2193 .event_unmapped = x86_pmu_event_unmapped,
2197 .start = x86_pmu_start,
2198 .stop = x86_pmu_stop,
2199 .read = x86_pmu_read,
2201 .start_txn = x86_pmu_start_txn,
2202 .cancel_txn = x86_pmu_cancel_txn,
2203 .commit_txn = x86_pmu_commit_txn,
2205 .event_idx = x86_pmu_event_idx,
2206 .sched_task = x86_pmu_sched_task,
2207 .task_ctx_size = sizeof(struct x86_perf_task_context),
2210 void arch_perf_update_userpage(struct perf_event *event,
2211 struct perf_event_mmap_page *userpg, u64 now)
2213 struct cyc2ns_data *data;
2215 userpg->cap_user_time = 0;
2216 userpg->cap_user_time_zero = 0;
2217 userpg->cap_user_rdpmc =
2218 !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED);
2219 userpg->pmc_width = x86_pmu.cntval_bits;
2221 if (!sched_clock_stable())
2224 data = cyc2ns_read_begin();
2227 * Internal timekeeping for enabled/running/stopped times
2228 * is always in the local_clock domain.
2230 userpg->cap_user_time = 1;
2231 userpg->time_mult = data->cyc2ns_mul;
2232 userpg->time_shift = data->cyc2ns_shift;
2233 userpg->time_offset = data->cyc2ns_offset - now;
2236 * cap_user_time_zero doesn't make sense when we're using a different
2237 * time base for the records.
2239 if (!event->attr.use_clockid) {
2240 userpg->cap_user_time_zero = 1;
2241 userpg->time_zero = data->cyc2ns_offset;
2244 cyc2ns_read_end(data);
2251 static int backtrace_stack(void *data, char *name)
2256 static int backtrace_address(void *data, unsigned long addr, int reliable)
2258 struct perf_callchain_entry_ctx *entry = data;
2260 return perf_callchain_store(entry, addr);
2263 static const struct stacktrace_ops backtrace_ops = {
2264 .stack = backtrace_stack,
2265 .address = backtrace_address,
2266 .walk_stack = print_context_stack_bp,
2270 perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2272 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2273 /* TODO: We don't support guest os callchain now */
2277 perf_callchain_store(entry, regs->ip);
2279 dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
2283 valid_user_frame(const void __user *fp, unsigned long size)
2285 return (__range_not_ok(fp, size, TASK_SIZE) == 0);
2288 static unsigned long get_segment_base(unsigned int segment)
2290 struct desc_struct *desc;
2291 int idx = segment >> 3;
2293 if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2294 #ifdef CONFIG_MODIFY_LDT_SYSCALL
2295 struct ldt_struct *ldt;
2297 if (idx > LDT_ENTRIES)
2300 /* IRQs are off, so this synchronizes with smp_store_release */
2301 ldt = lockless_dereference(current->active_mm->context.ldt);
2302 if (!ldt || idx > ldt->size)
2305 desc = &ldt->entries[idx];
2310 if (idx > GDT_ENTRIES)
2313 desc = raw_cpu_ptr(gdt_page.gdt) + idx;
2316 return get_desc_base(desc);
2319 #ifdef CONFIG_IA32_EMULATION
2321 #include <asm/compat.h>
2324 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2326 /* 32-bit process in 64-bit kernel. */
2327 unsigned long ss_base, cs_base;
2328 struct stack_frame_ia32 frame;
2329 const void __user *fp;
2331 if (!test_thread_flag(TIF_IA32))
2334 cs_base = get_segment_base(regs->cs);
2335 ss_base = get_segment_base(regs->ss);
2337 fp = compat_ptr(ss_base + regs->bp);
2338 pagefault_disable();
2339 while (entry->nr < entry->max_stack) {
2340 unsigned long bytes;
2341 frame.next_frame = 0;
2342 frame.return_address = 0;
2344 if (!access_ok(VERIFY_READ, fp, 8))
2347 bytes = __copy_from_user_nmi(&frame.next_frame, fp, 4);
2350 bytes = __copy_from_user_nmi(&frame.return_address, fp+4, 4);
2354 if (!valid_user_frame(fp, sizeof(frame)))
2357 perf_callchain_store(entry, cs_base + frame.return_address);
2358 fp = compat_ptr(ss_base + frame.next_frame);
2365 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2372 perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2374 struct stack_frame frame;
2375 const unsigned long __user *fp;
2377 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2378 /* TODO: We don't support guest os callchain now */
2383 * We don't know what to do with VM86 stacks.. ignore them for now.
2385 if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2388 fp = (unsigned long __user *)regs->bp;
2390 perf_callchain_store(entry, regs->ip);
2395 if (perf_callchain_user32(regs, entry))
2398 pagefault_disable();
2399 while (entry->nr < entry->max_stack) {
2400 unsigned long bytes;
2402 frame.next_frame = NULL;
2403 frame.return_address = 0;
2405 if (!access_ok(VERIFY_READ, fp, sizeof(*fp) * 2))
2408 bytes = __copy_from_user_nmi(&frame.next_frame, fp, sizeof(*fp));
2411 bytes = __copy_from_user_nmi(&frame.return_address, fp + 1, sizeof(*fp));
2415 if (!valid_user_frame(fp, sizeof(frame)))
2418 perf_callchain_store(entry, frame.return_address);
2419 fp = (void __user *)frame.next_frame;
2425 * Deal with code segment offsets for the various execution modes:
2427 * VM86 - the good olde 16 bit days, where the linear address is
2428 * 20 bits and we use regs->ip + 0x10 * regs->cs.
2430 * IA32 - Where we need to look at GDT/LDT segment descriptor tables
2431 * to figure out what the 32bit base address is.
2433 * X32 - has TIF_X32 set, but is running in x86_64
2435 * X86_64 - CS,DS,SS,ES are all zero based.
2437 static unsigned long code_segment_base(struct pt_regs *regs)
2440 * For IA32 we look at the GDT/LDT segment base to convert the
2441 * effective IP to a linear address.
2444 #ifdef CONFIG_X86_32
2446 * If we are in VM86 mode, add the segment offset to convert to a
2449 if (regs->flags & X86_VM_MASK)
2450 return 0x10 * regs->cs;
2452 if (user_mode(regs) && regs->cs != __USER_CS)
2453 return get_segment_base(regs->cs);
2455 if (user_mode(regs) && !user_64bit_mode(regs) &&
2456 regs->cs != __USER32_CS)
2457 return get_segment_base(regs->cs);
2462 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2464 if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
2465 return perf_guest_cbs->get_guest_ip();
2467 return regs->ip + code_segment_base(regs);
2470 unsigned long perf_misc_flags(struct pt_regs *regs)
2474 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2475 if (perf_guest_cbs->is_user_mode())
2476 misc |= PERF_RECORD_MISC_GUEST_USER;
2478 misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2480 if (user_mode(regs))
2481 misc |= PERF_RECORD_MISC_USER;
2483 misc |= PERF_RECORD_MISC_KERNEL;
2486 if (regs->flags & PERF_EFLAGS_EXACT)
2487 misc |= PERF_RECORD_MISC_EXACT_IP;
2492 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2494 cap->version = x86_pmu.version;
2495 cap->num_counters_gp = x86_pmu.num_counters;
2496 cap->num_counters_fixed = x86_pmu.num_counters_fixed;
2497 cap->bit_width_gp = x86_pmu.cntval_bits;
2498 cap->bit_width_fixed = x86_pmu.cntval_bits;
2499 cap->events_mask = (unsigned int)x86_pmu.events_maskl;
2500 cap->events_mask_len = x86_pmu.events_mask_len;
2502 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);