arch/x86/events/core.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/cpu.h>
  26 #include <linux/bitops.h>
  27 #include <linux/device.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/stacktrace.h>
  31 #include <asm/nmi.h>
  32 #include <asm/smp.h>
  33 #include <asm/alternative.h>
  34 #include <asm/mmu_context.h>
  35 #include <asm/tlbflush.h>
  36 #include <asm/timer.h>
  37 #include <asm/desc.h>
  38 #include <asm/ldt.h>
  39
  40 #include "perf_event.h"
  41
  42 struct x86_pmu x86_pmu __read_mostly;
  43
  44 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
  45         .enabled = 1,
  46 };
  47
  48 struct static_key rdpmc_always_available = STATIC_KEY_INIT_FALSE;
  49
  50 u64 __read_mostly hw_cache_event_ids
  51                                 [PERF_COUNT_HW_CACHE_MAX]
  52                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  53                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  54 u64 __read_mostly hw_cache_extra_regs
  55                                 [PERF_COUNT_HW_CACHE_MAX]
  56                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  57                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  58
  59 /*
  60  * Propagate event elapsed time into the generic event.
  61  * Can only be executed on the CPU where the event is active.
  62  * Returns the delta events processed.
  63  */
  64 u64 x86_perf_event_update(struct perf_event *event)
  65 {
  66         struct hw_perf_event *hwc = &event->hw;
  67         int shift = 64 - x86_pmu.cntval_bits;
  68         u64 prev_raw_count, new_raw_count;
  69         int idx = hwc->idx;
  70         s64 delta;
  71
  72         if (idx == INTEL_PMC_IDX_FIXED_BTS)
  73                 return 0;
  74
  75         /*
  76          * Careful: an NMI might modify the previous event value.
  77          *
  78          * Our tactic to handle this is to first atomically read and
  79          * exchange a new raw count - then add that new-prev delta
  80          * count to the generic event atomically:
  81          */
  82 again:
  83         prev_raw_count = local64_read(&hwc->prev_count);
  84         rdpmcl(hwc->event_base_rdpmc, new_raw_count);
  85
  86         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
  87                                         new_raw_count) != prev_raw_count)
  88                 goto again;
  89
  90         /*
  91          * Now we have the new raw value and have updated the prev
  92          * timestamp already. We can now calculate the elapsed delta
  93          * (event-)time and add that to the generic event.
  94          *
  95          * Careful, not all hw sign-extends above the physical width
  96          * of the count.
  97          */
  98         delta = (new_raw_count << shift) - (prev_raw_count << shift);
  99         delta >>= shift;
 100
 101         local64_add(delta, &event->count);
 102         local64_sub(delta, &hwc->period_left);
 103
 104         return new_raw_count;
 105 }
 106
 107 /*
 108  * Find and validate any extra registers to set up.
 109  */
 110 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
 111 {
 112         struct hw_perf_event_extra *reg;
 113         struct extra_reg *er;
 114
 115         reg = &event->hw.extra_reg;
 116
 117         if (!x86_pmu.extra_regs)
 118                 return 0;
 119
 120         for (er = x86_pmu.extra_regs; er->msr; er++) {
 121                 if (er->event != (config & er->config_mask))
 122                         continue;
 123                 if (event->attr.config1 & ~er->valid_mask)
 124                         return -EINVAL;
 125                 /* Check if the extra msrs can be safely accessed*/
 126                 if (!er->extra_msr_access)
 127                         return -ENXIO;
 128
 129                 reg->idx = er->idx;
 130                 reg->config = event->attr.config1;
 131                 reg->reg = er->msr;
 132                 break;
 133         }
 134         return 0;
 135 }
 136
 137 static atomic_t active_events;
 138 static atomic_t pmc_refcount;
 139 static DEFINE_MUTEX(pmc_reserve_mutex);
 140
 141 #ifdef CONFIG_X86_LOCAL_APIC
 142
 143 static bool reserve_pmc_hardware(void)
 144 {
 145         int i;
 146
 147         for (i = 0; i < x86_pmu.num_counters; i++) {
 148                 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
 149                         goto perfctr_fail;
 150         }
 151
 152         for (i = 0; i < x86_pmu.num_counters; i++) {
 153                 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
 154                         goto eventsel_fail;
 155         }
 156
 157         return true;
 158
 159 eventsel_fail:
 160         for (i--; i >= 0; i--)
 161                 release_evntsel_nmi(x86_pmu_config_addr(i));
 162
 163         i = x86_pmu.num_counters;
 164
 165 perfctr_fail:
 166         for (i--; i >= 0; i--)
 167                 release_perfctr_nmi(x86_pmu_event_addr(i));
 168
 169         return false;
 170 }
 171
 172 static void release_pmc_hardware(void)
 173 {
 174         int i;
 175
 176         for (i = 0; i < x86_pmu.num_counters; i++) {
 177                 release_perfctr_nmi(x86_pmu_event_addr(i));
 178                 release_evntsel_nmi(x86_pmu_config_addr(i));
 179         }
 180 }
 181
 182 #else
 183
 184 static bool reserve_pmc_hardware(void) { return true; }
 185 static void release_pmc_hardware(void) {}
 186
 187 #endif
 188
 189 static bool check_hw_exists(void)
 190 {
 191         u64 val, val_fail, val_new= ~0;
 192         int i, reg, reg_fail, ret = 0;
 193         int bios_fail = 0;
 194         int reg_safe = -1;
 195
 196         /*
 197          * Check to see if the BIOS enabled any of the counters, if so
 198          * complain and bail.
 199          */
 200         for (i = 0; i < x86_pmu.num_counters; i++) {
 201                 reg = x86_pmu_config_addr(i);
 202                 ret = rdmsrl_safe(reg, &val);
 203                 if (ret)
 204                         goto msr_fail;
 205                 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
 206                         bios_fail = 1;
 207                         val_fail = val;
 208                         reg_fail = reg;
 209                 } else {
 210                         reg_safe = i;
 211                 }
 212         }
 213
 214         if (x86_pmu.num_counters_fixed) {
 215                 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 216                 ret = rdmsrl_safe(reg, &val);
 217                 if (ret)
 218                         goto msr_fail;
 219                 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
 220                         if (val & (0x03 << i*4)) {
 221                                 bios_fail = 1;
 222                                 val_fail = val;
 223                                 reg_fail = reg;
 224                         }
 225                 }
 226         }
 227
 228         /*
 229          * If all the counters are enabled, the below test will always
 230          * fail.  The tools will also become useless in this scenario.
 231          * Just fail and disable the hardware counters.
 232          */
 233
 234         if (reg_safe == -1) {
 235                 reg = reg_safe;
 236                 goto msr_fail;
 237         }
 238
 239         /*
 240          * Read the current value, change it and read it back to see if it
 241          * matches, this is needed to detect certain hardware emulators
 242          * (qemu/kvm) that don't trap on the MSR access and always return 0s.
 243          */
 244         reg = x86_pmu_event_addr(reg_safe);
 245         if (rdmsrl_safe(reg, &val))
 246                 goto msr_fail;
 247         val ^= 0xffffUL;
 248         ret = wrmsrl_safe(reg, val);
 249         ret |= rdmsrl_safe(reg, &val_new);
 250         if (ret || val != val_new)
 251                 goto msr_fail;
 252
 253         /*
 254          * We still allow the PMU driver to operate:
 255          */
 256         if (bios_fail) {
 257                 pr_cont("Broken BIOS detected, complain to your hardware vendor.\n");
 258                 pr_err(FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n",
 259                               reg_fail, val_fail);
 260         }
 261
 262         return true;
 263
 264 msr_fail:
 265         if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
 266                 pr_cont("PMU not available due to virtualization, using software events only.\n");
 267         } else {
 268                 pr_cont("Broken PMU hardware detected, using software events only.\n");
 269                 pr_err("Failed to access perfctr msr (MSR %x is %Lx)\n",
 270                        reg, val_new);
 271         }
 272
 273         return false;
 274 }
 275
 276 static void hw_perf_event_destroy(struct perf_event *event)
 277 {
 278         x86_release_hardware();
 279         atomic_dec(&active_events);
 280 }
 281
 282 void hw_perf_lbr_event_destroy(struct perf_event *event)
 283 {
 284         hw_perf_event_destroy(event);
 285
 286         /* undo the lbr/bts event accounting */
 287         x86_del_exclusive(x86_lbr_exclusive_lbr);
 288 }
 289
 290 static inline int x86_pmu_initialized(void)
 291 {
 292         return x86_pmu.handle_irq != NULL;
 293 }
 294
 295 static inline int
 296 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
 297 {
 298         struct perf_event_attr *attr = &event->attr;
 299         unsigned int cache_type, cache_op, cache_result;
 300         u64 config, val;
 301
 302         config = attr->config;
 303
 304         cache_type = (config >>  0) & 0xff;
 305         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 306                 return -EINVAL;
 307
 308         cache_op = (config >>  8) & 0xff;
 309         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 310                 return -EINVAL;
 311
 312         cache_result = (config >> 16) & 0xff;
 313         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 314                 return -EINVAL;
 315
 316         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 317
 318         if (val == 0)
 319                 return -ENOENT;
 320
 321         if (val == -1)
 322                 return -EINVAL;
 323
 324         hwc->config |= val;
 325         attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
 326         return x86_pmu_extra_regs(val, event);
 327 }
 328
 329 int x86_reserve_hardware(void)
 330 {
 331         int err = 0;
 332
 333         if (!atomic_inc_not_zero(&pmc_refcount)) {
 334                 mutex_lock(&pmc_reserve_mutex);
 335                 if (atomic_read(&pmc_refcount) == 0) {
 336                         if (!reserve_pmc_hardware())
 337                                 err = -EBUSY;
 338                         else
 339                                 reserve_ds_buffers();
 340                 }
 341                 if (!err)
 342                         atomic_inc(&pmc_refcount);
 343                 mutex_unlock(&pmc_reserve_mutex);
 344         }
 345
 346         return err;
 347 }
 348
 349 void x86_release_hardware(void)
 350 {
 351         if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) {
 352                 release_pmc_hardware();
 353                 release_ds_buffers();
 354                 mutex_unlock(&pmc_reserve_mutex);
 355         }
 356 }
 357
 358 /*
 359  * Check if we can create event of a certain type (that no conflicting events
 360  * are present).
 361  */
 362 int x86_add_exclusive(unsigned int what)
 363 {
 364         int i;
 365
 366         if (x86_pmu.lbr_pt_coexist)
 367                 return 0;
 368
 369         if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
 370                 mutex_lock(&pmc_reserve_mutex);
 371                 for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) {
 372                         if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i]))
 373                                 goto fail_unlock;
 374                 }
 375                 atomic_inc(&x86_pmu.lbr_exclusive[what]);
 376                 mutex_unlock(&pmc_reserve_mutex);
 377         }
 378
 379         atomic_inc(&active_events);
 380         return 0;
 381
 382 fail_unlock:
 383         mutex_unlock(&pmc_reserve_mutex);
 384         return -EBUSY;
 385 }
 386
 387 void x86_del_exclusive(unsigned int what)
 388 {
 389         if (x86_pmu.lbr_pt_coexist)
 390                 return;
 391
 392         atomic_dec(&x86_pmu.lbr_exclusive[what]);
 393         atomic_dec(&active_events);
 394 }
 395
 396 int x86_setup_perfctr(struct perf_event *event)
 397 {
 398         struct perf_event_attr *attr = &event->attr;
 399         struct hw_perf_event *hwc = &event->hw;
 400         u64 config;
 401
 402         if (!is_sampling_event(event)) {
 403                 hwc->sample_period = x86_pmu.max_period;
 404                 hwc->last_period = hwc->sample_period;
 405                 local64_set(&hwc->period_left, hwc->sample_period);
 406         }
 407
 408         if (attr->type == PERF_TYPE_RAW)
 409                 return x86_pmu_extra_regs(event->attr.config, event);
 410
 411         if (attr->type == PERF_TYPE_HW_CACHE)
 412                 return set_ext_hw_attr(hwc, event);
 413
 414         if (attr->config >= x86_pmu.max_events)
 415                 return -EINVAL;
 416
 417         /*
 418          * The generic map:
 419          */
 420         config = x86_pmu.event_map(attr->config);
 421
 422         if (config == 0)
 423                 return -ENOENT;
 424
 425         if (config == -1LL)
 426                 return -EINVAL;
 427
 428         /*
 429          * Branch tracing:
 430          */
 431         if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
 432             !attr->freq && hwc->sample_period == 1) {
 433                 /* BTS is not supported by this architecture. */
 434                 if (!x86_pmu.bts_active)
 435                         return -EOPNOTSUPP;
 436
 437                 /* BTS is currently only allowed for user-mode. */
 438                 if (!attr->exclude_kernel)
 439                         return -EOPNOTSUPP;
 440
 441                 /* disallow bts if conflicting events are present */
 442                 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
 443                         return -EBUSY;
 444
 445                 event->destroy = hw_perf_lbr_event_destroy;
 446         }
 447
 448         hwc->config |= config;
 449
 450         return 0;
 451 }
 452
 453 /*
 454  * check that branch_sample_type is compatible with
 455  * settings needed for precise_ip > 1 which implies
 456  * using the LBR to capture ALL taken branches at the
 457  * priv levels of the measurement
 458  */
 459 static inline int precise_br_compat(struct perf_event *event)
 460 {
 461         u64 m = event->attr.branch_sample_type;
 462         u64 b = 0;
 463
 464         /* must capture all branches */
 465         if (!(m & PERF_SAMPLE_BRANCH_ANY))
 466                 return 0;
 467
 468         m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
 469
 470         if (!event->attr.exclude_user)
 471                 b |= PERF_SAMPLE_BRANCH_USER;
 472
 473         if (!event->attr.exclude_kernel)
 474                 b |= PERF_SAMPLE_BRANCH_KERNEL;
 475
 476         /*
 477          * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
 478          */
 479
 480         return m == b;
 481 }
 482
 483 int x86_pmu_hw_config(struct perf_event *event)
 484 {
 485         if (event->attr.precise_ip) {
 486                 int precise = 0;
 487
 488                 /* Support for constant skid */
 489                 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
 490                         precise++;
 491
 492                         /* Support for IP fixup */
 493                         if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
 494                                 precise++;
 495
 496                         if (x86_pmu.pebs_prec_dist)
 497                                 precise++;
 498                 }
 499
 500                 if (event->attr.precise_ip > precise)
 501                         return -EOPNOTSUPP;
 502         }
 503         /*
 504          * check that PEBS LBR correction does not conflict with
 505          * whatever the user is asking with attr->branch_sample_type
 506          */
 507         if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) {
 508                 u64 *br_type = &event->attr.branch_sample_type;
 509
 510                 if (has_branch_stack(event)) {
 511                         if (!precise_br_compat(event))
 512                                 return -EOPNOTSUPP;
 513
 514                         /* branch_sample_type is compatible */
 515
 516                 } else {
 517                         /*
 518                          * user did not specify  branch_sample_type
 519                          *
 520                          * For PEBS fixups, we capture all
 521                          * the branches at the priv level of the
 522                          * event.
 523                          */
 524                         *br_type = PERF_SAMPLE_BRANCH_ANY;
 525
 526                         if (!event->attr.exclude_user)
 527                                 *br_type |= PERF_SAMPLE_BRANCH_USER;
 528
 529                         if (!event->attr.exclude_kernel)
 530                                 *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
 531                 }
 532         }
 533
 534         if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK)
 535                 event->attach_state |= PERF_ATTACH_TASK_DATA;
 536
 537         /*
 538          * Generate PMC IRQs:
 539          * (keep 'enabled' bit clear for now)
 540          */
 541         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
 542
 543         /*
 544          * Count user and OS events unless requested not to
 545          */
 546         if (!event->attr.exclude_user)
 547                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
 548         if (!event->attr.exclude_kernel)
 549                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
 550
 551         if (event->attr.type == PERF_TYPE_RAW)
 552                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
 553
 554         if (event->attr.sample_period && x86_pmu.limit_period) {
 555                 if (x86_pmu.limit_period(event, event->attr.sample_period) >
 556                                 event->attr.sample_period)
 557                         return -EINVAL;
 558         }
 559
 560         return x86_setup_perfctr(event);
 561 }
 562
 563 /*
 564  * Setup the hardware configuration for a given attr_type
 565  */
 566 static int __x86_pmu_event_init(struct perf_event *event)
 567 {
 568         int err;
 569
 570         if (!x86_pmu_initialized())
 571                 return -ENODEV;
 572
 573         err = x86_reserve_hardware();
 574         if (err)
 575                 return err;
 576
 577         atomic_inc(&active_events);
 578         event->destroy = hw_perf_event_destroy;
 579
 580         event->hw.idx = -1;
 581         event->hw.last_cpu = -1;
 582         event->hw.last_tag = ~0ULL;
 583
 584         /* mark unused */
 585         event->hw.extra_reg.idx = EXTRA_REG_NONE;
 586         event->hw.branch_reg.idx = EXTRA_REG_NONE;
 587
 588         return x86_pmu.hw_config(event);
 589 }
 590
 591 void x86_pmu_disable_all(void)
 592 {
 593         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 594         int idx;
 595
 596         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 597                 u64 val;
 598
 599                 if (!test_bit(idx, cpuc->active_mask))
 600                         continue;
 601                 rdmsrl(x86_pmu_config_addr(idx), val);
 602                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 603                         continue;
 604                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 605                 wrmsrl(x86_pmu_config_addr(idx), val);
 606         }
 607 }
 608
 609 /*
 610  * There may be PMI landing after enabled=0. The PMI hitting could be before or
 611  * after disable_all.
 612  *
 613  * If PMI hits before disable_all, the PMU will be disabled in the NMI handler.
 614  * It will not be re-enabled in the NMI handler again, because enabled=0. After
 615  * handling the NMI, disable_all will be called, which will not change the
 616  * state either. If PMI hits after disable_all, the PMU is already disabled
 617  * before entering NMI handler. The NMI handler will not change the state
 618  * either.
 619  *
 620  * So either situation is harmless.
 621  */
 622 static void x86_pmu_disable(struct pmu *pmu)
 623 {
 624         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 625
 626         if (!x86_pmu_initialized())
 627                 return;
 628
 629         if (!cpuc->enabled)
 630                 return;
 631
 632         cpuc->n_added = 0;
 633         cpuc->enabled = 0;
 634         barrier();
 635
 636         x86_pmu.disable_all();
 637 }
 638
 639 void x86_pmu_enable_all(int added)
 640 {
 641         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 642         int idx;
 643
 644         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 645                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
 646
 647                 if (!test_bit(idx, cpuc->active_mask))
 648                         continue;
 649
 650                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
 651         }
 652 }
 653
 654 static struct pmu pmu;
 655
 656 static inline int is_x86_event(struct perf_event *event)
 657 {
 658         return event->pmu == &pmu;
 659 }
 660
 661 /*
 662  * Event scheduler state:
 663  *
 664  * Assign events iterating over all events and counters, beginning
 665  * with events with least weights first. Keep the current iterator
 666  * state in struct sched_state.
 667  */
 668 struct sched_state {
 669         int     weight;
 670         int     event;          /* event index */
 671         int     counter;        /* counter index */
 672         int     unassigned;     /* number of events to be assigned left */
 673         int     nr_gp;          /* number of GP counters used */
 674         unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 675 };
 676
 677 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
 678 #define SCHED_STATES_MAX        2
 679
 680 struct perf_sched {
 681         int                     max_weight;
 682         int                     max_events;
 683         int                     max_gp;
 684         int                     saved_states;
 685         struct event_constraint **constraints;
 686         struct sched_state      state;
 687         struct sched_state      saved[SCHED_STATES_MAX];
 688 };
 689
 690 /*
 691  * Initialize interator that runs through all events and counters.
 692  */
 693 static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints,
 694                             int num, int wmin, int wmax, int gpmax)
 695 {
 696         int idx;
 697
 698         memset(sched, 0, sizeof(*sched));
 699         sched->max_events       = num;
 700         sched->max_weight       = wmax;
 701         sched->max_gp           = gpmax;
 702         sched->constraints      = constraints;
 703
 704         for (idx = 0; idx < num; idx++) {
 705                 if (constraints[idx]->weight == wmin)
 706                         break;
 707         }
 708
 709         sched->state.event      = idx;          /* start with min weight */
 710         sched->state.weight     = wmin;
 711         sched->state.unassigned = num;
 712 }
 713
 714 static void perf_sched_save_state(struct perf_sched *sched)
 715 {
 716         if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
 717                 return;
 718
 719         sched->saved[sched->saved_states] = sched->state;
 720         sched->saved_states++;
 721 }
 722
 723 static bool perf_sched_restore_state(struct perf_sched *sched)
 724 {
 725         if (!sched->saved_states)
 726                 return false;
 727
 728         sched->saved_states--;
 729         sched->state = sched->saved[sched->saved_states];
 730
 731         /* continue with next counter: */
 732         clear_bit(sched->state.counter++, sched->state.used);
 733
 734         return true;
 735 }
 736
 737 /*
 738  * Select a counter for the current event to schedule. Return true on
 739  * success.
 740  */
 741 static bool __perf_sched_find_counter(struct perf_sched *sched)
 742 {
 743         struct event_constraint *c;
 744         int idx;
 745
 746         if (!sched->state.unassigned)
 747                 return false;
 748
 749         if (sched->state.event >= sched->max_events)
 750                 return false;
 751
 752         c = sched->constraints[sched->state.event];
 753         /* Prefer fixed purpose counters */
 754         if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
 755                 idx = INTEL_PMC_IDX_FIXED;
 756                 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
 757                         if (!__test_and_set_bit(idx, sched->state.used))
 758                                 goto done;
 759                 }
 760         }
 761
 762         /* Grab the first unused counter starting with idx */
 763         idx = sched->state.counter;
 764         for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
 765                 if (!__test_and_set_bit(idx, sched->state.used)) {
 766                         if (sched->state.nr_gp++ >= sched->max_gp)
 767                                 return false;
 768
 769                         goto done;
 770                 }
 771         }
 772
 773         return false;
 774
 775 done:
 776         sched->state.counter = idx;
 777
 778         if (c->overlap)
 779                 perf_sched_save_state(sched);
 780
 781         return true;
 782 }
 783
 784 static bool perf_sched_find_counter(struct perf_sched *sched)
 785 {
 786         while (!__perf_sched_find_counter(sched)) {
 787                 if (!perf_sched_restore_state(sched))
 788                         return false;
 789         }
 790
 791         return true;
 792 }
 793
 794 /*
 795  * Go through all unassigned events and find the next one to schedule.
 796  * Take events with the least weight first. Return true on success.
 797  */
 798 static bool perf_sched_next_event(struct perf_sched *sched)
 799 {
 800         struct event_constraint *c;
 801
 802         if (!sched->state.unassigned || !--sched->state.unassigned)
 803                 return false;
 804
 805         do {
 806                 /* next event */
 807                 sched->state.event++;
 808                 if (sched->state.event >= sched->max_events) {
 809                         /* next weight */
 810                         sched->state.event = 0;
 811                         sched->state.weight++;
 812                         if (sched->state.weight > sched->max_weight)
 813                                 return false;
 814                 }
 815                 c = sched->constraints[sched->state.event];
 816         } while (c->weight != sched->state.weight);
 817
 818         sched->state.counter = 0;       /* start with first counter */
 819
 820         return true;
 821 }
 822
 823 /*
 824  * Assign a counter for each event.
 825  */
 826 int perf_assign_events(struct event_constraint **constraints, int n,
 827                         int wmin, int wmax, int gpmax, int *assign)
 828 {
 829         struct perf_sched sched;
 830
 831         perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax);
 832
 833         do {
 834                 if (!perf_sched_find_counter(&sched))
 835                         break;  /* failed */
 836                 if (assign)
 837                         assign[sched.state.event] = sched.state.counter;
 838         } while (perf_sched_next_event(&sched));
 839
 840         return sched.state.unassigned;
 841 }
 842 EXPORT_SYMBOL_GPL(perf_assign_events);
 843
 844 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 845 {
 846         struct event_constraint *c;
 847         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 848         struct perf_event *e;
 849         int i, wmin, wmax, unsched = 0;
 850         struct hw_perf_event *hwc;
 851
 852         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 853
 854         if (x86_pmu.start_scheduling)
 855                 x86_pmu.start_scheduling(cpuc);
 856
 857         for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
 858                 cpuc->event_constraint[i] = NULL;
 859                 c = x86_pmu.get_event_constraints(cpuc, i, cpuc->event_list[i]);
 860                 cpuc->event_constraint[i] = c;
 861
 862                 wmin = min(wmin, c->weight);
 863                 wmax = max(wmax, c->weight);
 864         }
 865
 866         /*
 867          * fastpath, try to reuse previous register
 868          */
 869         for (i = 0; i < n; i++) {
 870                 hwc = &cpuc->event_list[i]->hw;
 871                 c = cpuc->event_constraint[i];
 872
 873                 /* never assigned */
 874                 if (hwc->idx == -1)
 875                         break;
 876
 877                 /* constraint still honored */
 878                 if (!test_bit(hwc->idx, c->idxmsk))
 879                         break;
 880
 881                 /* not already used */
 882                 if (test_bit(hwc->idx, used_mask))
 883                         break;
 884
 885                 __set_bit(hwc->idx, used_mask);
 886                 if (assign)
 887                         assign[i] = hwc->idx;
 888         }
 889
 890         /* slow path */
 891         if (i != n) {
 892                 int gpmax = x86_pmu.num_counters;
 893
 894                 /*
 895                  * Do not allow scheduling of more than half the available
 896                  * generic counters.
 897                  *
 898                  * This helps avoid counter starvation of sibling thread by
 899                  * ensuring at most half the counters cannot be in exclusive
 900                  * mode. There is no designated counters for the limits. Any
 901                  * N/2 counters can be used. This helps with events with
 902                  * specific counter constraints.
 903                  */
 904                 if (is_ht_workaround_enabled() && !cpuc->is_fake &&
 905                     READ_ONCE(cpuc->excl_cntrs->exclusive_present))
 906                         gpmax /= 2;
 907
 908                 unsched = perf_assign_events(cpuc->event_constraint, n, wmin,
 909                                              wmax, gpmax, assign);
 910         }
 911
 912         /*
 913          * In case of success (unsched = 0), mark events as committed,
 914          * so we do not put_constraint() in case new events are added
 915          * and fail to be scheduled
 916          *
 917          * We invoke the lower level commit callback to lock the resource
 918          *
 919          * We do not need to do all of this in case we are called to
 920          * validate an event group (assign == NULL)
 921          */
 922         if (!unsched && assign) {
 923                 for (i = 0; i < n; i++) {
 924                         e = cpuc->event_list[i];
 925                         e->hw.flags |= PERF_X86_EVENT_COMMITTED;
 926                         if (x86_pmu.commit_scheduling)
 927                                 x86_pmu.commit_scheduling(cpuc, i, assign[i]);
 928                 }
 929         } else {
 930                 for (i = 0; i < n; i++) {
 931                         e = cpuc->event_list[i];
 932                         /*
 933                          * do not put_constraint() on comitted events,
 934                          * because they are good to go
 935                          */
 936                         if ((e->hw.flags & PERF_X86_EVENT_COMMITTED))
 937                                 continue;
 938
 939                         /*
 940                          * release events that failed scheduling
 941                          */
 942                         if (x86_pmu.put_event_constraints)
 943                                 x86_pmu.put_event_constraints(cpuc, e);
 944                 }
 945         }
 946
 947         if (x86_pmu.stop_scheduling)
 948                 x86_pmu.stop_scheduling(cpuc);
 949
 950         return unsched ? -EINVAL : 0;
 951 }
 952
 953 /*
 954  * dogrp: true if must collect siblings events (group)
 955  * returns total number of events and error code
 956  */
 957 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 958 {
 959         struct perf_event *event;
 960         int n, max_count;
 961
 962         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
 963
 964         /* current number of events already accepted */
 965         n = cpuc->n_events;
 966
 967         if (is_x86_event(leader)) {
 968                 if (n >= max_count)
 969                         return -EINVAL;
 970                 cpuc->event_list[n] = leader;
 971                 n++;
 972         }
 973         if (!dogrp)
 974                 return n;
 975
 976         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 977                 if (!is_x86_event(event) ||
 978                     event->state <= PERF_EVENT_STATE_OFF)
 979                         continue;
 980
 981                 if (n >= max_count)
 982                         return -EINVAL;
 983
 984                 cpuc->event_list[n] = event;
 985                 n++;
 986         }
 987         return n;
 988 }
 989
 990 static inline void x86_assign_hw_event(struct perf_event *event,
 991                                 struct cpu_hw_events *cpuc, int i)
 992 {
 993         struct hw_perf_event *hwc = &event->hw;
 994
 995         hwc->idx = cpuc->assign[i];
 996         hwc->last_cpu = smp_processor_id();
 997         hwc->last_tag = ++cpuc->tags[i];
 998
 999         if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) {
1000                 hwc->config_base = 0;
1001                 hwc->event_base = 0;
1002         } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
1003                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
1004                 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED);
1005                 hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30;
1006         } else {
1007                 hwc->config_base = x86_pmu_config_addr(hwc->idx);
1008                 hwc->event_base  = x86_pmu_event_addr(hwc->idx);
1009                 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
1010         }
1011 }
1012
1013 static inline int match_prev_assignment(struct hw_perf_event *hwc,
1014                                         struct cpu_hw_events *cpuc,
1015                                         int i)
1016 {
1017         return hwc->idx == cpuc->assign[i] &&
1018                 hwc->last_cpu == smp_processor_id() &&
1019                 hwc->last_tag == cpuc->tags[i];
1020 }
1021
1022 static void x86_pmu_start(struct perf_event *event, int flags);
1023
1024 static void x86_pmu_enable(struct pmu *pmu)
1025 {
1026         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1027         struct perf_event *event;
1028         struct hw_perf_event *hwc;
1029         int i, added = cpuc->n_added;
1030
1031         if (!x86_pmu_initialized())
1032                 return;
1033
1034         if (cpuc->enabled)
1035                 return;
1036
1037         if (cpuc->n_added) {
1038                 int n_running = cpuc->n_events - cpuc->n_added;
1039                 /*
1040                  * apply assignment obtained either from
1041                  * hw_perf_group_sched_in() or x86_pmu_enable()
1042                  *
1043                  * step1: save events moving to new counters
1044                  */
1045                 for (i = 0; i < n_running; i++) {
1046                         event = cpuc->event_list[i];
1047                         hwc = &event->hw;
1048
1049                         /*
1050                          * we can avoid reprogramming counter if:
1051                          * - assigned same counter as last time
1052                          * - running on same CPU as last time
1053                          * - no other event has used the counter since
1054                          */
1055                         if (hwc->idx == -1 ||
1056                             match_prev_assignment(hwc, cpuc, i))
1057                                 continue;
1058
1059                         /*
1060                          * Ensure we don't accidentally enable a stopped
1061                          * counter simply because we rescheduled.
1062                          */
1063                         if (hwc->state & PERF_HES_STOPPED)
1064                                 hwc->state |= PERF_HES_ARCH;
1065
1066                         x86_pmu_stop(event, PERF_EF_UPDATE);
1067                 }
1068
1069                 /*
1070                  * step2: reprogram moved events into new counters
1071                  */
1072                 for (i = 0; i < cpuc->n_events; i++) {
1073                         event = cpuc->event_list[i];
1074                         hwc = &event->hw;
1075
1076                         if (!match_prev_assignment(hwc, cpuc, i))
1077                                 x86_assign_hw_event(event, cpuc, i);
1078                         else if (i < n_running)
1079                                 continue;
1080
1081                         if (hwc->state & PERF_HES_ARCH)
1082                                 continue;
1083
1084                         x86_pmu_start(event, PERF_EF_RELOAD);
1085                 }
1086                 cpuc->n_added = 0;
1087                 perf_events_lapic_init();
1088         }
1089
1090         cpuc->enabled = 1;
1091         barrier();
1092
1093         x86_pmu.enable_all(added);
1094 }
1095
1096 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1097
1098 /*
1099  * Set the next IRQ period, based on the hwc->period_left value.
1100  * To be called with the event disabled in hw:
1101  */
1102 int x86_perf_event_set_period(struct perf_event *event)
1103 {
1104         struct hw_perf_event *hwc = &event->hw;
1105         s64 left = local64_read(&hwc->period_left);
1106         s64 period = hwc->sample_period;
1107         int ret = 0, idx = hwc->idx;
1108
1109         if (idx == INTEL_PMC_IDX_FIXED_BTS)
1110                 return 0;
1111
1112         /*
1113          * If we are way outside a reasonable range then just skip forward:
1114          */
1115         if (unlikely(left <= -period)) {
1116                 left = period;
1117                 local64_set(&hwc->period_left, left);
1118                 hwc->last_period = period;
1119                 ret = 1;
1120         }
1121
1122         if (unlikely(left <= 0)) {
1123                 left += period;
1124                 local64_set(&hwc->period_left, left);
1125                 hwc->last_period = period;
1126                 ret = 1;
1127         }
1128         /*
1129          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1130          */
1131         if (unlikely(left < 2))
1132                 left = 2;
1133
1134         if (left > x86_pmu.max_period)
1135                 left = x86_pmu.max_period;
1136
1137         if (x86_pmu.limit_period)
1138                 left = x86_pmu.limit_period(event, left);
1139
1140         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1141
1142         if (!(hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) ||
1143             local64_read(&hwc->prev_count) != (u64)-left) {
1144                 /*
1145                  * The hw event starts counting from this event offset,
1146                  * mark it to be able to extra future deltas:
1147                  */
1148                 local64_set(&hwc->prev_count, (u64)-left);
1149
1150                 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1151         }
1152
1153         /*
1154          * Due to erratum on certan cpu we need
1155          * a second write to be sure the register
1156          * is updated properly
1157          */
1158         if (x86_pmu.perfctr_second_write) {
1159                 wrmsrl(hwc->event_base,
1160                         (u64)(-left) & x86_pmu.cntval_mask);
1161         }
1162
1163         perf_event_update_userpage(event);
1164
1165         return ret;
1166 }
1167
1168 void x86_pmu_enable_event(struct perf_event *event)
1169 {
1170         if (__this_cpu_read(cpu_hw_events.enabled))
1171                 __x86_pmu_enable_event(&event->hw,
1172                                        ARCH_PERFMON_EVENTSEL_ENABLE);
1173 }
1174
1175 /*
1176  * Add a single event to the PMU.
1177  *
1178  * The event is added to the group of enabled events
1179  * but only if it can be scehduled with existing events.
1180  */
1181 static int x86_pmu_add(struct perf_event *event, int flags)
1182 {
1183         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1184         struct hw_perf_event *hwc;
1185         int assign[X86_PMC_IDX_MAX];
1186         int n, n0, ret;
1187
1188         hwc = &event->hw;
1189
1190         n0 = cpuc->n_events;
1191         ret = n = collect_events(cpuc, event, false);
1192         if (ret < 0)
1193                 goto out;
1194
1195         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1196         if (!(flags & PERF_EF_START))
1197                 hwc->state |= PERF_HES_ARCH;
1198
1199         /*
1200          * If group events scheduling transaction was started,
1201          * skip the schedulability test here, it will be performed
1202          * at commit time (->commit_txn) as a whole.
1203          */
1204         if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1205                 goto done_collect;
1206
1207         ret = x86_pmu.schedule_events(cpuc, n, assign);
1208         if (ret)
1209                 goto out;
1210         /*
1211          * copy new assignment, now we know it is possible
1212          * will be used by hw_perf_enable()
1213          */
1214         memcpy(cpuc->assign, assign, n*sizeof(int));
1215
1216 done_collect:
1217         /*
1218          * Commit the collect_events() state. See x86_pmu_del() and
1219          * x86_pmu_*_txn().
1220          */
1221         cpuc->n_events = n;
1222         cpuc->n_added += n - n0;
1223         cpuc->n_txn += n - n0;
1224
1225         ret = 0;
1226 out:
1227         return ret;
1228 }
1229
1230 static void x86_pmu_start(struct perf_event *event, int flags)
1231 {
1232         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1233         int idx = event->hw.idx;
1234
1235         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1236                 return;
1237
1238         if (WARN_ON_ONCE(idx == -1))
1239                 return;
1240
1241         if (flags & PERF_EF_RELOAD) {
1242                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1243                 x86_perf_event_set_period(event);
1244         }
1245
1246         event->hw.state = 0;
1247
1248         cpuc->events[idx] = event;
1249         __set_bit(idx, cpuc->active_mask);
1250         __set_bit(idx, cpuc->running);
1251         x86_pmu.enable(event);
1252         perf_event_update_userpage(event);
1253 }
1254
1255 void perf_event_print_debug(void)
1256 {
1257         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1258         u64 pebs, debugctl;
1259         struct cpu_hw_events *cpuc;
1260         unsigned long flags;
1261         int cpu, idx;
1262
1263         if (!x86_pmu.num_counters)
1264                 return;
1265
1266         local_irq_save(flags);
1267
1268         cpu = smp_processor_id();
1269         cpuc = &per_cpu(cpu_hw_events, cpu);
1270
1271         if (x86_pmu.version >= 2) {
1272                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1273                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1274                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1275                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1276
1277                 pr_info("\n");
1278                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1279                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1280                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1281                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1282                 if (x86_pmu.pebs_constraints) {
1283                         rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1284                         pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1285                 }
1286                 if (x86_pmu.lbr_nr) {
1287                         rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1288                         pr_info("CPU#%d: debugctl:   %016llx\n", cpu, debugctl);
1289                 }
1290         }
1291         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1292
1293         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1294                 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1295                 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1296
1297                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1298
1299                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1300                         cpu, idx, pmc_ctrl);
1301                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1302                         cpu, idx, pmc_count);
1303                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1304                         cpu, idx, prev_left);
1305         }
1306         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1307                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1308
1309                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1310                         cpu, idx, pmc_count);
1311         }
1312         local_irq_restore(flags);
1313 }
1314
1315 void x86_pmu_stop(struct perf_event *event, int flags)
1316 {
1317         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1318         struct hw_perf_event *hwc = &event->hw;
1319
1320         if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1321                 x86_pmu.disable(event);
1322                 cpuc->events[hwc->idx] = NULL;
1323                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1324                 hwc->state |= PERF_HES_STOPPED;
1325         }
1326
1327         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1328                 /*
1329                  * Drain the remaining delta count out of a event
1330                  * that we are disabling:
1331                  */
1332                 x86_perf_event_update(event);
1333                 hwc->state |= PERF_HES_UPTODATE;
1334         }
1335 }
1336
1337 static void x86_pmu_del(struct perf_event *event, int flags)
1338 {
1339         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1340         int i;
1341
1342         /*
1343          * event is descheduled
1344          */
1345         event->hw.flags &= ~PERF_X86_EVENT_COMMITTED;
1346
1347         /*
1348          * If we're called during a txn, we don't need to do anything.
1349          * The events never got scheduled and ->cancel_txn will truncate
1350          * the event_list.
1351          *
1352          * XXX assumes any ->del() called during a TXN will only be on
1353          * an event added during that same TXN.
1354          */
1355         if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1356                 return;
1357
1358         /*
1359          * Not a TXN, therefore cleanup properly.
1360          */
1361         x86_pmu_stop(event, PERF_EF_UPDATE);
1362
1363         for (i = 0; i < cpuc->n_events; i++) {
1364                 if (event == cpuc->event_list[i])
1365                         break;
1366         }
1367
1368         if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
1369                 return;
1370
1371         /* If we have a newly added event; make sure to decrease n_added. */
1372         if (i >= cpuc->n_events - cpuc->n_added)
1373                 --cpuc->n_added;
1374
1375         if (x86_pmu.put_event_constraints)
1376                 x86_pmu.put_event_constraints(cpuc, event);
1377
1378         /* Delete the array entry. */
1379         while (++i < cpuc->n_events) {
1380                 cpuc->event_list[i-1] = cpuc->event_list[i];
1381                 cpuc->event_constraint[i-1] = cpuc->event_constraint[i];
1382         }
1383         --cpuc->n_events;
1384
1385         perf_event_update_userpage(event);
1386 }
1387
1388 int x86_pmu_handle_irq(struct pt_regs *regs)
1389 {
1390         struct perf_sample_data data;
1391         struct cpu_hw_events *cpuc;
1392         struct perf_event *event;
1393         int idx, handled = 0;
1394         u64 val;
1395
1396         cpuc = this_cpu_ptr(&cpu_hw_events);
1397
1398         /*
1399          * Some chipsets need to unmask the LVTPC in a particular spot
1400          * inside the nmi handler.  As a result, the unmasking was pushed
1401          * into all the nmi handlers.
1402          *
1403          * This generic handler doesn't seem to have any issues where the
1404          * unmasking occurs so it was left at the top.
1405          */
1406         apic_write(APIC_LVTPC, APIC_DM_NMI);
1407
1408         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1409                 if (!test_bit(idx, cpuc->active_mask)) {
1410                         /*
1411                          * Though we deactivated the counter some cpus
1412                          * might still deliver spurious interrupts still
1413                          * in flight. Catch them:
1414                          */
1415                         if (__test_and_clear_bit(idx, cpuc->running))
1416                                 handled++;
1417                         continue;
1418                 }
1419
1420                 event = cpuc->events[idx];
1421
1422                 val = x86_perf_event_update(event);
1423                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1424                         continue;
1425
1426                 /*
1427                  * event overflow
1428                  */
1429                 handled++;
1430                 perf_sample_data_init(&data, 0, event->hw.last_period);
1431
1432                 if (!x86_perf_event_set_period(event))
1433                         continue;
1434
1435                 if (perf_event_overflow(event, &data, regs))
1436                         x86_pmu_stop(event, 0);
1437         }
1438
1439         if (handled)
1440                 inc_irq_stat(apic_perf_irqs);
1441
1442         return handled;
1443 }
1444
1445 void perf_events_lapic_init(void)
1446 {
1447         if (!x86_pmu.apic || !x86_pmu_initialized())
1448                 return;
1449
1450         /*
1451          * Always use NMI for PMU
1452          */
1453         apic_write(APIC_LVTPC, APIC_DM_NMI);
1454 }
1455
1456 static int
1457 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1458 {
1459         u64 start_clock;
1460         u64 finish_clock;
1461         int ret;
1462
1463         /*
1464          * All PMUs/events that share this PMI handler should make sure to
1465          * increment active_events for their events.
1466          */
1467         if (!atomic_read(&active_events))
1468                 return NMI_DONE;
1469
1470         start_clock = sched_clock();
1471         ret = x86_pmu.handle_irq(regs);
1472         finish_clock = sched_clock();
1473
1474         perf_sample_event_took(finish_clock - start_clock);
1475
1476         return ret;
1477 }
1478 NOKPROBE_SYMBOL(perf_event_nmi_handler);
1479
1480 struct event_constraint emptyconstraint;
1481 struct event_constraint unconstrained;
1482
1483 static int x86_pmu_prepare_cpu(unsigned int cpu)
1484 {
1485         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1486         int i;
1487
1488         for (i = 0 ; i < X86_PERF_KFREE_MAX; i++)
1489                 cpuc->kfree_on_online[i] = NULL;
1490         if (x86_pmu.cpu_prepare)
1491                 return x86_pmu.cpu_prepare(cpu);
1492         return 0;
1493 }
1494
1495 static int x86_pmu_dead_cpu(unsigned int cpu)
1496 {
1497         if (x86_pmu.cpu_dead)
1498                 x86_pmu.cpu_dead(cpu);
1499         return 0;
1500 }
1501
1502 static int x86_pmu_online_cpu(unsigned int cpu)
1503 {
1504         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1505         int i;
1506
1507         for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) {
1508                 kfree(cpuc->kfree_on_online[i]);
1509                 cpuc->kfree_on_online[i] = NULL;
1510         }
1511         return 0;
1512 }
1513
1514 static int x86_pmu_starting_cpu(unsigned int cpu)
1515 {
1516         if (x86_pmu.cpu_starting)
1517                 x86_pmu.cpu_starting(cpu);
1518         return 0;
1519 }
1520
1521 static int x86_pmu_dying_cpu(unsigned int cpu)
1522 {
1523         if (x86_pmu.cpu_dying)
1524                 x86_pmu.cpu_dying(cpu);
1525         return 0;
1526 }
1527
1528 static void __init pmu_check_apic(void)
1529 {
1530         if (boot_cpu_has(X86_FEATURE_APIC))
1531                 return;
1532
1533         x86_pmu.apic = 0;
1534         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1535         pr_info("no hardware sampling interrupt available.\n");
1536
1537         /*
1538          * If we have a PMU initialized but no APIC
1539          * interrupts, we cannot sample hardware
1540          * events (user-space has to fall back and
1541          * sample via a hrtimer based software event):
1542          */
1543         pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1544
1545 }
1546
1547 static struct attribute_group x86_pmu_format_group = {
1548         .name = "format",
1549         .attrs = NULL,
1550 };
1551
1552 /*
1553  * Remove all undefined events (x86_pmu.event_map(id) == 0)
1554  * out of events_attr attributes.
1555  */
1556 static void __init filter_events(struct attribute **attrs)
1557 {
1558         struct device_attribute *d;
1559         struct perf_pmu_events_attr *pmu_attr;
1560         int offset = 0;
1561         int i, j;
1562
1563         for (i = 0; attrs[i]; i++) {
1564                 d = (struct device_attribute *)attrs[i];
1565                 pmu_attr = container_of(d, struct perf_pmu_events_attr, attr);
1566                 /* str trumps id */
1567                 if (pmu_attr->event_str)
1568                         continue;
1569                 if (x86_pmu.event_map(i + offset))
1570                         continue;
1571
1572                 for (j = i; attrs[j]; j++)
1573                         attrs[j] = attrs[j + 1];
1574
1575                 /* Check the shifted attr. */
1576                 i--;
1577
1578                 /*
1579                  * event_map() is index based, the attrs array is organized
1580                  * by increasing event index. If we shift the events, then
1581                  * we need to compensate for the event_map(), otherwise
1582                  * we are looking up the wrong event in the map
1583                  */
1584                 offset++;
1585         }
1586 }
1587
1588 /* Merge two pointer arrays */
1589 __init struct attribute **merge_attr(struct attribute **a, struct attribute **b)
1590 {
1591         struct attribute **new;
1592         int j, i;
1593
1594         for (j = 0; a[j]; j++)
1595                 ;
1596         for (i = 0; b[i]; i++)
1597                 j++;
1598         j++;
1599
1600         new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL);
1601         if (!new)
1602                 return NULL;
1603
1604         j = 0;
1605         for (i = 0; a[i]; i++)
1606                 new[j++] = a[i];
1607         for (i = 0; b[i]; i++)
1608                 new[j++] = b[i];
1609         new[j] = NULL;
1610
1611         return new;
1612 }
1613
1614 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, char *page)
1615 {
1616         struct perf_pmu_events_attr *pmu_attr = \
1617                 container_of(attr, struct perf_pmu_events_attr, attr);
1618         u64 config = x86_pmu.event_map(pmu_attr->id);
1619
1620         /* string trumps id */
1621         if (pmu_attr->event_str)
1622                 return sprintf(page, "%s", pmu_attr->event_str);
1623
1624         return x86_pmu.events_sysfs_show(page, config);
1625 }
1626 EXPORT_SYMBOL_GPL(events_sysfs_show);
1627
1628 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr,
1629                           char *page)
1630 {
1631         struct perf_pmu_events_ht_attr *pmu_attr =
1632                 container_of(attr, struct perf_pmu_events_ht_attr, attr);
1633
1634         /*
1635          * Report conditional events depending on Hyper-Threading.
1636          *
1637          * This is overly conservative as usually the HT special
1638          * handling is not needed if the other CPU thread is idle.
1639          *
1640          * Note this does not (and cannot) handle the case when thread
1641          * siblings are invisible, for example with virtualization
1642          * if they are owned by some other guest.  The user tool
1643          * has to re-read when a thread sibling gets onlined later.
1644          */
1645         return sprintf(page, "%s",
1646                         topology_max_smt_threads() > 1 ?
1647                         pmu_attr->event_str_ht :
1648                         pmu_attr->event_str_noht);
1649 }
1650
1651 EVENT_ATTR(cpu-cycles,                  CPU_CYCLES              );
1652 EVENT_ATTR(instructions,                INSTRUCTIONS            );
1653 EVENT_ATTR(cache-references,            CACHE_REFERENCES        );
1654 EVENT_ATTR(cache-misses,                CACHE_MISSES            );
1655 EVENT_ATTR(branch-instructions,         BRANCH_INSTRUCTIONS     );
1656 EVENT_ATTR(branch-misses,               BRANCH_MISSES           );
1657 EVENT_ATTR(bus-cycles,                  BUS_CYCLES              );
1658 EVENT_ATTR(stalled-cycles-frontend,     STALLED_CYCLES_FRONTEND );
1659 EVENT_ATTR(stalled-cycles-backend,      STALLED_CYCLES_BACKEND  );
1660 EVENT_ATTR(ref-cycles,                  REF_CPU_CYCLES          );
1661
1662 static struct attribute *empty_attrs;
1663
1664 static struct attribute *events_attr[] = {
1665         EVENT_PTR(CPU_CYCLES),
1666         EVENT_PTR(INSTRUCTIONS),
1667         EVENT_PTR(CACHE_REFERENCES),
1668         EVENT_PTR(CACHE_MISSES),
1669         EVENT_PTR(BRANCH_INSTRUCTIONS),
1670         EVENT_PTR(BRANCH_MISSES),
1671         EVENT_PTR(BUS_CYCLES),
1672         EVENT_PTR(STALLED_CYCLES_FRONTEND),
1673         EVENT_PTR(STALLED_CYCLES_BACKEND),
1674         EVENT_PTR(REF_CPU_CYCLES),
1675         NULL,
1676 };
1677
1678 static struct attribute_group x86_pmu_events_group = {
1679         .name = "events",
1680         .attrs = events_attr,
1681 };
1682
1683 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1684 {
1685         u64 umask  = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1686         u64 cmask  = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1687         bool edge  = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1688         bool pc    = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1689         bool any   = (config & ARCH_PERFMON_EVENTSEL_ANY);
1690         bool inv   = (config & ARCH_PERFMON_EVENTSEL_INV);
1691         ssize_t ret;
1692
1693         /*
1694         * We have whole page size to spend and just little data
1695         * to write, so we can safely use sprintf.
1696         */
1697         ret = sprintf(page, "event=0x%02llx", event);
1698
1699         if (umask)
1700                 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1701
1702         if (edge)
1703                 ret += sprintf(page + ret, ",edge");
1704
1705         if (pc)
1706                 ret += sprintf(page + ret, ",pc");
1707
1708         if (any)
1709                 ret += sprintf(page + ret, ",any");
1710
1711         if (inv)
1712                 ret += sprintf(page + ret, ",inv");
1713
1714         if (cmask)
1715                 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
1716
1717         ret += sprintf(page + ret, "\n");
1718
1719         return ret;
1720 }
1721
1722 static int __init init_hw_perf_events(void)
1723 {
1724         struct x86_pmu_quirk *quirk;
1725         int err;
1726
1727         pr_info("Performance Events: ");
1728
1729         switch (boot_cpu_data.x86_vendor) {
1730         case X86_VENDOR_INTEL:
1731                 err = intel_pmu_init();
1732                 break;
1733         case X86_VENDOR_AMD:
1734                 err = amd_pmu_init();
1735                 break;
1736         default:
1737                 err = -ENOTSUPP;
1738         }
1739         if (err != 0) {
1740                 pr_cont("no PMU driver, software events only.\n");
1741                 return 0;
1742         }
1743
1744         pmu_check_apic();
1745
1746         /* sanity check that the hardware exists or is emulated */
1747         if (!check_hw_exists())
1748                 return 0;
1749
1750         pr_cont("%s PMU driver.\n", x86_pmu.name);
1751
1752         x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
1753
1754         for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
1755                 quirk->func();
1756
1757         if (!x86_pmu.intel_ctrl)
1758                 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1759
1760         perf_events_lapic_init();
1761         register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1762
1763         unconstrained = (struct event_constraint)
1764                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1765                                    0, x86_pmu.num_counters, 0, 0);
1766
1767         x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1768
1769         if (x86_pmu.event_attrs)
1770                 x86_pmu_events_group.attrs = x86_pmu.event_attrs;
1771
1772         if (!x86_pmu.events_sysfs_show)
1773                 x86_pmu_events_group.attrs = &empty_attrs;
1774         else
1775                 filter_events(x86_pmu_events_group.attrs);
1776
1777         if (x86_pmu.cpu_events) {
1778                 struct attribute **tmp;
1779
1780                 tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events);
1781                 if (!WARN_ON(!tmp))
1782                         x86_pmu_events_group.attrs = tmp;
1783         }
1784
1785         pr_info("... version:                %d\n",     x86_pmu.version);
1786         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1787         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1788         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1789         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1790         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1791         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1792
1793         /*
1794          * Install callbacks. Core will call them for each online
1795          * cpu.
1796          */
1797         err = cpuhp_setup_state(CPUHP_PERF_X86_PREPARE, "PERF_X86_PREPARE",
1798                                 x86_pmu_prepare_cpu, x86_pmu_dead_cpu);
1799         if (err)
1800                 return err;
1801
1802         err = cpuhp_setup_state(CPUHP_AP_PERF_X86_STARTING,
1803                                 "AP_PERF_X86_STARTING", x86_pmu_starting_cpu,
1804                                 x86_pmu_dying_cpu);
1805         if (err)
1806                 goto out;
1807
1808         err = cpuhp_setup_state(CPUHP_AP_PERF_X86_ONLINE, "AP_PERF_X86_ONLINE",
1809                                 x86_pmu_online_cpu, NULL);
1810         if (err)
1811                 goto out1;
1812
1813         err = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1814         if (err)
1815                 goto out2;
1816
1817         return 0;
1818
1819 out2:
1820         cpuhp_remove_state(CPUHP_AP_PERF_X86_ONLINE);
1821 out1:
1822         cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING);
1823 out:
1824         cpuhp_remove_state(CPUHP_PERF_X86_PREPARE);
1825         return err;
1826 }
1827 early_initcall(init_hw_perf_events);
1828
1829 static inline void x86_pmu_read(struct perf_event *event)
1830 {
1831         x86_perf_event_update(event);
1832 }
1833
1834 /*
1835  * Start group events scheduling transaction
1836  * Set the flag to make pmu::enable() not perform the
1837  * schedulability test, it will be performed at commit time
1838  *
1839  * We only support PERF_PMU_TXN_ADD transactions. Save the
1840  * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
1841  * transactions.
1842  */
1843 static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
1844 {
1845         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1846
1847         WARN_ON_ONCE(cpuc->txn_flags);          /* txn already in flight */
1848
1849         cpuc->txn_flags = txn_flags;
1850         if (txn_flags & ~PERF_PMU_TXN_ADD)
1851                 return;
1852
1853         perf_pmu_disable(pmu);
1854         __this_cpu_write(cpu_hw_events.n_txn, 0);
1855 }
1856
1857 /*
1858  * Stop group events scheduling transaction
1859  * Clear the flag and pmu::enable() will perform the
1860  * schedulability test.
1861  */
1862 static void x86_pmu_cancel_txn(struct pmu *pmu)
1863 {
1864         unsigned int txn_flags;
1865         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1866
1867         WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
1868
1869         txn_flags = cpuc->txn_flags;
1870         cpuc->txn_flags = 0;
1871         if (txn_flags & ~PERF_PMU_TXN_ADD)
1872                 return;
1873
1874         /*
1875          * Truncate collected array by the number of events added in this
1876          * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1877          */
1878         __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1879         __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1880         perf_pmu_enable(pmu);
1881 }
1882
1883 /*
1884  * Commit group events scheduling transaction
1885  * Perform the group schedulability test as a whole
1886  * Return 0 if success
1887  *
1888  * Does not cancel the transaction on failure; expects the caller to do this.
1889  */
1890 static int x86_pmu_commit_txn(struct pmu *pmu)
1891 {
1892         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1893         int assign[X86_PMC_IDX_MAX];
1894         int n, ret;
1895
1896         WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
1897
1898         if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) {
1899                 cpuc->txn_flags = 0;
1900                 return 0;
1901         }
1902
1903         n = cpuc->n_events;
1904
1905         if (!x86_pmu_initialized())
1906                 return -EAGAIN;
1907
1908         ret = x86_pmu.schedule_events(cpuc, n, assign);
1909         if (ret)
1910                 return ret;
1911
1912         /*
1913          * copy new assignment, now we know it is possible
1914          * will be used by hw_perf_enable()
1915          */
1916         memcpy(cpuc->assign, assign, n*sizeof(int));
1917
1918         cpuc->txn_flags = 0;
1919         perf_pmu_enable(pmu);
1920         return 0;
1921 }
1922 /*
1923  * a fake_cpuc is used to validate event groups. Due to
1924  * the extra reg logic, we need to also allocate a fake
1925  * per_core and per_cpu structure. Otherwise, group events
1926  * using extra reg may conflict without the kernel being
1927  * able to catch this when the last event gets added to
1928  * the group.
1929  */
1930 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
1931 {
1932         kfree(cpuc->shared_regs);
1933         kfree(cpuc);
1934 }
1935
1936 static struct cpu_hw_events *allocate_fake_cpuc(void)
1937 {
1938         struct cpu_hw_events *cpuc;
1939         int cpu = raw_smp_processor_id();
1940
1941         cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
1942         if (!cpuc)
1943                 return ERR_PTR(-ENOMEM);
1944
1945         /* only needed, if we have extra_regs */
1946         if (x86_pmu.extra_regs) {
1947                 cpuc->shared_regs = allocate_shared_regs(cpu);
1948                 if (!cpuc->shared_regs)
1949                         goto error;
1950         }
1951         cpuc->is_fake = 1;
1952         return cpuc;
1953 error:
1954         free_fake_cpuc(cpuc);
1955         return ERR_PTR(-ENOMEM);
1956 }
1957
1958 /*
1959  * validate that we can schedule this event
1960  */
1961 static int validate_event(struct perf_event *event)
1962 {
1963         struct cpu_hw_events *fake_cpuc;
1964         struct event_constraint *c;
1965         int ret = 0;
1966
1967         fake_cpuc = allocate_fake_cpuc();
1968         if (IS_ERR(fake_cpuc))
1969                 return PTR_ERR(fake_cpuc);
1970
1971         c = x86_pmu.get_event_constraints(fake_cpuc, -1, event);
1972
1973         if (!c || !c->weight)
1974                 ret = -EINVAL;
1975
1976         if (x86_pmu.put_event_constraints)
1977                 x86_pmu.put_event_constraints(fake_cpuc, event);
1978
1979         free_fake_cpuc(fake_cpuc);
1980
1981         return ret;
1982 }
1983
1984 /*
1985  * validate a single event group
1986  *
1987  * validation include:
1988  *      - check events are compatible which each other
1989  *      - events do not compete for the same counter
1990  *      - number of events <= number of counters
1991  *
1992  * validation ensures the group can be loaded onto the
1993  * PMU if it was the only group available.
1994  */
1995 static int validate_group(struct perf_event *event)
1996 {
1997         struct perf_event *leader = event->group_leader;
1998         struct cpu_hw_events *fake_cpuc;
1999         int ret = -EINVAL, n;
2000
2001         fake_cpuc = allocate_fake_cpuc();
2002         if (IS_ERR(fake_cpuc))
2003                 return PTR_ERR(fake_cpuc);
2004         /*
2005          * the event is not yet connected with its
2006          * siblings therefore we must first collect
2007          * existing siblings, then add the new event
2008          * before we can simulate the scheduling
2009          */
2010         n = collect_events(fake_cpuc, leader, true);
2011         if (n < 0)
2012                 goto out;
2013
2014         fake_cpuc->n_events = n;
2015         n = collect_events(fake_cpuc, event, false);
2016         if (n < 0)
2017                 goto out;
2018
2019         fake_cpuc->n_events = n;
2020
2021         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
2022
2023 out:
2024         free_fake_cpuc(fake_cpuc);
2025         return ret;
2026 }
2027
2028 static int x86_pmu_event_init(struct perf_event *event)
2029 {
2030         struct pmu *tmp;
2031         int err;
2032
2033         switch (event->attr.type) {
2034         case PERF_TYPE_RAW:
2035         case PERF_TYPE_HARDWARE:
2036         case PERF_TYPE_HW_CACHE:
2037                 break;
2038
2039         default:
2040                 return -ENOENT;
2041         }
2042
2043         err = __x86_pmu_event_init(event);
2044         if (!err) {
2045                 /*
2046                  * we temporarily connect event to its pmu
2047                  * such that validate_group() can classify
2048                  * it as an x86 event using is_x86_event()
2049                  */
2050                 tmp = event->pmu;
2051                 event->pmu = &pmu;
2052
2053                 if (event->group_leader != event)
2054                         err = validate_group(event);
2055                 else
2056                         err = validate_event(event);
2057
2058                 event->pmu = tmp;
2059         }
2060         if (err) {
2061                 if (event->destroy)
2062                         event->destroy(event);
2063         }
2064
2065         if (ACCESS_ONCE(x86_pmu.attr_rdpmc))
2066                 event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED;
2067
2068         return err;
2069 }
2070
2071 static void refresh_pce(void *ignored)
2072 {
2073         if (current->mm)
2074                 load_mm_cr4(current->mm);
2075 }
2076
2077 static void x86_pmu_event_mapped(struct perf_event *event)
2078 {
2079         if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2080                 return;
2081
2082         if (atomic_inc_return(&current->mm->context.perf_rdpmc_allowed) == 1)
2083                 on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1);
2084 }
2085
2086 static void x86_pmu_event_unmapped(struct perf_event *event)
2087 {
2088         if (!current->mm)
2089                 return;
2090
2091         if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2092                 return;
2093
2094         if (atomic_dec_and_test(&current->mm->context.perf_rdpmc_allowed))
2095                 on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1);
2096 }
2097
2098 static int x86_pmu_event_idx(struct perf_event *event)
2099 {
2100         int idx = event->hw.idx;
2101
2102         if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2103                 return 0;
2104
2105         if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) {
2106                 idx -= INTEL_PMC_IDX_FIXED;
2107                 idx |= 1 << 30;
2108         }
2109
2110         return idx + 1;
2111 }
2112
2113 static ssize_t get_attr_rdpmc(struct device *cdev,
2114                               struct device_attribute *attr,
2115                               char *buf)
2116 {
2117         return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
2118 }
2119
2120 static ssize_t set_attr_rdpmc(struct device *cdev,
2121                               struct device_attribute *attr,
2122                               const char *buf, size_t count)
2123 {
2124         unsigned long val;
2125         ssize_t ret;
2126
2127         ret = kstrtoul(buf, 0, &val);
2128         if (ret)
2129                 return ret;
2130
2131         if (val > 2)
2132                 return -EINVAL;
2133
2134         if (x86_pmu.attr_rdpmc_broken)
2135                 return -ENOTSUPP;
2136
2137         if ((val == 2) != (x86_pmu.attr_rdpmc == 2)) {
2138                 /*
2139                  * Changing into or out of always available, aka
2140                  * perf-event-bypassing mode.  This path is extremely slow,
2141                  * but only root can trigger it, so it's okay.
2142                  */
2143                 if (val == 2)
2144                         static_key_slow_inc(&rdpmc_always_available);
2145                 else
2146                         static_key_slow_dec(&rdpmc_always_available);
2147                 on_each_cpu(refresh_pce, NULL, 1);
2148         }
2149
2150         x86_pmu.attr_rdpmc = val;
2151
2152         return count;
2153 }
2154
2155 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
2156
2157 static struct attribute *x86_pmu_attrs[] = {
2158         &dev_attr_rdpmc.attr,
2159         NULL,
2160 };
2161
2162 static struct attribute_group x86_pmu_attr_group = {
2163         .attrs = x86_pmu_attrs,
2164 };
2165
2166 static const struct attribute_group *x86_pmu_attr_groups[] = {
2167         &x86_pmu_attr_group,
2168         &x86_pmu_format_group,
2169         &x86_pmu_events_group,
2170         NULL,
2171 };
2172
2173 static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
2174 {
2175         if (x86_pmu.sched_task)
2176                 x86_pmu.sched_task(ctx, sched_in);
2177 }
2178
2179 void perf_check_microcode(void)
2180 {
2181         if (x86_pmu.check_microcode)
2182                 x86_pmu.check_microcode();
2183 }
2184 EXPORT_SYMBOL_GPL(perf_check_microcode);
2185
2186 static struct pmu pmu = {
2187         .pmu_enable             = x86_pmu_enable,
2188         .pmu_disable            = x86_pmu_disable,
2189
2190         .attr_groups            = x86_pmu_attr_groups,
2191
2192         .event_init             = x86_pmu_event_init,
2193
2194         .event_mapped           = x86_pmu_event_mapped,
2195         .event_unmapped         = x86_pmu_event_unmapped,
2196
2197         .add                    = x86_pmu_add,
2198         .del                    = x86_pmu_del,
2199         .start                  = x86_pmu_start,
2200         .stop                   = x86_pmu_stop,
2201         .read                   = x86_pmu_read,
2202
2203         .start_txn              = x86_pmu_start_txn,
2204         .cancel_txn             = x86_pmu_cancel_txn,
2205         .commit_txn             = x86_pmu_commit_txn,
2206
2207         .event_idx              = x86_pmu_event_idx,
2208         .sched_task             = x86_pmu_sched_task,
2209         .task_ctx_size          = sizeof(struct x86_perf_task_context),
2210 };
2211
2212 void arch_perf_update_userpage(struct perf_event *event,
2213                                struct perf_event_mmap_page *userpg, u64 now)
2214 {
2215         struct cyc2ns_data *data;
2216
2217         userpg->cap_user_time = 0;
2218         userpg->cap_user_time_zero = 0;
2219         userpg->cap_user_rdpmc =
2220                 !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED);
2221         userpg->pmc_width = x86_pmu.cntval_bits;
2222
2223         if (!sched_clock_stable())
2224                 return;
2225
2226         data = cyc2ns_read_begin();
2227
2228         /*
2229          * Internal timekeeping for enabled/running/stopped times
2230          * is always in the local_clock domain.
2231          */
2232         userpg->cap_user_time = 1;
2233         userpg->time_mult = data->cyc2ns_mul;
2234         userpg->time_shift = data->cyc2ns_shift;
2235         userpg->time_offset = data->cyc2ns_offset - now;
2236
2237         /*
2238          * cap_user_time_zero doesn't make sense when we're using a different
2239          * time base for the records.
2240          */
2241         if (!event->attr.use_clockid) {
2242                 userpg->cap_user_time_zero = 1;
2243                 userpg->time_zero = data->cyc2ns_offset;
2244         }
2245
2246         cyc2ns_read_end(data);
2247 }
2248
2249 /*
2250  * callchain support
2251  */
2252
2253 static int backtrace_stack(void *data, char *name)
2254 {
2255         return 0;
2256 }
2257
2258 static int backtrace_address(void *data, unsigned long addr, int reliable)
2259 {
2260         struct perf_callchain_entry_ctx *entry = data;
2261
2262         return perf_callchain_store(entry, addr);
2263 }
2264
2265 static const struct stacktrace_ops backtrace_ops = {
2266         .stack                  = backtrace_stack,
2267         .address                = backtrace_address,
2268         .walk_stack             = print_context_stack_bp,
2269 };
2270
2271 void
2272 perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2273 {
2274         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2275                 /* TODO: We don't support guest os callchain now */
2276                 return;
2277         }
2278
2279         perf_callchain_store(entry, regs->ip);
2280
2281         dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
2282 }
2283
2284 static inline int
2285 valid_user_frame(const void __user *fp, unsigned long size)
2286 {
2287         return (__range_not_ok(fp, size, TASK_SIZE) == 0);
2288 }
2289
2290 static unsigned long get_segment_base(unsigned int segment)
2291 {
2292         struct desc_struct *desc;
2293         int idx = segment >> 3;
2294
2295         if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2296 #ifdef CONFIG_MODIFY_LDT_SYSCALL
2297                 struct ldt_struct *ldt;
2298
2299                 if (idx > LDT_ENTRIES)
2300                         return 0;
2301
2302                 /* IRQs are off, so this synchronizes with smp_store_release */
2303                 ldt = lockless_dereference(current->active_mm->context.ldt);
2304                 if (!ldt || idx > ldt->size)
2305                         return 0;
2306
2307                 desc = &ldt->entries[idx];
2308 #else
2309                 return 0;
2310 #endif
2311         } else {
2312                 if (idx > GDT_ENTRIES)
2313                         return 0;
2314
2315                 desc = raw_cpu_ptr(gdt_page.gdt) + idx;
2316         }
2317
2318         return get_desc_base(desc);
2319 }
2320
2321 #ifdef CONFIG_IA32_EMULATION
2322
2323 #include <asm/compat.h>
2324
2325 static inline int
2326 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2327 {
2328         /* 32-bit process in 64-bit kernel. */
2329         unsigned long ss_base, cs_base;
2330         struct stack_frame_ia32 frame;
2331         const void __user *fp;
2332
2333         if (!test_thread_flag(TIF_IA32))
2334                 return 0;
2335
2336         cs_base = get_segment_base(regs->cs);
2337         ss_base = get_segment_base(regs->ss);
2338
2339         fp = compat_ptr(ss_base + regs->bp);
2340         pagefault_disable();
2341         while (entry->nr < entry->max_stack) {
2342                 unsigned long bytes;
2343                 frame.next_frame     = 0;
2344                 frame.return_address = 0;
2345
2346                 if (!access_ok(VERIFY_READ, fp, 8))
2347                         break;
2348
2349                 bytes = __copy_from_user_nmi(&frame.next_frame, fp, 4);
2350                 if (bytes != 0)
2351                         break;
2352                 bytes = __copy_from_user_nmi(&frame.return_address, fp+4, 4);
2353                 if (bytes != 0)
2354                         break;
2355
2356                 if (!valid_user_frame(fp, sizeof(frame)))
2357                         break;
2358
2359                 perf_callchain_store(entry, cs_base + frame.return_address);
2360                 fp = compat_ptr(ss_base + frame.next_frame);
2361         }
2362         pagefault_enable();
2363         return 1;
2364 }
2365 #else
2366 static inline int
2367 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2368 {
2369     return 0;
2370 }
2371 #endif
2372
2373 void
2374 perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2375 {
2376         struct stack_frame frame;
2377         const unsigned long __user *fp;
2378
2379         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2380                 /* TODO: We don't support guest os callchain now */
2381                 return;
2382         }
2383
2384         /*
2385          * We don't know what to do with VM86 stacks.. ignore them for now.
2386          */
2387         if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2388                 return;
2389
2390         fp = (unsigned long __user *)regs->bp;
2391
2392         perf_callchain_store(entry, regs->ip);
2393
2394         if (!current->mm)
2395                 return;
2396
2397         if (perf_callchain_user32(regs, entry))
2398                 return;
2399
2400         pagefault_disable();
2401         while (entry->nr < entry->max_stack) {
2402                 unsigned long bytes;
2403
2404                 frame.next_frame             = NULL;
2405                 frame.return_address = 0;
2406
2407                 if (!access_ok(VERIFY_READ, fp, sizeof(*fp) * 2))
2408                         break;
2409
2410                 bytes = __copy_from_user_nmi(&frame.next_frame, fp, sizeof(*fp));
2411                 if (bytes != 0)
2412                         break;
2413                 bytes = __copy_from_user_nmi(&frame.return_address, fp + 1, sizeof(*fp));
2414                 if (bytes != 0)
2415                         break;
2416
2417                 if (!valid_user_frame(fp, sizeof(frame)))
2418                         break;
2419
2420                 perf_callchain_store(entry, frame.return_address);
2421                 fp = (void __user *)frame.next_frame;
2422         }
2423         pagefault_enable();
2424 }
2425
2426 /*
2427  * Deal with code segment offsets for the various execution modes:
2428  *
2429  *   VM86 - the good olde 16 bit days, where the linear address is
2430  *          20 bits and we use regs->ip + 0x10 * regs->cs.
2431  *
2432  *   IA32 - Where we need to look at GDT/LDT segment descriptor tables
2433  *          to figure out what the 32bit base address is.
2434  *
2435  *    X32 - has TIF_X32 set, but is running in x86_64
2436  *
2437  * X86_64 - CS,DS,SS,ES are all zero based.
2438  */
2439 static unsigned long code_segment_base(struct pt_regs *regs)
2440 {
2441         /*
2442          * For IA32 we look at the GDT/LDT segment base to convert the
2443          * effective IP to a linear address.
2444          */
2445
2446 #ifdef CONFIG_X86_32
2447         /*
2448          * If we are in VM86 mode, add the segment offset to convert to a
2449          * linear address.
2450          */
2451         if (regs->flags & X86_VM_MASK)
2452                 return 0x10 * regs->cs;
2453
2454         if (user_mode(regs) && regs->cs != __USER_CS)
2455                 return get_segment_base(regs->cs);
2456 #else
2457         if (user_mode(regs) && !user_64bit_mode(regs) &&
2458             regs->cs != __USER32_CS)
2459                 return get_segment_base(regs->cs);
2460 #endif
2461         return 0;
2462 }
2463
2464 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2465 {
2466         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
2467                 return perf_guest_cbs->get_guest_ip();
2468
2469         return regs->ip + code_segment_base(regs);
2470 }
2471
2472 unsigned long perf_misc_flags(struct pt_regs *regs)
2473 {
2474         int misc = 0;
2475
2476         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2477                 if (perf_guest_cbs->is_user_mode())
2478                         misc |= PERF_RECORD_MISC_GUEST_USER;
2479                 else
2480                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2481         } else {
2482                 if (user_mode(regs))
2483                         misc |= PERF_RECORD_MISC_USER;
2484                 else
2485                         misc |= PERF_RECORD_MISC_KERNEL;
2486         }
2487
2488         if (regs->flags & PERF_EFLAGS_EXACT)
2489                 misc |= PERF_RECORD_MISC_EXACT_IP;
2490
2491         return misc;
2492 }
2493
2494 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2495 {
2496         cap->version            = x86_pmu.version;
2497         cap->num_counters_gp    = x86_pmu.num_counters;
2498         cap->num_counters_fixed = x86_pmu.num_counters_fixed;
2499         cap->bit_width_gp       = x86_pmu.cntval_bits;
2500         cap->bit_width_fixed    = x86_pmu.cntval_bits;
2501         cap->events_mask        = (unsigned int)x86_pmu.events_maskl;
2502         cap->events_mask_len    = x86_pmu.events_mask_len;
2503 }
2504 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);