2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
15 #ifndef _ASM_TILE_CACHE_H
16 #define _ASM_TILE_CACHE_H
18 #include <arch/chip.h>
20 /* bytes per L1 data cache line */
21 #define L1_CACHE_SHIFT CHIP_L1D_LOG_LINE_SIZE()
22 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
23 #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1)) & -L1_CACHE_BYTES)
25 /* bytes per L1 instruction cache line */
26 #define L1I_CACHE_SHIFT CHIP_L1I_LOG_LINE_SIZE()
27 #define L1I_CACHE_BYTES (1 << L1I_CACHE_SHIFT)
28 #define L1I_CACHE_ALIGN(x) (((x)+(L1I_CACHE_BYTES-1)) & -L1I_CACHE_BYTES)
30 /* bytes per L2 cache line */
31 #define L2_CACHE_SHIFT CHIP_L2_LOG_LINE_SIZE()
32 #define L2_CACHE_BYTES (1 << L2_CACHE_SHIFT)
33 #define L2_CACHE_ALIGN(x) (((x)+(L2_CACHE_BYTES-1)) & -L2_CACHE_BYTES)
35 /* use the cache line size for the L2, which is where it counts */
36 #define SMP_CACHE_BYTES_SHIFT L2_CACHE_SHIFT
37 #define SMP_CACHE_BYTES L2_CACHE_BYTES
38 #define INTERNODE_CACHE_SHIFT L2_CACHE_SHIFT
39 #define INTERNODE_CACHE_BYTES L2_CACHE_BYTES
41 /* Group together read-mostly things to avoid cache false sharing */
42 #define __read_mostly __attribute__((__section__(".data.read_mostly")))
45 * Attribute for data that is kept read/write coherent until the end of
46 * initialization, then bumped to read/only incoherent for performance.
48 #define __write_once __attribute__((__section__(".w1data")))
50 #endif /* _ASM_TILE_CACHE_H */