1 // SPDX-License-Identifier: GPL-2.0
3 * iommu.c: IOMMU specific routines for memory management.
5 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
6 * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
7 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
8 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
11 #include <linux/kernel.h>
12 #include <linux/init.h>
14 #include <linux/slab.h>
15 #include <linux/highmem.h> /* pte_offset_map => kmap_atomic */
16 #include <linux/dma-mapping.h>
18 #include <linux/of_device.h>
20 #include <asm/pgalloc.h>
21 #include <asm/pgtable.h>
25 #include <asm/cacheflush.h>
26 #include <asm/tlbflush.h>
27 #include <asm/bitext.h>
28 #include <asm/iommu.h>
34 * This can be sized dynamically, but we will do this
35 * only when we have a guidance about actual I/O pressures.
37 #define IOMMU_RNGE IOMMU_RNGE_256MB
38 #define IOMMU_START 0xF0000000
39 #define IOMMU_WINSIZE (256*1024*1024U)
40 #define IOMMU_NPTES (IOMMU_WINSIZE/PAGE_SIZE) /* 64K PTEs, 256KB */
41 #define IOMMU_ORDER 6 /* 4096 * (1<<6) */
43 static int viking_flush;
45 extern void viking_flush_page(unsigned long page);
46 extern void viking_mxcc_flush_page(unsigned long page);
49 * Values precomputed according to CPU type.
51 static unsigned int ioperm_noc; /* Consistent mapping iopte flags */
52 static pgprot_t dvma_prot; /* Consistent mapping pte flags */
54 #define IOPERM (IOPTE_CACHE | IOPTE_WRITE | IOPTE_VALID)
55 #define MKIOPTE(pfn, perm) (((((pfn)<<8) & IOPTE_PAGE) | (perm)) & ~IOPTE_WAZ)
57 static void __init sbus_iommu_init(struct platform_device *op)
59 struct iommu_struct *iommu;
60 unsigned int impl, vers;
61 unsigned long *bitmap;
62 unsigned long control;
66 iommu = kmalloc(sizeof(struct iommu_struct), GFP_KERNEL);
68 prom_printf("Unable to allocate iommu structure\n");
72 iommu->regs = of_ioremap(&op->resource[0], 0, PAGE_SIZE * 3,
75 prom_printf("Cannot map IOMMU registers\n");
79 control = sbus_readl(&iommu->regs->control);
80 impl = (control & IOMMU_CTRL_IMPL) >> 28;
81 vers = (control & IOMMU_CTRL_VERS) >> 24;
82 control &= ~(IOMMU_CTRL_RNGE);
83 control |= (IOMMU_RNGE_256MB | IOMMU_CTRL_ENAB);
84 sbus_writel(control, &iommu->regs->control);
86 iommu_invalidate(iommu->regs);
87 iommu->start = IOMMU_START;
88 iommu->end = 0xffffffff;
90 /* Allocate IOMMU page table */
91 /* Stupid alignment constraints give me a headache.
92 We need 256K or 512K or 1M or 2M area aligned to
93 its size and current gfp will fortunately give
95 tmp = __get_free_pages(GFP_KERNEL, IOMMU_ORDER);
97 prom_printf("Unable to allocate iommu table [0x%lx]\n",
98 IOMMU_NPTES * sizeof(iopte_t));
101 iommu->page_table = (iopte_t *)tmp;
103 /* Initialize new table. */
104 memset(iommu->page_table, 0, IOMMU_NPTES*sizeof(iopte_t));
108 base = __pa((unsigned long)iommu->page_table) >> 4;
109 sbus_writel(base, &iommu->regs->base);
110 iommu_invalidate(iommu->regs);
112 bitmap = kmalloc(IOMMU_NPTES>>3, GFP_KERNEL);
114 prom_printf("Unable to allocate iommu bitmap [%d]\n",
115 (int)(IOMMU_NPTES>>3));
118 bit_map_init(&iommu->usemap, bitmap, IOMMU_NPTES);
119 /* To be coherent on HyperSparc, the page color of DVMA
120 * and physical addresses must match.
122 if (srmmu_modtype == HyperSparc)
123 iommu->usemap.num_colors = vac_cache_size >> PAGE_SHIFT;
125 iommu->usemap.num_colors = 1;
127 printk(KERN_INFO "IOMMU: impl %d vers %d table 0x%p[%d B] map [%d b]\n",
128 impl, vers, iommu->page_table,
129 (int)(IOMMU_NPTES*sizeof(iopte_t)), (int)IOMMU_NPTES);
131 op->dev.archdata.iommu = iommu;
134 static int __init iommu_init(void)
136 struct device_node *dp;
138 for_each_node_by_name(dp, "iommu") {
139 struct platform_device *op = of_find_device_by_node(dp);
142 of_propagate_archdata(op);
148 subsys_initcall(iommu_init);
150 /* Flush the iotlb entries to ram. */
151 /* This could be better if we didn't have to flush whole pages. */
152 static void iommu_flush_iotlb(iopte_t *iopte, unsigned int niopte)
157 start = (unsigned long)iopte;
158 end = PAGE_ALIGN(start + niopte*sizeof(iopte_t));
160 if (viking_mxcc_present) {
162 viking_mxcc_flush_page(start);
165 } else if (viking_flush) {
167 viking_flush_page(start);
172 __flush_page_to_ram(start);
178 static u32 iommu_get_one(struct device *dev, phys_addr_t paddr, int npages)
180 struct iommu_struct *iommu = dev->archdata.iommu;
182 iopte_t *iopte, *iopte0;
183 unsigned int busa, busa0;
184 unsigned long pfn = __phys_to_pfn(paddr);
187 /* page color = pfn of page */
188 ioptex = bit_map_string_get(&iommu->usemap, npages, pfn);
191 busa0 = iommu->start + (ioptex << PAGE_SHIFT);
192 iopte0 = &iommu->page_table[ioptex];
196 for (i = 0; i < npages; i++) {
197 iopte_val(*iopte) = MKIOPTE(pfn, IOPERM);
198 iommu_invalidate_page(iommu->regs, busa);
204 iommu_flush_iotlb(iopte0, npages);
209 static dma_addr_t __sbus_iommu_map_page(struct device *dev, struct page *page,
210 unsigned long offset, size_t len)
212 void *vaddr = page_address(page) + offset;
213 unsigned long off = (unsigned long)vaddr & ~PAGE_MASK;
214 unsigned long npages = (off + len + PAGE_SIZE - 1) >> PAGE_SHIFT;
216 /* XXX So what is maxphys for us and how do drivers know it? */
217 if (!len || len > 256 * 1024)
218 return DMA_MAPPING_ERROR;
219 return iommu_get_one(dev, virt_to_phys(vaddr), npages) + off;
222 static dma_addr_t sbus_iommu_map_page_gflush(struct device *dev,
223 struct page *page, unsigned long offset, size_t len,
224 enum dma_data_direction dir, unsigned long attrs)
226 flush_page_for_dma(0);
227 return __sbus_iommu_map_page(dev, page, offset, len);
230 static dma_addr_t sbus_iommu_map_page_pflush(struct device *dev,
231 struct page *page, unsigned long offset, size_t len,
232 enum dma_data_direction dir, unsigned long attrs)
234 void *vaddr = page_address(page) + offset;
235 unsigned long p = ((unsigned long)vaddr) & PAGE_MASK;
237 while (p < (unsigned long)vaddr + len) {
238 flush_page_for_dma(p);
242 return __sbus_iommu_map_page(dev, page, offset, len);
245 static int __sbus_iommu_map_sg(struct device *dev, struct scatterlist *sgl,
246 int nents, enum dma_data_direction dir, unsigned long attrs,
249 unsigned long page, oldpage = 0;
250 struct scatterlist *sg;
253 for_each_sg(sgl, sg, nents, j) {
254 n = (sg->length + sg->offset + PAGE_SIZE-1) >> PAGE_SHIFT;
257 * We expect unmapped highmem pages to be not in the cache.
258 * XXX Is this a good assumption?
259 * XXX What if someone else unmaps it here and races us?
261 if (per_page_flush && !PageHighMem(sg_page(sg))) {
262 page = (unsigned long)page_address(sg_page(sg));
263 for (i = 0; i < n; i++) {
264 if (page != oldpage) { /* Already flushed? */
265 flush_page_for_dma(page);
272 sg->dma_address = iommu_get_one(dev, sg_phys(sg), n) + sg->offset;
273 sg->dma_length = sg->length;
279 static int sbus_iommu_map_sg_gflush(struct device *dev, struct scatterlist *sgl,
280 int nents, enum dma_data_direction dir, unsigned long attrs)
282 flush_page_for_dma(0);
283 return __sbus_iommu_map_sg(dev, sgl, nents, dir, attrs, false);
286 static int sbus_iommu_map_sg_pflush(struct device *dev, struct scatterlist *sgl,
287 int nents, enum dma_data_direction dir, unsigned long attrs)
289 return __sbus_iommu_map_sg(dev, sgl, nents, dir, attrs, true);
292 static void sbus_iommu_unmap_page(struct device *dev, dma_addr_t dma_addr,
293 size_t len, enum dma_data_direction dir, unsigned long attrs)
295 struct iommu_struct *iommu = dev->archdata.iommu;
296 unsigned int busa = dma_addr & PAGE_MASK;
297 unsigned long off = dma_addr & ~PAGE_MASK;
298 unsigned int npages = (off + len + PAGE_SIZE-1) >> PAGE_SHIFT;
299 unsigned int ioptex = (busa - iommu->start) >> PAGE_SHIFT;
302 BUG_ON(busa < iommu->start);
303 for (i = 0; i < npages; i++) {
304 iopte_val(iommu->page_table[ioptex + i]) = 0;
305 iommu_invalidate_page(iommu->regs, busa);
308 bit_map_clear(&iommu->usemap, ioptex, npages);
311 static void sbus_iommu_unmap_sg(struct device *dev, struct scatterlist *sgl,
312 int nents, enum dma_data_direction dir, unsigned long attrs)
314 struct scatterlist *sg;
317 for_each_sg(sgl, sg, nents, i) {
318 sbus_iommu_unmap_page(dev, sg->dma_address, sg->length, dir,
320 sg->dma_address = 0x21212121;
325 static void *sbus_iommu_alloc(struct device *dev, size_t len,
326 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
328 struct iommu_struct *iommu = dev->archdata.iommu;
329 unsigned long va, addr, page, end, ret;
330 iopte_t *iopte = iommu->page_table;
334 /* XXX So what is maxphys for us and how do drivers know it? */
335 if (!len || len > 256 * 1024)
338 len = PAGE_ALIGN(len);
339 va = __get_free_pages(gfp | __GFP_ZERO, get_order(len));
343 addr = ret = sparc_dma_alloc_resource(dev, len);
347 BUG_ON((va & ~PAGE_MASK) != 0);
348 BUG_ON((addr & ~PAGE_MASK) != 0);
349 BUG_ON((len & ~PAGE_MASK) != 0);
351 /* page color = physical address */
352 ioptex = bit_map_string_get(&iommu->usemap, len >> PAGE_SHIFT,
367 if (viking_mxcc_present)
368 viking_mxcc_flush_page(page);
369 else if (viking_flush)
370 viking_flush_page(page);
372 __flush_page_to_ram(page);
374 pgdp = pgd_offset(&init_mm, addr);
375 pmdp = pmd_offset(pgdp, addr);
376 ptep = pte_offset_map(pmdp, addr);
378 set_pte(ptep, mk_pte(virt_to_page(page), dvma_prot));
380 iopte_val(*iopte++) =
381 MKIOPTE(page_to_pfn(virt_to_page(page)), ioperm_noc);
385 /* P3: why do we need this?
387 * DAVEM: Because there are several aspects, none of which
388 * are handled by a single interface. Some cpus are
389 * completely not I/O DMA coherent, and some have
390 * virtually indexed caches. The driver DMA flushing
391 * methods handle the former case, but here during
392 * IOMMU page table modifications, and usage of non-cacheable
393 * cpu mappings of pages potentially in the cpu caches, we have
394 * to handle the latter case as well.
397 iommu_flush_iotlb(first, len >> PAGE_SHIFT);
399 iommu_invalidate(iommu->regs);
401 *dma_handle = iommu->start + (ioptex << PAGE_SHIFT);
405 free_pages(va, get_order(len));
409 static void sbus_iommu_free(struct device *dev, size_t len, void *cpu_addr,
410 dma_addr_t busa, unsigned long attrs)
412 struct iommu_struct *iommu = dev->archdata.iommu;
413 iopte_t *iopte = iommu->page_table;
414 struct page *page = virt_to_page(cpu_addr);
415 int ioptex = (busa - iommu->start) >> PAGE_SHIFT;
418 if (!sparc_dma_free_resource(cpu_addr, len))
421 BUG_ON((busa & ~PAGE_MASK) != 0);
422 BUG_ON((len & ~PAGE_MASK) != 0);
427 iopte_val(*iopte++) = 0;
431 iommu_invalidate(iommu->regs);
432 bit_map_clear(&iommu->usemap, ioptex, len >> PAGE_SHIFT);
434 __free_pages(page, get_order(len));
438 static const struct dma_map_ops sbus_iommu_dma_gflush_ops = {
440 .alloc = sbus_iommu_alloc,
441 .free = sbus_iommu_free,
443 .map_page = sbus_iommu_map_page_gflush,
444 .unmap_page = sbus_iommu_unmap_page,
445 .map_sg = sbus_iommu_map_sg_gflush,
446 .unmap_sg = sbus_iommu_unmap_sg,
449 static const struct dma_map_ops sbus_iommu_dma_pflush_ops = {
451 .alloc = sbus_iommu_alloc,
452 .free = sbus_iommu_free,
454 .map_page = sbus_iommu_map_page_pflush,
455 .unmap_page = sbus_iommu_unmap_page,
456 .map_sg = sbus_iommu_map_sg_pflush,
457 .unmap_sg = sbus_iommu_unmap_sg,
460 void __init ld_mmu_iommu(void)
462 if (flush_page_for_dma_global) {
463 /* flush_page_for_dma flushes everything, no matter of what page is it */
464 dma_ops = &sbus_iommu_dma_gflush_ops;
466 dma_ops = &sbus_iommu_dma_pflush_ops;
469 if (viking_mxcc_present || srmmu_modtype == HyperSparc) {
470 dvma_prot = __pgprot(SRMMU_CACHE | SRMMU_ET_PTE | SRMMU_PRIV);
471 ioperm_noc = IOPTE_CACHE | IOPTE_WRITE | IOPTE_VALID;
473 dvma_prot = __pgprot(SRMMU_ET_PTE | SRMMU_PRIV);
474 ioperm_noc = IOPTE_WRITE | IOPTE_VALID;