1 // SPDX-License-Identifier: GPL-2.0
3 * linux/arch/sparc64/kernel/setup.c
5 * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
6 * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
9 #include <linux/errno.h>
10 #include <linux/sched.h>
11 #include <linux/kernel.h>
13 #include <linux/stddef.h>
14 #include <linux/unistd.h>
15 #include <linux/ptrace.h>
17 #include <linux/user.h>
18 #include <linux/screen_info.h>
19 #include <linux/delay.h>
21 #include <linux/seq_file.h>
22 #include <linux/syscalls.h>
23 #include <linux/kdev_t.h>
24 #include <linux/major.h>
25 #include <linux/string.h>
26 #include <linux/init.h>
27 #include <linux/inet.h>
28 #include <linux/console.h>
29 #include <linux/root_dev.h>
30 #include <linux/interrupt.h>
31 #include <linux/cpu.h>
32 #include <linux/initrd.h>
33 #include <linux/module.h>
34 #include <linux/start_kernel.h>
35 #include <linux/bootmem.h>
38 #include <asm/processor.h>
39 #include <asm/oplib.h>
41 #include <asm/pgtable.h>
42 #include <asm/idprom.h>
44 #include <asm/starfire.h>
45 #include <asm/mmu_context.h>
46 #include <asm/timer.h>
47 #include <asm/sections.h>
48 #include <asm/setup.h>
50 #include <asm/ns87303.h>
51 #include <asm/btext.h>
53 #include <asm/mdesc.h>
54 #include <asm/cacheflush.h>
59 #include <net/ipconfig.h>
65 /* Used to synchronize accesses to NatSemi SUPER I/O chip configure
66 * operations in asm/ns87303.h
68 DEFINE_SPINLOCK(ns87303_lock);
69 EXPORT_SYMBOL(ns87303_lock);
71 struct screen_info screen_info = {
72 0, 0, /* orig-x, orig-y */
74 0, /* orig-video-page */
75 0, /* orig-video-mode */
76 128, /* orig-video-cols */
77 0, 0, 0, /* unused, ega_bx, unused */
78 54, /* orig-video-lines */
79 0, /* orig-video-isVGA */
80 16 /* orig-video-points */
84 prom_console_write(struct console *con, const char *s, unsigned int n)
89 /* Exported for mm/init.c:paging_init. */
90 unsigned long cmdline_memory_size = 0;
92 static struct console prom_early_console = {
94 .write = prom_console_write,
95 .flags = CON_PRINTBUFFER | CON_BOOT | CON_ANYTIME,
100 * Process kernel command line switches that are specific to the
101 * SPARC or that require special low-level processing.
103 static void __init process_switch(char c)
110 prom_printf("boot_flags_init: Halt!\n");
114 prom_early_console.flags &= ~CON_BOOT;
117 /* Force UltraSPARC-III P-Cache on. */
118 if (tlb_type != cheetah) {
119 printk("BOOT: Ignoring P-Cache force option.\n");
122 cheetah_pcache_forced_on = 1;
123 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
124 cheetah_enable_pcache();
128 printk("Unknown boot switch (-%c)\n", c);
133 static void __init boot_flags_init(char *commands)
136 /* Move to the start of the next "argument". */
137 while (*commands == ' ')
140 /* Process any command switches, otherwise skip it. */
141 if (*commands == '\0')
143 if (*commands == '-') {
145 while (*commands && *commands != ' ')
146 process_switch(*commands++);
149 if (!strncmp(commands, "mem=", 4))
150 cmdline_memory_size = memparse(commands + 4, &commands);
152 while (*commands && *commands != ' ')
157 extern unsigned short root_flags;
158 extern unsigned short root_dev;
159 extern unsigned short ram_flags;
160 #define RAMDISK_IMAGE_START_MASK 0x07FF
161 #define RAMDISK_PROMPT_FLAG 0x8000
162 #define RAMDISK_LOAD_FLAG 0x4000
164 extern int root_mountflags;
166 char reboot_command[COMMAND_LINE_SIZE];
168 static struct pt_regs fake_swapper_regs = { { 0, }, 0, 0, 0, 0 };
170 static void __init per_cpu_patch(void)
172 struct cpuid_patch_entry *p;
176 if (tlb_type == spitfire && !this_is_starfire)
180 if (tlb_type != hypervisor) {
181 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
182 is_jbus = ((ver >> 32UL) == __JALAPENO_ID ||
183 (ver >> 32UL) == __SERRANO_ID);
187 while (p < &__cpuid_patch_end) {
188 unsigned long addr = p->addr;
193 insns = &p->starfire[0];
198 insns = &p->cheetah_jbus[0];
200 insns = &p->cheetah_safari[0];
203 insns = &p->sun4v[0];
206 prom_printf("Unknown cpu type, halting.\n");
210 *(unsigned int *) (addr + 0) = insns[0];
212 __asm__ __volatile__("flush %0" : : "r" (addr + 0));
214 *(unsigned int *) (addr + 4) = insns[1];
216 __asm__ __volatile__("flush %0" : : "r" (addr + 4));
218 *(unsigned int *) (addr + 8) = insns[2];
220 __asm__ __volatile__("flush %0" : : "r" (addr + 8));
222 *(unsigned int *) (addr + 12) = insns[3];
224 __asm__ __volatile__("flush %0" : : "r" (addr + 12));
230 void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry *start,
231 struct sun4v_1insn_patch_entry *end)
233 while (start < end) {
234 unsigned long addr = start->addr;
236 *(unsigned int *) (addr + 0) = start->insn;
238 __asm__ __volatile__("flush %0" : : "r" (addr + 0));
244 void sun4v_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
245 struct sun4v_2insn_patch_entry *end)
247 while (start < end) {
248 unsigned long addr = start->addr;
250 *(unsigned int *) (addr + 0) = start->insns[0];
252 __asm__ __volatile__("flush %0" : : "r" (addr + 0));
254 *(unsigned int *) (addr + 4) = start->insns[1];
256 __asm__ __volatile__("flush %0" : : "r" (addr + 4));
262 void sun_m7_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
263 struct sun4v_2insn_patch_entry *end)
265 while (start < end) {
266 unsigned long addr = start->addr;
268 *(unsigned int *) (addr + 0) = start->insns[0];
270 __asm__ __volatile__("flush %0" : : "r" (addr + 0));
272 *(unsigned int *) (addr + 4) = start->insns[1];
274 __asm__ __volatile__("flush %0" : : "r" (addr + 4));
280 static void __init sun4v_patch(void)
282 extern void sun4v_hvapi_init(void);
284 if (tlb_type != hypervisor)
287 sun4v_patch_1insn_range(&__sun4v_1insn_patch,
288 &__sun4v_1insn_patch_end);
290 sun4v_patch_2insn_range(&__sun4v_2insn_patch,
291 &__sun4v_2insn_patch_end);
293 switch (sun4v_chip_type) {
294 case SUN4V_CHIP_SPARC_M7:
295 case SUN4V_CHIP_SPARC_M8:
296 case SUN4V_CHIP_SPARC_SN:
297 sun_m7_patch_2insn_range(&__sun_m7_2insn_patch,
298 &__sun_m7_2insn_patch_end);
304 if (sun4v_chip_type != SUN4V_CHIP_NIAGARA1) {
305 sun4v_patch_1insn_range(&__fast_win_ctrl_1insn_patch,
306 &__fast_win_ctrl_1insn_patch_end);
312 static void __init popc_patch(void)
314 struct popc_3insn_patch_entry *p3;
315 struct popc_6insn_patch_entry *p6;
317 p3 = &__popc_3insn_patch;
318 while (p3 < &__popc_3insn_patch_end) {
319 unsigned long i, addr = p3->addr;
321 for (i = 0; i < 3; i++) {
322 *(unsigned int *) (addr + (i * 4)) = p3->insns[i];
324 __asm__ __volatile__("flush %0"
325 : : "r" (addr + (i * 4)));
331 p6 = &__popc_6insn_patch;
332 while (p6 < &__popc_6insn_patch_end) {
333 unsigned long i, addr = p6->addr;
335 for (i = 0; i < 6; i++) {
336 *(unsigned int *) (addr + (i * 4)) = p6->insns[i];
338 __asm__ __volatile__("flush %0"
339 : : "r" (addr + (i * 4)));
346 static void __init pause_patch(void)
348 struct pause_patch_entry *p;
350 p = &__pause_3insn_patch;
351 while (p < &__pause_3insn_patch_end) {
352 unsigned long i, addr = p->addr;
354 for (i = 0; i < 3; i++) {
355 *(unsigned int *) (addr + (i * 4)) = p->insns[i];
357 __asm__ __volatile__("flush %0"
358 : : "r" (addr + (i * 4)));
365 void __init start_early_boot(void)
374 cpu = hard_smp_processor_id();
375 if (cpu >= NR_CPUS) {
376 prom_printf("Serious problem, boot cpu id (%d) >= NR_CPUS (%d)\n",
380 current_thread_info()->cpu = cpu;
387 /* On Ultra, we support all of the v8 capabilities. */
388 unsigned long sparc64_elf_hwcap = (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR |
389 HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV |
391 EXPORT_SYMBOL(sparc64_elf_hwcap);
393 static const char *hwcaps[] = {
394 "flush", "stbar", "swap", "muldiv", "v9",
395 "ultra3", "blkinit", "n2",
397 /* These strings are as they appear in the machine description
398 * 'hwcap-list' property for cpu nodes.
400 "mul32", "div32", "fsmuld", "v8plus", "popc", "vis", "vis2",
401 "ASIBlkInit", "fmaf", "vis3", "hpc", "random", "trans", "fjfmau",
402 "ima", "cspare", "pause", "cbcond", NULL /*reserved for crypto */,
406 static const char *crypto_hwcaps[] = {
407 "aes", "des", "kasumi", "camellia", "md5", "sha1", "sha256",
408 "sha512", "mpmul", "montmul", "montsqr", "crc32c",
411 void cpucap_info(struct seq_file *m)
413 unsigned long caps = sparc64_elf_hwcap;
416 seq_puts(m, "cpucaps\t\t: ");
417 for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
418 unsigned long bit = 1UL << i;
419 if (hwcaps[i] && (caps & bit)) {
420 seq_printf(m, "%s%s",
421 printed ? "," : "", hwcaps[i]);
425 if (caps & HWCAP_SPARC_CRYPTO) {
428 __asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
429 for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
430 unsigned long bit = 1UL << i;
432 seq_printf(m, "%s%s",
433 printed ? "," : "", crypto_hwcaps[i]);
441 static void __init report_one_hwcap(int *printed, const char *name)
444 printk(KERN_INFO "CPU CAPS: [");
445 printk(KERN_CONT "%s%s",
446 (*printed) ? "," : "", name);
447 if (++(*printed) == 8) {
448 printk(KERN_CONT "]\n");
453 static void __init report_crypto_hwcaps(int *printed)
458 __asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
460 for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
461 unsigned long bit = 1UL << i;
463 report_one_hwcap(printed, crypto_hwcaps[i]);
467 static void __init report_hwcaps(unsigned long caps)
471 for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
472 unsigned long bit = 1UL << i;
473 if (hwcaps[i] && (caps & bit))
474 report_one_hwcap(&printed, hwcaps[i]);
476 if (caps & HWCAP_SPARC_CRYPTO)
477 report_crypto_hwcaps(&printed);
479 printk(KERN_CONT "]\n");
482 static unsigned long __init mdesc_cpu_hwcap_list(void)
484 struct mdesc_handle *hp;
485 unsigned long caps = 0;
494 pn = mdesc_node_by_name(hp, MDESC_NODE_NULL, "cpu");
495 if (pn == MDESC_NODE_NULL)
498 prop = mdesc_get_property(hp, pn, "hwcap-list", &len);
505 for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
506 unsigned long bit = 1UL << i;
508 if (hwcaps[i] && !strcmp(prop, hwcaps[i])) {
513 for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
514 if (!strcmp(prop, crypto_hwcaps[i]))
515 caps |= HWCAP_SPARC_CRYPTO;
518 plen = strlen(prop) + 1;
528 /* This yields a mask that user programs can use to figure out what
529 * instruction set this cpu supports.
531 static void __init init_sparc64_elf_hwcap(void)
533 unsigned long cap = sparc64_elf_hwcap;
534 unsigned long mdesc_caps;
536 if (tlb_type == cheetah || tlb_type == cheetah_plus)
537 cap |= HWCAP_SPARC_ULTRA3;
538 else if (tlb_type == hypervisor) {
539 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||
540 sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
541 sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
542 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
543 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
544 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
545 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
546 sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
547 sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
548 sun4v_chip_type == SUN4V_CHIP_SPARC64X)
549 cap |= HWCAP_SPARC_BLKINIT;
550 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
551 sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
552 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
553 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
554 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
555 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
556 sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
557 sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
558 sun4v_chip_type == SUN4V_CHIP_SPARC64X)
559 cap |= HWCAP_SPARC_N2;
562 cap |= (AV_SPARC_MUL32 | AV_SPARC_DIV32 | AV_SPARC_V8PLUS);
564 mdesc_caps = mdesc_cpu_hwcap_list();
566 if (tlb_type == spitfire)
568 if (tlb_type == cheetah || tlb_type == cheetah_plus)
569 cap |= AV_SPARC_VIS | AV_SPARC_VIS2;
570 if (tlb_type == cheetah_plus) {
571 unsigned long impl, ver;
573 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
574 impl = ((ver >> 32) & 0xffff);
575 if (impl == PANTHER_IMPL)
576 cap |= AV_SPARC_POPC;
578 if (tlb_type == hypervisor) {
579 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1)
580 cap |= AV_SPARC_ASI_BLK_INIT;
581 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
582 sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
583 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
584 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
585 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
586 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
587 sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
588 sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
589 sun4v_chip_type == SUN4V_CHIP_SPARC64X)
590 cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 |
591 AV_SPARC_ASI_BLK_INIT |
593 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
594 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
595 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
596 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
597 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
598 sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
599 sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
600 sun4v_chip_type == SUN4V_CHIP_SPARC64X)
601 cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC |
605 sparc64_elf_hwcap = cap | mdesc_caps;
607 report_hwcaps(sparc64_elf_hwcap);
609 if (sparc64_elf_hwcap & AV_SPARC_POPC)
611 if (sparc64_elf_hwcap & AV_SPARC_PAUSE)
615 void __init alloc_irqstack_bootmem(void)
617 unsigned int i, node;
619 for_each_possible_cpu(i) {
620 node = cpu_to_node(i);
622 softirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
625 hardirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
631 void __init setup_arch(char **cmdline_p)
633 /* Initialize PROM console and command line. */
634 *cmdline_p = prom_getbootargs();
635 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
638 boot_flags_init(*cmdline_p);
639 #ifdef CONFIG_EARLYFB
640 if (btext_find_display())
642 register_console(&prom_early_console);
644 if (tlb_type == hypervisor)
645 printk("ARCH: SUN4V\n");
647 printk("ARCH: SUN4U\n");
649 #ifdef CONFIG_DUMMY_CONSOLE
650 conswitchp = &dummy_con;
656 root_mountflags &= ~MS_RDONLY;
657 ROOT_DEV = old_decode_dev(root_dev);
658 #ifdef CONFIG_BLK_DEV_RAM
659 rd_image_start = ram_flags & RAMDISK_IMAGE_START_MASK;
660 rd_prompt = ((ram_flags & RAMDISK_PROMPT_FLAG) != 0);
661 rd_doload = ((ram_flags & RAMDISK_LOAD_FLAG) != 0);
664 task_thread_info(&init_task)->kregs = &fake_swapper_regs;
667 if (!ic_set_manually) {
668 phandle chosen = prom_finddevice("/chosen");
671 cl = prom_getintdefault (chosen, "client-ip", 0);
672 sv = prom_getintdefault (chosen, "server-ip", 0);
673 gw = prom_getintdefault (chosen, "gateway-ip", 0);
679 #if defined(CONFIG_IP_PNP_BOOTP) || defined(CONFIG_IP_PNP_RARP)
680 ic_proto_enabled = 0;
686 /* Get boot processor trap_block[] setup. */
687 init_cur_cpu_trap(current_thread_info());
690 init_sparc64_elf_hwcap();
691 smp_fill_in_cpu_possible_map();
693 * Once the OF device tree and MDESC have been setup and nr_cpus has
694 * been parsed, we know the list of possible cpus. Therefore we can
695 * allocate the IRQ stacks.
697 alloc_irqstack_bootmem();
700 extern int stop_a_enabled;
702 void sun_do_break(void)
708 flush_user_windows();
712 EXPORT_SYMBOL(sun_do_break);
714 int stop_a_enabled = 1;
715 EXPORT_SYMBOL(stop_a_enabled);