2 * head.S: The initial boot code for the Sparc port of Linux.
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1995,1999 Pete Zaitcev (zaitcev@yahoo.com)
6 * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
7 * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 * Copyright (C) 1997 Michael A. Griffith (grif@acm.org)
10 * CompactPCI platform by Eric Brower, 1999.
13 #include <linux/version.h>
14 #include <linux/init.h>
18 #include <asm/contregs.h>
19 #include <asm/ptrace.h>
22 #include <asm/kdebug.h>
23 #include <asm/winmacro.h>
24 #include <asm/thread_info.h> /* TI_UWINMASK */
25 #include <asm/errno.h>
26 #include <asm/pgtsrmmu.h> /* SRMMU_PGDIR_SHIFT */
29 /* The following are used with the prom_vector node-ops to figure out
42 /* Tested on SS-5, SS-10 */
50 .asciz "Sparc-Linux sun4/sun4c support does no longer exist.\n\n"
54 .asciz "Sparc-Linux sun4e support does not exist\n\n"
57 /* The trap-table - located in the __HEAD section */
58 #include "ttable_32.S"
62 /* This was the only reasonable way I could think of to properly align
63 * these page-table data structures.
66 swapper_pg_dir: .skip PAGE_SIZE
67 .globl empty_zero_page
68 empty_zero_page: .skip PAGE_SIZE
73 .global sparc_ramdisk_image
74 .global sparc_ramdisk_size
76 /* This stuff has to be in sync with SILO and other potential boot loaders
77 * Fields should be kept upward compatible and whenever any change is made,
78 * HdrS version should be incremented.
81 .word LINUX_VERSION_CODE
82 .half 0x0203 /* HdrS version */
97 /* Cool, here we go. Pick up the romvec pointer in %o0 and stash it in
98 * %g7 and at prom_vector_p. And also quickly check whether we are on
99 * a v0, v2, or v3 prom.
102 /* Ok, it's nice to know, as early as possible, if we
103 * are already mapped where we expect to be in virtual
104 * memory. The Solaris /boot elf format bootloader
105 * will peek into our elf header and load us where
106 * we want to be, otherwise we have to re-map.
108 * Some boot loaders don't place the jmp'rs address
109 * in %o7, so we do a pc-relative call to a local
110 * label, then see what %o7 has.
113 mov %o7, %g4 ! Save %o7
115 /* Jump to it, and pray... */
125 mov %g4, %o7 /* Previous %o7. */
127 mov %o0, %l0 ! stash away romvec
128 mov %o0, %g7 ! put it here too
129 mov %o1, %l1 ! stash away debug_vec too
131 /* Ok, let's check out our run time program counter. */
137 /* %l6 will hold the offset we have to subtract
138 * from absolute symbols in order to access areas
139 * in our own image. If already mapped this is
140 * just plain zero, else it is KERNBASE.
149 /* Copy over the Prom's level 14 clock handler. */
153 * preserve our linked/calculated instructions
157 sub %g1, %l6, %g1 ! translate to physical
158 sub %g3, %l6, %g3 ! translate to physical
165 andn %g1, 0xfff, %g1 ! proms trap table base
166 or %g0, (0x1e<<4), %g2 ! offset to lvl14 intr
173 std %g4, [%g3 + 0x8] ! Copy proms handler
175 /* DON'T TOUCH %l0 thru %l5 in these remapping routines,
176 * we need their values afterwards!
179 /* Now check whether we are already mapped, if we
180 * are we can skip all this garbage coming up.
184 be go_to_highmem ! this will be a nop then
187 /* Validate that we are in fact running on an
197 set sun4c_notsup, %o0
205 lda [%g0] ASI_M_MMUREGS, %g1
207 be halt_sun4_or_sun4c
211 /* First, check for a viking (TI) module. */
219 /* Figure out what kind of viking we are on.
220 * We need to know if we have to play with the
221 * AC bit and disable traps or not.
224 /* I've only seen MicroSparc's on SparcClassics with this
228 lda [%g0] ASI_M_MMUREGS, %g3 ! peek in the control reg
231 bnz srmmu_nviking ! is in mbus mode
234 rd %psr, %g3 ! DO NOT TOUCH %g3
235 andn %g3, PSR_ET, %g2
239 /* Get context table pointer, then convert to
240 * a physical address, which is 36 bits.
243 lda [%g4] ASI_M_MMUREGS, %g4
244 sll %g4, 0x4, %g4 ! We use this below
247 /* Set the AC bit in the Viking's MMU control reg. */
248 lda [%g0] ASI_M_MMUREGS, %g5 ! DO NOT TOUCH %g5
249 set 0x8000, %g6 ! AC bit mask
250 or %g5, %g6, %g6 ! Or it in...
251 sta %g6, [%g0] ASI_M_MMUREGS ! Close your eyes...
253 /* Grrr, why does it seem like every other load/store
254 * on the sun4m is in some ASI space...
255 * Fine with me, let's get the pointer to the level 1
256 * page table directory and fetch its entry.
258 lda [%g4] ASI_M_BYPASS, %o1 ! This is a level 1 ptr
259 srl %o1, 0x4, %o1 ! Clear low 4 bits
260 sll %o1, 0x8, %o1 ! Make physical
262 /* Ok, pull in the PTD. */
263 lda [%o1] ASI_M_BYPASS, %o2 ! This is the 0x0 16MB pgd
265 /* Calculate to KERNBASE entry. */
266 add %o1, KERNBASE >> (SRMMU_PGDIR_SHIFT - 2), %o3
268 /* Poke the entry into the calculated address. */
269 sta %o2, [%o3] ASI_M_BYPASS
271 /* I don't get it Sun, if you engineered all these
272 * boot loaders and the PROM (thank you for the debugging
273 * features btw) why did you not have them load kernel
274 * images up in high address space, since this is necessary
275 * for ABI compliance anyways? Does this low-mapping provide
276 * enhanced interoperability?
278 * "The PROM is the computer."
281 /* Ok, restore the MMU control register we saved in %g5 */
282 sta %g5, [%g0] ASI_M_MMUREGS ! POW... ouch
284 /* Turn traps back on. We saved it in %g3 earlier. */
285 wr %g3, 0x0, %psr ! tick tock, tick tock
287 /* Now we burn precious CPU cycles due to bad engineering. */
290 /* Wow, all that just to move a 32-bit value from one
291 * place to another... Jump to high memory.
296 /* This works on viking's in Mbus mode and all
297 * other MBUS modules. It is virtually the same as
298 * the above madness sans turning traps off and flipping
303 lda [%g1] ASI_M_MMUREGS, %g1 ! get ctx table ptr
304 sll %g1, 0x4, %g1 ! make physical addr
305 lda [%g1] ASI_M_BYPASS, %g1 ! ptr to level 1 pg_table
307 sll %g1, 0x8, %g1 ! make phys addr for l1 tbl
309 lda [%g1] ASI_M_BYPASS, %g2 ! get level1 entry for 0x0
310 add %g1, KERNBASE >> (SRMMU_PGDIR_SHIFT - 2), %g3
311 sta %g2, [%g3] ASI_M_BYPASS ! place at KERNBASE entry
316 /* Now do a non-relative jump so that PC is in high-memory */
318 set execute_in_high_mem, %g1
322 /* The code above should be at beginning and we have to take care about
323 * short jumps, as branching to .init.text section from .text is usually
326 /* Acquire boot time privileged register values, this will help debugging.
327 * I figure out and store nwindows and nwindowsm1 later on.
330 mov %l0, %o0 ! put back romvec
331 mov %l1, %o1 ! and debug_vec
333 sethi %hi(prom_vector_p), %g1
334 st %o0, [%g1 + %lo(prom_vector_p)]
336 sethi %hi(linux_dbvec), %g1
337 st %o1, [%g1 + %lo(linux_dbvec)]
339 /* Get the machine type via the mysterious romvec node operations. */
345 or %g0, %g0, %o0 ! next_node(0) = first_node
348 sethi %hi(cputypvar), %o1 ! First node has cpu-arch
349 or %o1, %lo(cputypvar), %o1
350 sethi %hi(cputypval), %o2 ! information, the string
351 or %o2, %lo(cputypval), %o2
352 ld [%l1], %l0 ! 'compatible' tells
353 ld [%l0 + 0xc], %l0 ! that we want 'sun4x' where
354 call %l0 ! x is one of 'm', 'd' or 'e'.
355 nop ! %o2 holds pointer
356 ! to a buf where above string
357 ! will get stored by the prom.
359 #ifdef CONFIG_SPARC_LEON
360 /* no cpu-type check is needed, it is a SPARC-LEON */
362 sethi %hi(boot_cpu_id), %g2 ! boot-cpu index
365 ldub [%g2 + %lo(boot_cpu_id)], %g1
366 cmp %g1, 0xff ! unset means first CPU
367 bne leon_smp_cpu_startup ! continue only with master
370 /* Get CPU-ID from most significant 4-bit of ASR17 */
374 /* Update boot_cpu_id only on boot cpu */
375 stub %g1, [%g2 + %lo(boot_cpu_id)]
381 /* Check to cputype. We may be booted on a sun4u (64 bit box),
382 * and sun4d needs special treatment.
386 ldub [%o2 + 0x4], %l1
395 be no_sun4e_here ! Could be a sun4e.
397 b no_sun4u_here ! AIEEE, a V9 sun4u... Get our BIG BROTHER kernel :))
400 /* CPUID in bootbus can be found at PA 0xff0140000 */
401 #define SUN4D_BOOTBUS_CPUID 0xf0140000
404 /* Need to patch call to handler_irq */
405 set patch_handler_irq, %g4
406 set sun4d_handler_irq, %g5
407 sethi %hi(0x40000000), %g3 ! call
414 /* Get our CPU id out of bootbus */
415 set SUN4D_BOOTBUS_CPUID, %g3
416 lduba [%g3] ASI_M_CTL, %g3
419 sta %g4, [%g0] ASI_M_VIKING_TMP1
420 sethi %hi(boot_cpu_id), %g5
421 stb %g4, [%g5 + %lo(boot_cpu_id)]
424 /* Fall through to sun4m_init */
427 /* Ok, the PROM could have done funny things and apple cider could still
428 * be sitting in the fault status/address registers. Read them all to
429 * clear them so we don't get magic faults later on.
431 /* This sucks, apparently this makes Vikings call prom panic, will fix later */
434 srl %o1, 28, %o1 ! Get a type of the CPU
436 subcc %o1, 4, %g0 ! TI: Viking or MicroSPARC
441 lda [%o0] ASI_M_MMUREGS, %g0
443 lda [%o0] ASI_M_MMUREGS, %g0
445 /* Fujitsu MicroSPARC-II has no asynchronous flavors of FARs */
451 lda [%o0] ASI_M_MMUREGS, %g0
453 lda [%o0] ASI_M_MMUREGS, %g0
459 /* Aieee, now set PC and nPC, enable traps, give ourselves a stack and it's
463 sethi %hi(cputyp), %o0
464 st %g4, [%o0 + %lo(cputyp)]
466 /* Turn on Supervisor, EnableFloating, and all the PIL bits.
467 * Also puts us in register window zero with traps off.
469 set (PSR_PS | PSR_S | PSR_PIL | PSR_EF), %g2
473 /* I want a kernel stack NOW! */
474 set init_thread_union, %g1
475 set (THREAD_SIZE - STACKFRAME_SZ), %g2
477 mov 0, %fp /* And for good luck */
479 /* Zero out our BSS section. */
480 set __bss_start , %o0 ! First address of BSS
481 set _end , %o1 ! Last address of BSS
489 /* If boot_cpu_id has not been setup by machine specific
490 * init-code above we default it to zero.
492 sethi %hi(boot_cpu_id), %g2
493 ldub [%g2 + %lo(boot_cpu_id)], %g3
498 stub %g3, [%g2 + %lo(boot_cpu_id)]
502 /* Initialize the uwinmask value for init task just in case.
503 * But first make current_set[boot_cpu_id] point to something useful.
505 set init_thread_union, %g6
513 st %g0, [%g6 + TI_UWINMASK]
515 /* Compute NWINDOWS and stash it away. Now uses %wim trick explained
516 * in the V8 manual. Ok, this method seems to work, Sparc is cool...
517 * No, it doesn't work, have to play the save/readCWP/restore trick.
520 wr %g0, 0x0, %wim ! so we do not get a trap
533 wr %g1, 0x0, %wim ! make window 1 invalid
540 /* Adjust our window handling routines to
541 * do things correctly on 7 window Sparcs.
544 #define PATCH_INSN(src, dest) \
550 /* Patch for window spills... */
551 PATCH_INSN(spnwin_patch1_7win, spnwin_patch1)
552 PATCH_INSN(spnwin_patch2_7win, spnwin_patch2)
553 PATCH_INSN(spnwin_patch3_7win, spnwin_patch3)
555 /* Patch for window fills... */
556 PATCH_INSN(fnwin_patch1_7win, fnwin_patch1)
557 PATCH_INSN(fnwin_patch2_7win, fnwin_patch2)
559 /* Patch for trap entry setup... */
560 PATCH_INSN(tsetup_7win_patch1, tsetup_patch1)
561 PATCH_INSN(tsetup_7win_patch2, tsetup_patch2)
562 PATCH_INSN(tsetup_7win_patch3, tsetup_patch3)
563 PATCH_INSN(tsetup_7win_patch4, tsetup_patch4)
564 PATCH_INSN(tsetup_7win_patch5, tsetup_patch5)
565 PATCH_INSN(tsetup_7win_patch6, tsetup_patch6)
567 /* Patch for returning from traps... */
568 PATCH_INSN(rtrap_7win_patch1, rtrap_patch1)
569 PATCH_INSN(rtrap_7win_patch2, rtrap_patch2)
570 PATCH_INSN(rtrap_7win_patch3, rtrap_patch3)
571 PATCH_INSN(rtrap_7win_patch4, rtrap_patch4)
572 PATCH_INSN(rtrap_7win_patch5, rtrap_patch5)
574 /* Patch for killing user windows from the register file. */
575 PATCH_INSN(kuw_patch1_7win, kuw_patch1)
577 /* Now patch the kernel window flush sequences.
578 * This saves 2 traps on every switch and fork.
581 set flush_patch_one, %g5
584 set flush_patch_two, %g5
587 set flush_patch_three, %g5
590 set flush_patch_four, %g5
593 set flush_patch_exception, %g5
596 set flush_patch_switch, %g5
601 sethi %hi(nwindows), %g4
602 st %g3, [%g4 + %lo(nwindows)] ! store final value
604 sethi %hi(nwindowsm1), %g4
605 st %g3, [%g4 + %lo(nwindowsm1)]
607 /* Here we go, start using Linux's trap table... */
612 /* Finally, turn on traps so that we can call c-code. */
620 /* First we call prom_init() to set up PROMLIB, then
621 * off to start_kernel().
624 sethi %hi(prom_vector_p), %g5
625 ld [%g5 + %lo(prom_vector_p)], %o0
632 /* We should not get here. */
638 set sun4e_notsup, %o0
662 .asciz "\n\rOn sun4u you have to use UltraLinux (64bit) kernel\n\rand not a 32bit sun4[cdem] version\n\r\n\r"
669 .word 0, sun4u_1, 0, 1, 0, 1, 0, sun4u_2, 0
673 .word 0, sun4u_3, 0, 4, 0, 1, 0
675 .word 0, 0, sun4u_4, 0, sun4u_1, 0, 8, 0
679 .word 0, sun4u_5, 0, 3, 0, 1, 0
681 .word 0, 0, sun4u_6, 0, sun4u_6e - sun4u_6 - 1, 0
685 .word 0, sun4u_7, 0, 0, 0, 0
698 mov sun4u_r4 - sun4u_a1, %l3
714 ld [%l1 + (sun4u_r1 - sun4u_a1)], %o1
715 add %l1, (sun4u_a2 - sun4u_a1), %o0
717 st %o1, [%o0 + (sun4u_i2 - sun4u_a2)]
719 ld [%l1 + (sun4u_1 - sun4u_a1)], %o1
720 add %l1, (sun4u_a3 - sun4u_a1), %o0
722 st %o1, [%o0 + (sun4u_i3 - sun4u_a3)]
725 add %l1, (sun4u_a4 - sun4u_a1), %o0
730 call %o0 ! Get us out of here...
731 nop ! Apparently Solaris is better.
733 /* Ok, now we continue in the .data/.text sections */
739 * Fill up the prom vector, note in particular the kind first element,
740 * no joke. I don't need all of them in here as the entire prom vector
741 * gets initialized in c-code so all routines can use it.
747 /* We calculate the following at boot time, window fills/spills and trap entry
748 * code uses these to keep track of the register windows.
759 /* Boot time debugger vector value. We need this later on. */
777 .section ".fixup",#alloc,#execinstr
781 restore %g0, -EFAULT, %o0