arch/sh/kernel/traps_32.c

   1 /*
   2  * 'traps.c' handles hardware traps and faults after we have saved some
   3  * state in 'entry.S'.
   4  *
   5  *  SuperH version: Copyright (C) 1999 Niibe Yutaka
   6  *                  Copyright (C) 2000 Philipp Rumpf
   7  *                  Copyright (C) 2000 David Howells
   8  *                  Copyright (C) 2002 - 2010 Paul Mundt
   9  *
  10  * This file is subject to the terms and conditions of the GNU General Public
  11  * License.  See the file "COPYING" in the main directory of this archive
  12  * for more details.
  13  */
  14 #include <linux/kernel.h>
  15 #include <linux/ptrace.h>
  16 #include <linux/hardirq.h>
  17 #include <linux/init.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/kallsyms.h>
  20 #include <linux/io.h>
  21 #include <linux/bug.h>
  22 #include <linux/debug_locks.h>
  23 #include <linux/kdebug.h>
  24 #include <linux/limits.h>
  25 #include <linux/sysfs.h>
  26 #include <linux/uaccess.h>
  27 #include <linux/perf_event.h>
  28 #include <linux/sched/task_stack.h>
  29
  30 #include <asm/alignment.h>
  31 #include <asm/fpu.h>
  32 #include <asm/kprobes.h>
  33 #include <asm/traps.h>
  34 #include <asm/bl_bit.h>
  35
  36 #ifdef CONFIG_CPU_SH2
  37 # define TRAP_RESERVED_INST     4
  38 # define TRAP_ILLEGAL_SLOT_INST 6
  39 # define TRAP_ADDRESS_ERROR     9
  40 # ifdef CONFIG_CPU_SH2A
  41 #  define TRAP_UBC              12
  42 #  define TRAP_FPU_ERROR        13
  43 #  define TRAP_DIVZERO_ERROR    17
  44 #  define TRAP_DIVOVF_ERROR     18
  45 # endif
  46 #else
  47 #define TRAP_RESERVED_INST      12
  48 #define TRAP_ILLEGAL_SLOT_INST  13
  49 #endif
  50
  51 static inline void sign_extend(unsigned int count, unsigned char *dst)
  52 {
  53 #ifdef __LITTLE_ENDIAN__
  54         if ((count == 1) && dst[0] & 0x80) {
  55                 dst[1] = 0xff;
  56                 dst[2] = 0xff;
  57                 dst[3] = 0xff;
  58         }
  59         if ((count == 2) && dst[1] & 0x80) {
  60                 dst[2] = 0xff;
  61                 dst[3] = 0xff;
  62         }
  63 #else
  64         if ((count == 1) && dst[3] & 0x80) {
  65                 dst[2] = 0xff;
  66                 dst[1] = 0xff;
  67                 dst[0] = 0xff;
  68         }
  69         if ((count == 2) && dst[2] & 0x80) {
  70                 dst[1] = 0xff;
  71                 dst[0] = 0xff;
  72         }
  73 #endif
  74 }
  75
  76 static struct mem_access user_mem_access = {
  77         copy_from_user,
  78         copy_to_user,
  79 };
  80
  81 /*
  82  * handle an instruction that does an unaligned memory access by emulating the
  83  * desired behaviour
  84  * - note that PC _may not_ point to the faulting instruction
  85  *   (if that instruction is in a branch delay slot)
  86  * - return 0 if emulation okay, -EFAULT on existential error
  87  */
  88 static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs,
  89                                 struct mem_access *ma)
  90 {
  91         int ret, index, count;
  92         unsigned long *rm, *rn;
  93         unsigned char *src, *dst;
  94         unsigned char __user *srcu, *dstu;
  95
  96         index = (instruction>>8)&15;    /* 0x0F00 */
  97         rn = &regs->regs[index];
  98
  99         index = (instruction>>4)&15;    /* 0x00F0 */
 100         rm = &regs->regs[index];
 101
 102         count = 1<<(instruction&3);
 103
 104         switch (count) {
 105         case 1: inc_unaligned_byte_access(); break;
 106         case 2: inc_unaligned_word_access(); break;
 107         case 4: inc_unaligned_dword_access(); break;
 108         case 8: inc_unaligned_multi_access(); break;
 109         }
 110
 111         ret = -EFAULT;
 112         switch (instruction>>12) {
 113         case 0: /* mov.[bwl] to/from memory via r0+rn */
 114                 if (instruction & 8) {
 115                         /* from memory */
 116                         srcu = (unsigned char __user *)*rm;
 117                         srcu += regs->regs[0];
 118                         dst = (unsigned char *)rn;
 119                         *(unsigned long *)dst = 0;
 120
 121 #if !defined(__LITTLE_ENDIAN__)
 122                         dst += 4-count;
 123 #endif
 124                         if (ma->from(dst, srcu, count))
 125                                 goto fetch_fault;
 126
 127                         sign_extend(count, dst);
 128                 } else {
 129                         /* to memory */
 130                         src = (unsigned char *)rm;
 131 #if !defined(__LITTLE_ENDIAN__)
 132                         src += 4-count;
 133 #endif
 134                         dstu = (unsigned char __user *)*rn;
 135                         dstu += regs->regs[0];
 136
 137                         if (ma->to(dstu, src, count))
 138                                 goto fetch_fault;
 139                 }
 140                 ret = 0;
 141                 break;
 142
 143         case 1: /* mov.l Rm,@(disp,Rn) */
 144                 src = (unsigned char*) rm;
 145                 dstu = (unsigned char __user *)*rn;
 146                 dstu += (instruction&0x000F)<<2;
 147
 148                 if (ma->to(dstu, src, 4))
 149                         goto fetch_fault;
 150                 ret = 0;
 151                 break;
 152
 153         case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
 154                 if (instruction & 4)
 155                         *rn -= count;
 156                 src = (unsigned char*) rm;
 157                 dstu = (unsigned char __user *)*rn;
 158 #if !defined(__LITTLE_ENDIAN__)
 159                 src += 4-count;
 160 #endif
 161                 if (ma->to(dstu, src, count))
 162                         goto fetch_fault;
 163                 ret = 0;
 164                 break;
 165
 166         case 5: /* mov.l @(disp,Rm),Rn */
 167                 srcu = (unsigned char __user *)*rm;
 168                 srcu += (instruction & 0x000F) << 2;
 169                 dst = (unsigned char *)rn;
 170                 *(unsigned long *)dst = 0;
 171
 172                 if (ma->from(dst, srcu, 4))
 173                         goto fetch_fault;
 174                 ret = 0;
 175                 break;
 176
 177         case 6: /* mov.[bwl] from memory, possibly with post-increment */
 178                 srcu = (unsigned char __user *)*rm;
 179                 if (instruction & 4)
 180                         *rm += count;
 181                 dst = (unsigned char*) rn;
 182                 *(unsigned long*)dst = 0;
 183
 184 #if !defined(__LITTLE_ENDIAN__)
 185                 dst += 4-count;
 186 #endif
 187                 if (ma->from(dst, srcu, count))
 188                         goto fetch_fault;
 189                 sign_extend(count, dst);
 190                 ret = 0;
 191                 break;
 192
 193         case 8:
 194                 switch ((instruction&0xFF00)>>8) {
 195                 case 0x81: /* mov.w R0,@(disp,Rn) */
 196                         src = (unsigned char *) &regs->regs[0];
 197 #if !defined(__LITTLE_ENDIAN__)
 198                         src += 2;
 199 #endif
 200                         dstu = (unsigned char __user *)*rm; /* called Rn in the spec */
 201                         dstu += (instruction & 0x000F) << 1;
 202
 203                         if (ma->to(dstu, src, 2))
 204                                 goto fetch_fault;
 205                         ret = 0;
 206                         break;
 207
 208                 case 0x85: /* mov.w @(disp,Rm),R0 */
 209                         srcu = (unsigned char __user *)*rm;
 210                         srcu += (instruction & 0x000F) << 1;
 211                         dst = (unsigned char *) &regs->regs[0];
 212                         *(unsigned long *)dst = 0;
 213
 214 #if !defined(__LITTLE_ENDIAN__)
 215                         dst += 2;
 216 #endif
 217                         if (ma->from(dst, srcu, 2))
 218                                 goto fetch_fault;
 219                         sign_extend(2, dst);
 220                         ret = 0;
 221                         break;
 222                 }
 223                 break;
 224
 225         case 9: /* mov.w @(disp,PC),Rn */
 226                 srcu = (unsigned char __user *)regs->pc;
 227                 srcu += 4;
 228                 srcu += (instruction & 0x00FF) << 1;
 229                 dst = (unsigned char *)rn;
 230                 *(unsigned long *)dst = 0;
 231
 232 #if !defined(__LITTLE_ENDIAN__)
 233                 dst += 2;
 234 #endif
 235
 236                 if (ma->from(dst, srcu, 2))
 237                         goto fetch_fault;
 238                 sign_extend(2, dst);
 239                 ret = 0;
 240                 break;
 241
 242         case 0xd: /* mov.l @(disp,PC),Rn */
 243                 srcu = (unsigned char __user *)(regs->pc & ~0x3);
 244                 srcu += 4;
 245                 srcu += (instruction & 0x00FF) << 2;
 246                 dst = (unsigned char *)rn;
 247                 *(unsigned long *)dst = 0;
 248
 249                 if (ma->from(dst, srcu, 4))
 250                         goto fetch_fault;
 251                 ret = 0;
 252                 break;
 253         }
 254         return ret;
 255
 256  fetch_fault:
 257         /* Argh. Address not only misaligned but also non-existent.
 258          * Raise an EFAULT and see if it's trapped
 259          */
 260         die_if_no_fixup("Fault in unaligned fixup", regs, 0);
 261         return -EFAULT;
 262 }
 263
 264 /*
 265  * emulate the instruction in the delay slot
 266  * - fetches the instruction from PC+2
 267  */
 268 static inline int handle_delayslot(struct pt_regs *regs,
 269                                    insn_size_t old_instruction,
 270                                    struct mem_access *ma)
 271 {
 272         insn_size_t instruction;
 273         void __user *addr = (void __user *)(regs->pc +
 274                 instruction_size(old_instruction));
 275
 276         if (copy_from_user(&instruction, addr, sizeof(instruction))) {
 277                 /* the instruction-fetch faulted */
 278                 if (user_mode(regs))
 279                         return -EFAULT;
 280
 281                 /* kernel */
 282                 die("delay-slot-insn faulting in handle_unaligned_delayslot",
 283                     regs, 0);
 284         }
 285
 286         return handle_unaligned_ins(instruction, regs, ma);
 287 }
 288
 289 /*
 290  * handle an instruction that does an unaligned memory access
 291  * - have to be careful of branch delay-slot instructions that fault
 292  *  SH3:
 293  *   - if the branch would be taken PC points to the branch
 294  *   - if the branch would not be taken, PC points to delay-slot
 295  *  SH4:
 296  *   - PC always points to delayed branch
 297  * - return 0 if handled, -EFAULT if failed (may not return if in kernel)
 298  */
 299
 300 /* Macros to determine offset from current PC for branch instructions */
 301 /* Explicit type coercion is used to force sign extension where needed */
 302 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
 303 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
 304
 305 int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
 306                             struct mem_access *ma, int expected,
 307                             unsigned long address)
 308 {
 309         u_int rm;
 310         int ret, index;
 311
 312         /*
 313          * XXX: We can't handle mixed 16/32-bit instructions yet
 314          */
 315         if (instruction_size(instruction) != 2)
 316                 return -EINVAL;
 317
 318         index = (instruction>>8)&15;    /* 0x0F00 */
 319         rm = regs->regs[index];
 320
 321         /*
 322          * Log the unexpected fixups, and then pass them on to perf.
 323          *
 324          * We intentionally don't report the expected cases to perf as
 325          * otherwise the trapped I/O case will skew the results too much
 326          * to be useful.
 327          */
 328         if (!expected) {
 329                 unaligned_fixups_notify(current, instruction, regs);
 330                 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1,
 331                               regs, address);
 332         }
 333
 334         ret = -EFAULT;
 335         switch (instruction&0xF000) {
 336         case 0x0000:
 337                 if (instruction==0x000B) {
 338                         /* rts */
 339                         ret = handle_delayslot(regs, instruction, ma);
 340                         if (ret==0)
 341                                 regs->pc = regs->pr;
 342                 }
 343                 else if ((instruction&0x00FF)==0x0023) {
 344                         /* braf @Rm */
 345                         ret = handle_delayslot(regs, instruction, ma);
 346                         if (ret==0)
 347                                 regs->pc += rm + 4;
 348                 }
 349                 else if ((instruction&0x00FF)==0x0003) {
 350                         /* bsrf @Rm */
 351                         ret = handle_delayslot(regs, instruction, ma);
 352                         if (ret==0) {
 353                                 regs->pr = regs->pc + 4;
 354                                 regs->pc += rm + 4;
 355                         }
 356                 }
 357                 else {
 358                         /* mov.[bwl] to/from memory via r0+rn */
 359                         goto simple;
 360                 }
 361                 break;
 362
 363         case 0x1000: /* mov.l Rm,@(disp,Rn) */
 364                 goto simple;
 365
 366         case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
 367                 goto simple;
 368
 369         case 0x4000:
 370                 if ((instruction&0x00FF)==0x002B) {
 371                         /* jmp @Rm */
 372                         ret = handle_delayslot(regs, instruction, ma);
 373                         if (ret==0)
 374                                 regs->pc = rm;
 375                 }
 376                 else if ((instruction&0x00FF)==0x000B) {
 377                         /* jsr @Rm */
 378                         ret = handle_delayslot(regs, instruction, ma);
 379                         if (ret==0) {
 380                                 regs->pr = regs->pc + 4;
 381                                 regs->pc = rm;
 382                         }
 383                 }
 384                 else {
 385                         /* mov.[bwl] to/from memory via r0+rn */
 386                         goto simple;
 387                 }
 388                 break;
 389
 390         case 0x5000: /* mov.l @(disp,Rm),Rn */
 391                 goto simple;
 392
 393         case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
 394                 goto simple;
 395
 396         case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
 397                 switch (instruction&0x0F00) {
 398                 case 0x0100: /* mov.w R0,@(disp,Rm) */
 399                         goto simple;
 400                 case 0x0500: /* mov.w @(disp,Rm),R0 */
 401                         goto simple;
 402                 case 0x0B00: /* bf   lab - no delayslot*/
 403                         ret = 0;
 404                         break;
 405                 case 0x0F00: /* bf/s lab */
 406                         ret = handle_delayslot(regs, instruction, ma);
 407                         if (ret==0) {
 408 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
 409                                 if ((regs->sr & 0x00000001) != 0)
 410                                         regs->pc += 4; /* next after slot */
 411                                 else
 412 #endif
 413                                         regs->pc += SH_PC_8BIT_OFFSET(instruction);
 414                         }
 415                         break;
 416                 case 0x0900: /* bt   lab - no delayslot */
 417                         ret = 0;
 418                         break;
 419                 case 0x0D00: /* bt/s lab */
 420                         ret = handle_delayslot(regs, instruction, ma);
 421                         if (ret==0) {
 422 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
 423                                 if ((regs->sr & 0x00000001) == 0)
 424                                         regs->pc += 4; /* next after slot */
 425                                 else
 426 #endif
 427                                         regs->pc += SH_PC_8BIT_OFFSET(instruction);
 428                         }
 429                         break;
 430                 }
 431                 break;
 432
 433         case 0x9000: /* mov.w @(disp,Rm),Rn */
 434                 goto simple;
 435
 436         case 0xA000: /* bra label */
 437                 ret = handle_delayslot(regs, instruction, ma);
 438                 if (ret==0)
 439                         regs->pc += SH_PC_12BIT_OFFSET(instruction);
 440                 break;
 441
 442         case 0xB000: /* bsr label */
 443                 ret = handle_delayslot(regs, instruction, ma);
 444                 if (ret==0) {
 445                         regs->pr = regs->pc + 4;
 446                         regs->pc += SH_PC_12BIT_OFFSET(instruction);
 447                 }
 448                 break;
 449
 450         case 0xD000: /* mov.l @(disp,Rm),Rn */
 451                 goto simple;
 452         }
 453         return ret;
 454
 455         /* handle non-delay-slot instruction */
 456  simple:
 457         ret = handle_unaligned_ins(instruction, regs, ma);
 458         if (ret==0)
 459                 regs->pc += instruction_size(instruction);
 460         return ret;
 461 }
 462
 463 /*
 464  * Handle various address error exceptions:
 465  *  - instruction address error:
 466  *       misaligned PC
 467  *       PC >= 0x80000000 in user mode
 468  *  - data address error (read and write)
 469  *       misaligned data access
 470  *       access to >= 0x80000000 is user mode
 471  * Unfortuntaly we can't distinguish between instruction address error
 472  * and data address errors caused by read accesses.
 473  */
 474 asmlinkage void do_address_error(struct pt_regs *regs,
 475                                  unsigned long writeaccess,
 476                                  unsigned long address)
 477 {
 478         unsigned long error_code = 0;
 479         mm_segment_t oldfs;
 480         siginfo_t info;
 481         insn_size_t instruction;
 482         int tmp;
 483
 484         /* Intentional ifdef */
 485 #ifdef CONFIG_CPU_HAS_SR_RB
 486         error_code = lookup_exception_vector();
 487 #endif
 488
 489         oldfs = get_fs();
 490
 491         if (user_mode(regs)) {
 492                 int si_code = BUS_ADRERR;
 493                 unsigned int user_action;
 494
 495                 local_irq_enable();
 496                 inc_unaligned_user_access();
 497
 498                 set_fs(USER_DS);
 499                 if (copy_from_user(&instruction, (insn_size_t *)(regs->pc & ~1),
 500                                    sizeof(instruction))) {
 501                         set_fs(oldfs);
 502                         goto uspace_segv;
 503                 }
 504                 set_fs(oldfs);
 505
 506                 /* shout about userspace fixups */
 507                 unaligned_fixups_notify(current, instruction, regs);
 508
 509                 user_action = unaligned_user_action();
 510                 if (user_action & UM_FIXUP)
 511                         goto fixup;
 512                 if (user_action & UM_SIGNAL)
 513                         goto uspace_segv;
 514                 else {
 515                         /* ignore */
 516                         regs->pc += instruction_size(instruction);
 517                         return;
 518                 }
 519
 520 fixup:
 521                 /* bad PC is not something we can fix */
 522                 if (regs->pc & 1) {
 523                         si_code = BUS_ADRALN;
 524                         goto uspace_segv;
 525                 }
 526
 527                 set_fs(USER_DS);
 528                 tmp = handle_unaligned_access(instruction, regs,
 529                                               &user_mem_access, 0,
 530                                               address);
 531                 set_fs(oldfs);
 532
 533                 if (tmp == 0)
 534                         return; /* sorted */
 535 uspace_segv:
 536                 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned "
 537                        "access (PC %lx PR %lx)\n", current->comm, regs->pc,
 538                        regs->pr);
 539
 540                 info.si_signo = SIGBUS;
 541                 info.si_errno = 0;
 542                 info.si_code = si_code;
 543                 info.si_addr = (void __user *)address;
 544                 force_sig_info(SIGBUS, &info, current);
 545         } else {
 546                 inc_unaligned_kernel_access();
 547
 548                 if (regs->pc & 1)
 549                         die("unaligned program counter", regs, error_code);
 550
 551                 set_fs(KERNEL_DS);
 552                 if (copy_from_user(&instruction, (void __user *)(regs->pc),
 553                                    sizeof(instruction))) {
 554                         /* Argh. Fault on the instruction itself.
 555                            This should never happen non-SMP
 556                         */
 557                         set_fs(oldfs);
 558                         die("insn faulting in do_address_error", regs, 0);
 559                 }
 560
 561                 unaligned_fixups_notify(current, instruction, regs);
 562
 563                 handle_unaligned_access(instruction, regs, &user_mem_access,
 564                                         0, address);
 565                 set_fs(oldfs);
 566         }
 567 }
 568
 569 #ifdef CONFIG_SH_DSP
 570 /*
 571  *      SH-DSP support gerg@snapgear.com.
 572  */
 573 int is_dsp_inst(struct pt_regs *regs)
 574 {
 575         unsigned short inst = 0;
 576
 577         /*
 578          * Safe guard if DSP mode is already enabled or we're lacking
 579          * the DSP altogether.
 580          */
 581         if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
 582                 return 0;
 583
 584         get_user(inst, ((unsigned short *) regs->pc));
 585
 586         inst &= 0xf000;
 587
 588         /* Check for any type of DSP or support instruction */
 589         if ((inst == 0xf000) || (inst == 0x4000))
 590                 return 1;
 591
 592         return 0;
 593 }
 594 #else
 595 #define is_dsp_inst(regs)       (0)
 596 #endif /* CONFIG_SH_DSP */
 597
 598 #ifdef CONFIG_CPU_SH2A
 599 asmlinkage void do_divide_error(unsigned long r4)
 600 {
 601         siginfo_t info;
 602
 603         switch (r4) {
 604         case TRAP_DIVZERO_ERROR:
 605                 info.si_code = FPE_INTDIV;
 606                 break;
 607         case TRAP_DIVOVF_ERROR:
 608                 info.si_code = FPE_INTOVF;
 609                 break;
 610         }
 611
 612         force_sig_info(SIGFPE, &info, current);
 613 }
 614 #endif
 615
 616 asmlinkage void do_reserved_inst(void)
 617 {
 618         struct pt_regs *regs = current_pt_regs();
 619         unsigned long error_code;
 620         struct task_struct *tsk = current;
 621
 622 #ifdef CONFIG_SH_FPU_EMU
 623         unsigned short inst = 0;
 624         int err;
 625
 626         get_user(inst, (unsigned short*)regs->pc);
 627
 628         err = do_fpu_inst(inst, regs);
 629         if (!err) {
 630                 regs->pc += instruction_size(inst);
 631                 return;
 632         }
 633         /* not a FPU inst. */
 634 #endif
 635
 636 #ifdef CONFIG_SH_DSP
 637         /* Check if it's a DSP instruction */
 638         if (is_dsp_inst(regs)) {
 639                 /* Enable DSP mode, and restart instruction. */
 640                 regs->sr |= SR_DSP;
 641                 /* Save DSP mode */
 642                 tsk->thread.dsp_status.status |= SR_DSP;
 643                 return;
 644         }
 645 #endif
 646
 647         error_code = lookup_exception_vector();
 648
 649         local_irq_enable();
 650         force_sig(SIGILL, tsk);
 651         die_if_no_fixup("reserved instruction", regs, error_code);
 652 }
 653
 654 #ifdef CONFIG_SH_FPU_EMU
 655 static int emulate_branch(unsigned short inst, struct pt_regs *regs)
 656 {
 657         /*
 658          * bfs: 8fxx: PC+=d*2+4;
 659          * bts: 8dxx: PC+=d*2+4;
 660          * bra: axxx: PC+=D*2+4;
 661          * bsr: bxxx: PC+=D*2+4  after PR=PC+4;
 662          * braf:0x23: PC+=Rn*2+4;
 663          * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
 664          * jmp: 4x2b: PC=Rn;
 665          * jsr: 4x0b: PC=Rn      after PR=PC+4;
 666          * rts: 000b: PC=PR;
 667          */
 668         if (((inst & 0xf000) == 0xb000)  ||     /* bsr */
 669             ((inst & 0xf0ff) == 0x0003)  ||     /* bsrf */
 670             ((inst & 0xf0ff) == 0x400b))        /* jsr */
 671                 regs->pr = regs->pc + 4;
 672
 673         if ((inst & 0xfd00) == 0x8d00) {        /* bfs, bts */
 674                 regs->pc += SH_PC_8BIT_OFFSET(inst);
 675                 return 0;
 676         }
 677
 678         if ((inst & 0xe000) == 0xa000) {        /* bra, bsr */
 679                 regs->pc += SH_PC_12BIT_OFFSET(inst);
 680                 return 0;
 681         }
 682
 683         if ((inst & 0xf0df) == 0x0003) {        /* braf, bsrf */
 684                 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
 685                 return 0;
 686         }
 687
 688         if ((inst & 0xf0df) == 0x400b) {        /* jmp, jsr */
 689                 regs->pc = regs->regs[(inst & 0x0f00) >> 8];
 690                 return 0;
 691         }
 692
 693         if ((inst & 0xffff) == 0x000b) {        /* rts */
 694                 regs->pc = regs->pr;
 695                 return 0;
 696         }
 697
 698         return 1;
 699 }
 700 #endif
 701
 702 asmlinkage void do_illegal_slot_inst(void)
 703 {
 704         struct pt_regs *regs = current_pt_regs();
 705         unsigned long inst;
 706         struct task_struct *tsk = current;
 707
 708         if (kprobe_handle_illslot(regs->pc) == 0)
 709                 return;
 710
 711 #ifdef CONFIG_SH_FPU_EMU
 712         get_user(inst, (unsigned short *)regs->pc + 1);
 713         if (!do_fpu_inst(inst, regs)) {
 714                 get_user(inst, (unsigned short *)regs->pc);
 715                 if (!emulate_branch(inst, regs))
 716                         return;
 717                 /* fault in branch.*/
 718         }
 719         /* not a FPU inst. */
 720 #endif
 721
 722         inst = lookup_exception_vector();
 723
 724         local_irq_enable();
 725         force_sig(SIGILL, tsk);
 726         die_if_no_fixup("illegal slot instruction", regs, inst);
 727 }
 728
 729 asmlinkage void do_exception_error(void)
 730 {
 731         long ex;
 732
 733         ex = lookup_exception_vector();
 734         die_if_kernel("exception", current_pt_regs(), ex);
 735 }
 736
 737 void per_cpu_trap_init(void)
 738 {
 739         extern void *vbr_base;
 740
 741         /* NOTE: The VBR value should be at P1
 742            (or P2, virtural "fixed" address space).
 743            It's definitely should not in physical address.  */
 744
 745         asm volatile("ldc       %0, vbr"
 746                      : /* no output */
 747                      : "r" (&vbr_base)
 748                      : "memory");
 749
 750         /* disable exception blocking now when the vbr has been setup */
 751         clear_bl_bit();
 752 }
 753
 754 void *set_exception_table_vec(unsigned int vec, void *handler)
 755 {
 756         extern void *exception_handling_table[];
 757         void *old_handler;
 758
 759         old_handler = exception_handling_table[vec];
 760         exception_handling_table[vec] = handler;
 761         return old_handler;
 762 }
 763
 764 void __init trap_init(void)
 765 {
 766         set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
 767         set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
 768
 769 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
 770     defined(CONFIG_SH_FPU_EMU)
 771         /*
 772          * For SH-4 lacking an FPU, treat floating point instructions as
 773          * reserved. They'll be handled in the math-emu case, or faulted on
 774          * otherwise.
 775          */
 776         set_exception_table_evt(0x800, do_reserved_inst);
 777         set_exception_table_evt(0x820, do_illegal_slot_inst);
 778 #elif defined(CONFIG_SH_FPU)
 779         set_exception_table_evt(0x800, fpu_state_restore_trap_handler);
 780         set_exception_table_evt(0x820, fpu_state_restore_trap_handler);
 781 #endif
 782
 783 #ifdef CONFIG_CPU_SH2
 784         set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler);
 785 #endif
 786 #ifdef CONFIG_CPU_SH2A
 787         set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error);
 788         set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error);
 789 #ifdef CONFIG_SH_FPU
 790         set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler);
 791 #endif
 792 #endif
 793
 794 #ifdef TRAP_UBC
 795         set_exception_table_vec(TRAP_UBC, breakpoint_trap_handler);
 796 #endif
 797 }