2 * arch/sh/kernel/timers/timer-mtu2.c - MTU2 Timer Support
4 * Copyright (C) 2005 Paul Mundt
6 * Based off of arch/sh/kernel/timers/timer-tmu.c
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
12 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/interrupt.h>
15 #include <linux/spinlock.h>
16 #include <linux/seqlock.h>
17 #include <asm/timer.h>
20 #include <asm/clock.h>
23 * We use channel 1 for our lowly system timer. Channel 2 would be the other
24 * likely candidate, but we leave it alone as it has higher divisors that
25 * would be of more use to other more interesting applications.
27 * TODO: Presently we only implement a 16-bit single-channel system timer.
28 * However, we can implement channel cascade if we go the overflow route and
29 * get away with using 2 MTU2 channels as a 32-bit timer.
32 static DEFINE_SPINLOCK(mtu2_lock);
34 #define MTU2_TSTR 0xfffe4280
35 #define MTU2_TCR_1 0xfffe4380
36 #define MTU2_TMDR_1 0xfffe4381
37 #define MTU2_TIOR_1 0xfffe4382
38 #define MTU2_TIER_1 0xfffe4384
39 #define MTU2_TSR_1 0xfffe4385
40 #define MTU2_TCNT_1 0xfffe4386 /* 16-bit counter */
41 #define MTU2_TGRA_1 0xfffe438a
43 #define STBCR3 0xfffe0408
45 #define MTU2_TSTR_CST1 (1 << 1) /* Counter Start 1 */
47 #define MTU2_TSR_TGFA (1 << 0) /* GRA compare match */
49 #define MTU2_TIER_TGIEA (1 << 0) /* GRA compare match interrupt enable */
51 #define MTU2_TCR_INIT 0x22
53 #define MTU2_TCR_CALIB 0x00
55 static unsigned long mtu2_timer_get_offset(void)
60 static int count_p = 0x7fff; /* for the first call after boot */
61 static unsigned long jiffies_p = 0;
64 * cache volatile jiffies temporarily; we have IRQs turned off.
66 unsigned long jiffies_t;
68 spin_lock_irqsave(&mtu2_lock, flags);
69 /* timer count may underflow right here */
70 count = ctrl_inw(MTU2_TCNT_1); /* read the latched count */
75 * avoiding timer inconsistencies (they are rare, but they happen)...
76 * there is one kind of problem that must be avoided here:
77 * 1. the timer counter underflows
80 if (jiffies_t == jiffies_p) {
81 if (count > count_p) {
82 if (ctrl_inb(MTU2_TSR_1) & MTU2_TSR_TGFA) {
85 printk("%s (): hardware timer problem?\n",
90 jiffies_p = jiffies_t;
93 spin_unlock_irqrestore(&mtu2_lock, flags);
95 count = ((LATCH-1) - count) * TICK_SIZE;
96 count = (count + LATCH/2) / LATCH;
101 static irqreturn_t mtu2_timer_interrupt(int irq, void *dev_id)
103 unsigned long timer_status;
106 timer_status = ctrl_inb(MTU2_TSR_1);
107 timer_status &= ~MTU2_TSR_TGFA;
108 ctrl_outb(timer_status, MTU2_TSR_1);
111 write_seqlock(&xtime_lock);
113 write_sequnlock(&xtime_lock);
118 static struct irqaction mtu2_irq = {
120 .handler = mtu2_timer_interrupt,
121 .flags = IRQF_DISABLED,
122 .mask = CPU_MASK_NONE,
125 static unsigned int divisors[] = { 1, 4, 16, 64, 1, 1, 256 };
127 static void mtu2_clk_init(struct clk *clk)
129 u8 idx = MTU2_TCR_INIT & 0x7;
131 clk->rate = clk->parent->rate / divisors[idx];
132 /* Start TCNT counting */
133 ctrl_outb(ctrl_inb(MTU2_TSTR) | MTU2_TSTR_CST1, MTU2_TSTR);
137 static void mtu2_clk_recalc(struct clk *clk)
139 u8 idx = ctrl_inb(MTU2_TCR_1) & 0x7;
140 clk->rate = clk->parent->rate / divisors[idx];
143 static struct clk_ops mtu2_clk_ops = {
144 .init = mtu2_clk_init,
145 .recalc = mtu2_clk_recalc,
148 static struct clk mtu2_clk1 = {
150 .ops = &mtu2_clk_ops,
153 static int mtu2_timer_start(void)
155 ctrl_outb(ctrl_inb(MTU2_TSTR) | MTU2_TSTR_CST1, MTU2_TSTR);
159 static int mtu2_timer_stop(void)
161 ctrl_outb(ctrl_inb(MTU2_TSTR) & ~MTU2_TSTR_CST1, MTU2_TSTR);
165 static int mtu2_timer_init(void)
168 unsigned long interval;
170 setup_irq(TIMER_IRQ, &mtu2_irq);
172 mtu2_clk1.parent = clk_get("module_clk");
174 ctrl_outb(ctrl_inb(STBCR3) & (~0x20), STBCR3);
176 /* Normal operation */
177 ctrl_outb(0, MTU2_TMDR_1);
178 ctrl_outb(MTU2_TCR_INIT, MTU2_TCR_1);
179 ctrl_outb(0x01, MTU2_TIOR_1);
181 /* Enable underflow interrupt */
182 ctrl_outb(ctrl_inb(MTU2_TIER_1) | MTU2_TIER_TGIEA, MTU2_TIER_1);
184 interval = CONFIG_SH_PCLK_FREQ / 16 / HZ;
185 printk(KERN_INFO "Interval = %ld\n", interval);
187 ctrl_outw(interval, MTU2_TGRA_1);
188 ctrl_outw(0, MTU2_TCNT_1);
190 clk_register(&mtu2_clk1);
191 clk_enable(&mtu2_clk1);
196 struct sys_timer_ops mtu2_timer_ops = {
197 .init = mtu2_timer_init,
198 .start = mtu2_timer_start,
199 .stop = mtu2_timer_stop,
200 #ifndef CONFIG_GENERIC_TIME
201 .get_offset = mtu2_timer_get_offset,
205 struct sys_timer mtu2_timer = {
207 .ops = &mtu2_timer_ops,