4 * Copyright (C) 2006 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
14 #include <linux/serial_sci.h>
15 #include <linux/sh_timer.h>
17 #include <asm/dmaengine.h>
19 #include <cpu/dma-register.h>
21 static struct plat_sci_port scif0_platform_data = {
22 .mapbase = 0xffe00000,
23 .flags = UPF_BOOT_AUTOCONF,
25 .irqs = { 40, 40, 40, 40 },
28 static struct platform_device scif0_device = {
32 .platform_data = &scif0_platform_data,
36 static struct plat_sci_port scif1_platform_data = {
37 .mapbase = 0xffe10000,
38 .flags = UPF_BOOT_AUTOCONF,
40 .irqs = { 76, 76, 76, 76 },
43 static struct platform_device scif1_device = {
47 .platform_data = &scif1_platform_data,
51 static struct sh_timer_config tmu0_platform_data = {
53 .channel_offset = 0x04,
55 .clk = "peripheral_clk",
56 .clockevent_rating = 200,
59 static struct resource tmu0_resources[] = {
64 .flags = IORESOURCE_MEM,
68 .flags = IORESOURCE_IRQ,
72 static struct platform_device tmu0_device = {
76 .platform_data = &tmu0_platform_data,
78 .resource = tmu0_resources,
79 .num_resources = ARRAY_SIZE(tmu0_resources),
82 static struct sh_timer_config tmu1_platform_data = {
84 .channel_offset = 0x10,
86 .clk = "peripheral_clk",
87 .clocksource_rating = 200,
90 static struct resource tmu1_resources[] = {
95 .flags = IORESOURCE_MEM,
99 .flags = IORESOURCE_IRQ,
103 static struct platform_device tmu1_device = {
107 .platform_data = &tmu1_platform_data,
109 .resource = tmu1_resources,
110 .num_resources = ARRAY_SIZE(tmu1_resources),
113 static struct sh_timer_config tmu2_platform_data = {
115 .channel_offset = 0x1c,
117 .clk = "peripheral_clk",
120 static struct resource tmu2_resources[] = {
125 .flags = IORESOURCE_MEM,
129 .flags = IORESOURCE_IRQ,
133 static struct platform_device tmu2_device = {
137 .platform_data = &tmu2_platform_data,
139 .resource = tmu2_resources,
140 .num_resources = ARRAY_SIZE(tmu2_resources),
143 static struct sh_timer_config tmu3_platform_data = {
145 .channel_offset = 0x04,
147 .clk = "peripheral_clk",
150 static struct resource tmu3_resources[] = {
155 .flags = IORESOURCE_MEM,
159 .flags = IORESOURCE_IRQ,
163 static struct platform_device tmu3_device = {
167 .platform_data = &tmu3_platform_data,
169 .resource = tmu3_resources,
170 .num_resources = ARRAY_SIZE(tmu3_resources),
173 static struct sh_timer_config tmu4_platform_data = {
175 .channel_offset = 0x10,
177 .clk = "peripheral_clk",
180 static struct resource tmu4_resources[] = {
185 .flags = IORESOURCE_MEM,
189 .flags = IORESOURCE_IRQ,
193 static struct platform_device tmu4_device = {
197 .platform_data = &tmu4_platform_data,
199 .resource = tmu4_resources,
200 .num_resources = ARRAY_SIZE(tmu4_resources),
203 static struct sh_timer_config tmu5_platform_data = {
205 .channel_offset = 0x1c,
207 .clk = "peripheral_clk",
210 static struct resource tmu5_resources[] = {
215 .flags = IORESOURCE_MEM,
219 .flags = IORESOURCE_IRQ,
223 static struct platform_device tmu5_device = {
227 .platform_data = &tmu5_platform_data,
229 .resource = tmu5_resources,
230 .num_resources = ARRAY_SIZE(tmu5_resources),
233 static struct resource rtc_resources[] = {
236 .end = 0xffe80000 + 0x58 - 1,
237 .flags = IORESOURCE_IO,
240 /* Shared Period/Carry/Alarm IRQ */
242 .flags = IORESOURCE_IRQ,
246 static struct platform_device rtc_device = {
249 .num_resources = ARRAY_SIZE(rtc_resources),
250 .resource = rtc_resources,
254 static struct sh_dmae_channel sh7780_dmae0_channels[] = {
282 static struct sh_dmae_channel sh7780_dmae1_channels[] = {
298 static unsigned int ts_shift[] = TS_SHIFT;
300 static struct sh_dmae_pdata dma0_platform_data = {
301 .channel = sh7780_dmae0_channels,
302 .channel_num = ARRAY_SIZE(sh7780_dmae0_channels),
303 .ts_low_shift = CHCR_TS_LOW_SHIFT,
304 .ts_low_mask = CHCR_TS_LOW_MASK,
305 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
306 .ts_high_mask = CHCR_TS_HIGH_MASK,
307 .ts_shift = ts_shift,
308 .ts_shift_num = ARRAY_SIZE(ts_shift),
309 .dmaor_init = DMAOR_INIT,
312 static struct sh_dmae_pdata dma1_platform_data = {
313 .channel = sh7780_dmae1_channels,
314 .channel_num = ARRAY_SIZE(sh7780_dmae1_channels),
315 .ts_low_shift = CHCR_TS_LOW_SHIFT,
316 .ts_low_mask = CHCR_TS_LOW_MASK,
317 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
318 .ts_high_mask = CHCR_TS_HIGH_MASK,
319 .ts_shift = ts_shift,
320 .ts_shift_num = ARRAY_SIZE(ts_shift),
321 .dmaor_init = DMAOR_INIT,
324 static struct resource sh7780_dmae0_resources[] = {
326 /* Channel registers and DMAOR */
329 .flags = IORESOURCE_MEM,
335 .flags = IORESOURCE_MEM,
338 /* Real DMA error IRQ is 38, and channel IRQs are 34-37, 44-45 */
341 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
345 static struct resource sh7780_dmae1_resources[] = {
347 /* Channel registers and DMAOR */
350 .flags = IORESOURCE_MEM,
352 /* DMAC1 has no DMARS */
354 /* Real DMA error IRQ is 38, and channel IRQs are 46-47, 92-95 */
357 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
361 static struct platform_device dma0_device = {
362 .name = "sh-dma-engine",
364 .resource = sh7780_dmae0_resources,
365 .num_resources = ARRAY_SIZE(sh7780_dmae0_resources),
367 .platform_data = &dma0_platform_data,
371 static struct platform_device dma1_device = {
372 .name = "sh-dma-engine",
374 .resource = sh7780_dmae1_resources,
375 .num_resources = ARRAY_SIZE(sh7780_dmae1_resources),
377 .platform_data = &dma1_platform_data,
381 static struct platform_device *sh7780_devices[] __initdata = {
395 static int __init sh7780_devices_setup(void)
397 return platform_add_devices(sh7780_devices,
398 ARRAY_SIZE(sh7780_devices));
400 arch_initcall(sh7780_devices_setup);
401 static struct platform_device *sh7780_early_devices[] __initdata = {
412 void __init plat_early_device_setup(void)
414 early_platform_add_devices(sh7780_early_devices,
415 ARRAY_SIZE(sh7780_early_devices));
421 /* interrupt sources */
423 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
424 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
425 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
426 IRL_HHLL, IRL_HHLH, IRL_HHHL,
428 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
429 RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
430 HUDI, DMAC0, SCIF0, DMAC1, CMT, HAC,
431 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
432 SCIF1, SIOF, HSPI, MMCIF, TMU3, TMU4, TMU5, SSI, FLCTL, GPIO,
434 /* interrupt groups */
439 static struct intc_vect vectors[] __initdata = {
440 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
441 INTC_VECT(RTC, 0x4c0),
442 INTC_VECT(WDT, 0x560),
443 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
444 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
445 INTC_VECT(HUDI, 0x600),
446 INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660),
447 INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0),
448 INTC_VECT(DMAC0, 0x6c0),
449 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
450 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
451 INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0),
452 INTC_VECT(DMAC1, 0x7c0), INTC_VECT(DMAC1, 0x7e0),
453 INTC_VECT(CMT, 0x900), INTC_VECT(HAC, 0x980),
454 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
455 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
456 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
457 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
458 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
459 INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0),
460 INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0),
461 INTC_VECT(SIOF, 0xc00), INTC_VECT(HSPI, 0xc80),
462 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
463 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
464 INTC_VECT(DMAC1, 0xd80), INTC_VECT(DMAC1, 0xda0),
465 INTC_VECT(DMAC1, 0xdc0), INTC_VECT(DMAC1, 0xde0),
466 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
467 INTC_VECT(TMU5, 0xe40),
468 INTC_VECT(SSI, 0xe80),
469 INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
470 INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
471 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
472 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
475 static struct intc_group groups[] __initdata = {
476 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
477 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
480 static struct intc_mask_reg mask_registers[] __initdata = {
481 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
482 { 0, 0, 0, 0, 0, 0, GPIO, FLCTL,
483 SSI, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
484 PCIINTA, PCISERR, HAC, CMT, 0, 0, DMAC1, DMAC0,
485 HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
488 static struct intc_prio_reg prio_registers[] __initdata = {
489 { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
490 TMU2, TMU2_TICPI } },
491 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
492 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
493 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC0, DMAC1 } },
494 { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC,
495 PCISERR, PCIINTA, } },
496 { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
498 { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF, HSPI, MMCIF, SSI } },
499 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { FLCTL, GPIO } },
502 static DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups,
503 mask_registers, prio_registers, NULL);
505 /* Support for external interrupt pins in IRQ mode */
507 static struct intc_vect irq_vectors[] __initdata = {
508 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
509 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
510 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
511 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
514 static struct intc_mask_reg irq_mask_registers[] __initdata = {
515 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
516 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
519 static struct intc_prio_reg irq_prio_registers[] __initdata = {
520 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
521 IRQ4, IRQ5, IRQ6, IRQ7 } },
524 static struct intc_sense_reg irq_sense_registers[] __initdata = {
525 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
526 IRQ4, IRQ5, IRQ6, IRQ7 } },
529 static struct intc_mask_reg irq_ack_registers[] __initdata = {
530 { 0xffd00024, 0, 32, /* INTREQ */
531 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
534 static DECLARE_INTC_DESC_ACK(intc_irq_desc, "sh7780-irq", irq_vectors,
535 NULL, irq_mask_registers, irq_prio_registers,
536 irq_sense_registers, irq_ack_registers);
538 /* External interrupt pins in IRL mode */
540 static struct intc_vect irl_vectors[] __initdata = {
541 INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
542 INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
543 INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
544 INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
545 INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
546 INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
547 INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
548 INTC_VECT(IRL_HHHL, 0x3c0),
551 static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
552 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
553 { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
554 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
555 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
556 IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
559 static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
560 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
561 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
562 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
563 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
564 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
565 IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
568 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
569 NULL, irl7654_mask_registers, NULL, NULL);
571 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
572 NULL, irl3210_mask_registers, NULL, NULL);
574 #define INTC_ICR0 0xffd00000
575 #define INTC_INTMSK0 0xffd00044
576 #define INTC_INTMSK1 0xffd00048
577 #define INTC_INTMSK2 0xffd40080
578 #define INTC_INTMSKCLR1 0xffd00068
579 #define INTC_INTMSKCLR2 0xffd40084
581 void __init plat_irq_setup(void)
584 __raw_writel(0xff000000, INTC_INTMSK0);
586 /* disable IRL3-0 + IRL7-4 */
587 __raw_writel(0xc0000000, INTC_INTMSK1);
588 __raw_writel(0xfffefffe, INTC_INTMSK2);
590 /* select IRL mode for IRL3-0 + IRL7-4 */
591 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
593 /* disable holding function, ie enable "SH-4 Mode" */
594 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
596 register_intc_controller(&intc_desc);
599 void __init plat_irq_setup_pins(int mode)
603 /* select IRQ mode for IRL3-0 + IRL7-4 */
604 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
605 register_intc_controller(&intc_irq_desc);
607 case IRQ_MODE_IRL7654:
608 /* enable IRL7-4 but don't provide any masking */
609 __raw_writel(0x40000000, INTC_INTMSKCLR1);
610 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
612 case IRQ_MODE_IRL3210:
613 /* enable IRL0-3 but don't provide any masking */
614 __raw_writel(0x80000000, INTC_INTMSKCLR1);
615 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
617 case IRQ_MODE_IRL7654_MASK:
618 /* enable IRL7-4 and mask using cpu intc controller */
619 __raw_writel(0x40000000, INTC_INTMSKCLR1);
620 register_intc_controller(&intc_irl7654_desc);
622 case IRQ_MODE_IRL3210_MASK:
623 /* enable IRL0-3 and mask using cpu intc controller */
624 __raw_writel(0x80000000, INTC_INTMSKCLR1);
625 register_intc_controller(&intc_irl3210_desc);