arch/sh/kernel/cpu/sh4a/setup-sh7724.c

   1 /*
   2  * SH7724 Setup
   3  *
   4  * Copyright (C) 2009 Renesas Solutions Corp.
   5  *
   6  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
   7  *
   8  * Based on SH7723 Setup
   9  * Copyright (C) 2008  Paul Mundt
  10  *
  11  * This file is subject to the terms and conditions of the GNU General Public
  12  * License.  See the file "COPYING" in the main directory of this archive
  13  * for more details.
  14  */
  15 #include <linux/platform_device.h>
  16 #include <linux/init.h>
  17 #include <linux/serial.h>
  18 #include <linux/mm.h>
  19 #include <linux/serial_sci.h>
  20 #include <linux/uio_driver.h>
  21 #include <linux/sh_dma.h>
  22 #include <linux/sh_timer.h>
  23 #include <linux/sh_intc.h>
  24 #include <linux/io.h>
  25 #include <linux/notifier.h>
  26
  27 #include <asm/suspend.h>
  28 #include <asm/clock.h>
  29 #include <asm/mmzone.h>
  30
  31 #include <cpu/dma-register.h>
  32 #include <cpu/sh7724.h>
  33
  34 /* DMA */
  35 static const struct sh_dmae_slave_config sh7724_dmae_slaves[] = {
  36         {
  37                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
  38                 .addr           = 0xffe0000c,
  39                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
  40                 .mid_rid        = 0x21,
  41         }, {
  42                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
  43                 .addr           = 0xffe00014,
  44                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
  45                 .mid_rid        = 0x22,
  46         }, {
  47                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
  48                 .addr           = 0xffe1000c,
  49                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
  50                 .mid_rid        = 0x25,
  51         }, {
  52                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
  53                 .addr           = 0xffe10014,
  54                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
  55                 .mid_rid        = 0x26,
  56         }, {
  57                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
  58                 .addr           = 0xffe2000c,
  59                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
  60                 .mid_rid        = 0x29,
  61         }, {
  62                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
  63                 .addr           = 0xffe20014,
  64                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
  65                 .mid_rid        = 0x2a,
  66         }, {
  67                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
  68                 .addr           = 0xa4e30020,
  69                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
  70                 .mid_rid        = 0x2d,
  71         }, {
  72                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
  73                 .addr           = 0xa4e30024,
  74                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
  75                 .mid_rid        = 0x2e,
  76         }, {
  77                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
  78                 .addr           = 0xa4e40020,
  79                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
  80                 .mid_rid        = 0x31,
  81         }, {
  82                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
  83                 .addr           = 0xa4e40024,
  84                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
  85                 .mid_rid        = 0x32,
  86         }, {
  87                 .slave_id       = SHDMA_SLAVE_SCIF5_TX,
  88                 .addr           = 0xa4e50020,
  89                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
  90                 .mid_rid        = 0x35,
  91         }, {
  92                 .slave_id       = SHDMA_SLAVE_SCIF5_RX,
  93                 .addr           = 0xa4e50024,
  94                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
  95                 .mid_rid        = 0x36,
  96         }, {
  97                 .slave_id       = SHDMA_SLAVE_USB0D0_TX,
  98                 .addr           = 0xA4D80100,
  99                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
 100                 .mid_rid        = 0x73,
 101         }, {
 102                 .slave_id       = SHDMA_SLAVE_USB0D0_RX,
 103                 .addr           = 0xA4D80100,
 104                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
 105                 .mid_rid        = 0x73,
 106         }, {
 107                 .slave_id       = SHDMA_SLAVE_USB0D1_TX,
 108                 .addr           = 0xA4D80120,
 109                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
 110                 .mid_rid        = 0x77,
 111         }, {
 112                 .slave_id       = SHDMA_SLAVE_USB0D1_RX,
 113                 .addr           = 0xA4D80120,
 114                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
 115                 .mid_rid        = 0x77,
 116         }, {
 117                 .slave_id       = SHDMA_SLAVE_USB1D0_TX,
 118                 .addr           = 0xA4D90100,
 119                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
 120                 .mid_rid        = 0xab,
 121         }, {
 122                 .slave_id       = SHDMA_SLAVE_USB1D0_RX,
 123                 .addr           = 0xA4D90100,
 124                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
 125                 .mid_rid        = 0xab,
 126         }, {
 127                 .slave_id       = SHDMA_SLAVE_USB1D1_TX,
 128                 .addr           = 0xA4D90120,
 129                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
 130                 .mid_rid        = 0xaf,
 131         }, {
 132                 .slave_id       = SHDMA_SLAVE_USB1D1_RX,
 133                 .addr           = 0xA4D90120,
 134                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
 135                 .mid_rid        = 0xaf,
 136         }, {
 137                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 138                 .addr           = 0x04ce0030,
 139                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 140                 .mid_rid        = 0xc1,
 141         }, {
 142                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 143                 .addr           = 0x04ce0030,
 144                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 145                 .mid_rid        = 0xc2,
 146         }, {
 147                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 148                 .addr           = 0x04cf0030,
 149                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 150                 .mid_rid        = 0xc9,
 151         }, {
 152                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 153                 .addr           = 0x04cf0030,
 154                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 155                 .mid_rid        = 0xca,
 156         },
 157 };
 158
 159 static const struct sh_dmae_channel sh7724_dmae_channels[] = {
 160         {
 161                 .offset = 0,
 162                 .dmars = 0,
 163                 .dmars_bit = 0,
 164         }, {
 165                 .offset = 0x10,
 166                 .dmars = 0,
 167                 .dmars_bit = 8,
 168         }, {
 169                 .offset = 0x20,
 170                 .dmars = 4,
 171                 .dmars_bit = 0,
 172         }, {
 173                 .offset = 0x30,
 174                 .dmars = 4,
 175                 .dmars_bit = 8,
 176         }, {
 177                 .offset = 0x50,
 178                 .dmars = 8,
 179                 .dmars_bit = 0,
 180         }, {
 181                 .offset = 0x60,
 182                 .dmars = 8,
 183                 .dmars_bit = 8,
 184         }
 185 };
 186
 187 static const unsigned int ts_shift[] = TS_SHIFT;
 188
 189 static struct sh_dmae_pdata dma_platform_data = {
 190         .slave          = sh7724_dmae_slaves,
 191         .slave_num      = ARRAY_SIZE(sh7724_dmae_slaves),
 192         .channel        = sh7724_dmae_channels,
 193         .channel_num    = ARRAY_SIZE(sh7724_dmae_channels),
 194         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
 195         .ts_low_mask    = CHCR_TS_LOW_MASK,
 196         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
 197         .ts_high_mask   = CHCR_TS_HIGH_MASK,
 198         .ts_shift       = ts_shift,
 199         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 200         .dmaor_init     = DMAOR_INIT,
 201 };
 202
 203 /* Resource order important! */
 204 static struct resource sh7724_dmae0_resources[] = {
 205         {
 206                 /* Channel registers and DMAOR */
 207                 .start  = 0xfe008020,
 208                 .end    = 0xfe00808f,
 209                 .flags  = IORESOURCE_MEM,
 210         },
 211         {
 212                 /* DMARSx */
 213                 .start  = 0xfe009000,
 214                 .end    = 0xfe00900b,
 215                 .flags  = IORESOURCE_MEM,
 216         },
 217         {
 218                 .name   = "error_irq",
 219                 .start  = evt2irq(0xbc0),
 220                 .end    = evt2irq(0xbc0),
 221                 .flags  = IORESOURCE_IRQ,
 222         },
 223         {
 224                 /* IRQ for channels 0-3 */
 225                 .start  = evt2irq(0x800),
 226                 .end    = evt2irq(0x860),
 227                 .flags  = IORESOURCE_IRQ,
 228         },
 229         {
 230                 /* IRQ for channels 4-5 */
 231                 .start  = evt2irq(0xb80),
 232                 .end    = evt2irq(0xba0),
 233                 .flags  = IORESOURCE_IRQ,
 234         },
 235 };
 236
 237 /* Resource order important! */
 238 static struct resource sh7724_dmae1_resources[] = {
 239         {
 240                 /* Channel registers and DMAOR */
 241                 .start  = 0xfdc08020,
 242                 .end    = 0xfdc0808f,
 243                 .flags  = IORESOURCE_MEM,
 244         },
 245         {
 246                 /* DMARSx */
 247                 .start  = 0xfdc09000,
 248                 .end    = 0xfdc0900b,
 249                 .flags  = IORESOURCE_MEM,
 250         },
 251         {
 252                 .name   = "error_irq",
 253                 .start  = evt2irq(0xb40),
 254                 .end    = evt2irq(0xb40),
 255                 .flags  = IORESOURCE_IRQ,
 256         },
 257         {
 258                 /* IRQ for channels 0-3 */
 259                 .start  = evt2irq(0x700),
 260                 .end    = evt2irq(0x760),
 261                 .flags  = IORESOURCE_IRQ,
 262         },
 263         {
 264                 /* IRQ for channels 4-5 */
 265                 .start  = evt2irq(0xb00),
 266                 .end    = evt2irq(0xb20),
 267                 .flags  = IORESOURCE_IRQ,
 268         },
 269 };
 270
 271 static struct platform_device dma0_device = {
 272         .name           = "sh-dma-engine",
 273         .id             = 0,
 274         .resource       = sh7724_dmae0_resources,
 275         .num_resources  = ARRAY_SIZE(sh7724_dmae0_resources),
 276         .dev            = {
 277                 .platform_data  = &dma_platform_data,
 278         },
 279 };
 280
 281 static struct platform_device dma1_device = {
 282         .name           = "sh-dma-engine",
 283         .id             = 1,
 284         .resource       = sh7724_dmae1_resources,
 285         .num_resources  = ARRAY_SIZE(sh7724_dmae1_resources),
 286         .dev            = {
 287                 .platform_data  = &dma_platform_data,
 288         },
 289 };
 290
 291 /* Serial */
 292 static struct plat_sci_port scif0_platform_data = {
 293         .port_reg       = SCIx_NOT_SUPPORTED,
 294         .flags          = UPF_BOOT_AUTOCONF,
 295         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 296         .type           = PORT_SCIF,
 297         .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
 298 };
 299
 300 static struct resource scif0_resources[] = {
 301         DEFINE_RES_MEM(0xffe00000, 0x100),
 302         DEFINE_RES_IRQ(evt2irq(0xc00)),
 303 };
 304
 305 static struct platform_device scif0_device = {
 306         .name           = "sh-sci",
 307         .id             = 0,
 308         .resource       = scif0_resources,
 309         .num_resources  = ARRAY_SIZE(scif0_resources),
 310         .dev            = {
 311                 .platform_data  = &scif0_platform_data,
 312         },
 313 };
 314
 315 static struct plat_sci_port scif1_platform_data = {
 316         .port_reg       = SCIx_NOT_SUPPORTED,
 317         .flags          = UPF_BOOT_AUTOCONF,
 318         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 319         .type           = PORT_SCIF,
 320         .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
 321 };
 322
 323 static struct resource scif1_resources[] = {
 324         DEFINE_RES_MEM(0xffe10000, 0x100),
 325         DEFINE_RES_IRQ(evt2irq(0xc20)),
 326 };
 327
 328 static struct platform_device scif1_device = {
 329         .name           = "sh-sci",
 330         .id             = 1,
 331         .resource       = scif1_resources,
 332         .num_resources  = ARRAY_SIZE(scif1_resources),
 333         .dev            = {
 334                 .platform_data  = &scif1_platform_data,
 335         },
 336 };
 337
 338 static struct plat_sci_port scif2_platform_data = {
 339         .port_reg       = SCIx_NOT_SUPPORTED,
 340         .flags          = UPF_BOOT_AUTOCONF,
 341         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 342         .type           = PORT_SCIF,
 343         .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
 344 };
 345
 346 static struct resource scif2_resources[] = {
 347         DEFINE_RES_MEM(0xffe20000, 0x100),
 348         DEFINE_RES_IRQ(evt2irq(0xc40)),
 349 };
 350
 351 static struct platform_device scif2_device = {
 352         .name           = "sh-sci",
 353         .id             = 2,
 354         .resource       = scif2_resources,
 355         .num_resources  = ARRAY_SIZE(scif2_resources),
 356         .dev            = {
 357                 .platform_data  = &scif2_platform_data,
 358         },
 359 };
 360
 361 static struct plat_sci_port scif3_platform_data = {
 362         .port_reg       = SCIx_NOT_SUPPORTED,
 363         .flags          = UPF_BOOT_AUTOCONF,
 364         .scscr          = SCSCR_RE | SCSCR_TE,
 365         .sampling_rate  = 8,
 366         .type           = PORT_SCIFA,
 367 };
 368
 369 static struct resource scif3_resources[] = {
 370         DEFINE_RES_MEM(0xa4e30000, 0x100),
 371         DEFINE_RES_IRQ(evt2irq(0x900)),
 372 };
 373
 374 static struct platform_device scif3_device = {
 375         .name           = "sh-sci",
 376         .id             = 3,
 377         .resource       = scif3_resources,
 378         .num_resources  = ARRAY_SIZE(scif3_resources),
 379         .dev            = {
 380                 .platform_data  = &scif3_platform_data,
 381         },
 382 };
 383
 384 static struct plat_sci_port scif4_platform_data = {
 385         .port_reg       = SCIx_NOT_SUPPORTED,
 386         .flags          = UPF_BOOT_AUTOCONF,
 387         .scscr          = SCSCR_RE | SCSCR_TE,
 388         .sampling_rate  = 8,
 389         .type           = PORT_SCIFA,
 390 };
 391
 392 static struct resource scif4_resources[] = {
 393         DEFINE_RES_MEM(0xa4e40000, 0x100),
 394         DEFINE_RES_IRQ(evt2irq(0xd00)),
 395 };
 396
 397 static struct platform_device scif4_device = {
 398         .name           = "sh-sci",
 399         .id             = 4,
 400         .resource       = scif4_resources,
 401         .num_resources  = ARRAY_SIZE(scif4_resources),
 402         .dev            = {
 403                 .platform_data  = &scif4_platform_data,
 404         },
 405 };
 406
 407 static struct plat_sci_port scif5_platform_data = {
 408         .port_reg       = SCIx_NOT_SUPPORTED,
 409         .flags          = UPF_BOOT_AUTOCONF,
 410         .scscr          = SCSCR_RE | SCSCR_TE,
 411         .sampling_rate  = 8,
 412         .type           = PORT_SCIFA,
 413 };
 414
 415 static struct resource scif5_resources[] = {
 416         DEFINE_RES_MEM(0xa4e50000, 0x100),
 417         DEFINE_RES_IRQ(evt2irq(0xfa0)),
 418 };
 419
 420 static struct platform_device scif5_device = {
 421         .name           = "sh-sci",
 422         .id             = 5,
 423         .resource       = scif5_resources,
 424         .num_resources  = ARRAY_SIZE(scif5_resources),
 425         .dev            = {
 426                 .platform_data  = &scif5_platform_data,
 427         },
 428 };
 429
 430 /* RTC */
 431 static struct resource rtc_resources[] = {
 432         [0] = {
 433                 .start  = 0xa465fec0,
 434                 .end    = 0xa465fec0 + 0x58 - 1,
 435                 .flags  = IORESOURCE_IO,
 436         },
 437         [1] = {
 438                 /* Period IRQ */
 439                 .start  = evt2irq(0xaa0),
 440                 .flags  = IORESOURCE_IRQ,
 441         },
 442         [2] = {
 443                 /* Carry IRQ */
 444                 .start  = evt2irq(0xac0),
 445                 .flags  = IORESOURCE_IRQ,
 446         },
 447         [3] = {
 448                 /* Alarm IRQ */
 449                 .start  = evt2irq(0xa80),
 450                 .flags  = IORESOURCE_IRQ,
 451         },
 452 };
 453
 454 static struct platform_device rtc_device = {
 455         .name           = "sh-rtc",
 456         .id             = -1,
 457         .num_resources  = ARRAY_SIZE(rtc_resources),
 458         .resource       = rtc_resources,
 459 };
 460
 461 /* I2C0 */
 462 static struct resource iic0_resources[] = {
 463         [0] = {
 464                 .name   = "IIC0",
 465                 .start  = 0x04470000,
 466                 .end    = 0x04470018 - 1,
 467                 .flags  = IORESOURCE_MEM,
 468         },
 469         [1] = {
 470                 .start  = evt2irq(0xe00),
 471                 .end    = evt2irq(0xe60),
 472                 .flags  = IORESOURCE_IRQ,
 473         },
 474 };
 475
 476 static struct platform_device iic0_device = {
 477         .name           = "i2c-sh_mobile",
 478         .id             = 0, /* "i2c0" clock */
 479         .num_resources  = ARRAY_SIZE(iic0_resources),
 480         .resource       = iic0_resources,
 481 };
 482
 483 /* I2C1 */
 484 static struct resource iic1_resources[] = {
 485         [0] = {
 486                 .name   = "IIC1",
 487                 .start  = 0x04750000,
 488                 .end    = 0x04750018 - 1,
 489                 .flags  = IORESOURCE_MEM,
 490         },
 491         [1] = {
 492                 .start  = evt2irq(0xd80),
 493                 .end    = evt2irq(0xde0),
 494                 .flags  = IORESOURCE_IRQ,
 495         },
 496 };
 497
 498 static struct platform_device iic1_device = {
 499         .name           = "i2c-sh_mobile",
 500         .id             = 1, /* "i2c1" clock */
 501         .num_resources  = ARRAY_SIZE(iic1_resources),
 502         .resource       = iic1_resources,
 503 };
 504
 505 /* VPU */
 506 static struct uio_info vpu_platform_data = {
 507         .name = "VPU5F",
 508         .version = "0",
 509         .irq = evt2irq(0x980),
 510 };
 511
 512 static struct resource vpu_resources[] = {
 513         [0] = {
 514                 .name   = "VPU",
 515                 .start  = 0xfe900000,
 516                 .end    = 0xfe902807,
 517                 .flags  = IORESOURCE_MEM,
 518         },
 519         [1] = {
 520                 /* place holder for contiguous memory */
 521         },
 522 };
 523
 524 static struct platform_device vpu_device = {
 525         .name           = "uio_pdrv_genirq",
 526         .id             = 0,
 527         .dev = {
 528                 .platform_data  = &vpu_platform_data,
 529         },
 530         .resource       = vpu_resources,
 531         .num_resources  = ARRAY_SIZE(vpu_resources),
 532 };
 533
 534 /* VEU0 */
 535 static struct uio_info veu0_platform_data = {
 536         .name = "VEU3F0",
 537         .version = "0",
 538         .irq = evt2irq(0xc60),
 539 };
 540
 541 static struct resource veu0_resources[] = {
 542         [0] = {
 543                 .name   = "VEU3F0",
 544                 .start  = 0xfe920000,
 545                 .end    = 0xfe9200cb,
 546                 .flags  = IORESOURCE_MEM,
 547         },
 548         [1] = {
 549                 /* place holder for contiguous memory */
 550         },
 551 };
 552
 553 static struct platform_device veu0_device = {
 554         .name           = "uio_pdrv_genirq",
 555         .id             = 1,
 556         .dev = {
 557                 .platform_data  = &veu0_platform_data,
 558         },
 559         .resource       = veu0_resources,
 560         .num_resources  = ARRAY_SIZE(veu0_resources),
 561 };
 562
 563 /* VEU1 */
 564 static struct uio_info veu1_platform_data = {
 565         .name = "VEU3F1",
 566         .version = "0",
 567         .irq = evt2irq(0x8c0),
 568 };
 569
 570 static struct resource veu1_resources[] = {
 571         [0] = {
 572                 .name   = "VEU3F1",
 573                 .start  = 0xfe924000,
 574                 .end    = 0xfe9240cb,
 575                 .flags  = IORESOURCE_MEM,
 576         },
 577         [1] = {
 578                 /* place holder for contiguous memory */
 579         },
 580 };
 581
 582 static struct platform_device veu1_device = {
 583         .name           = "uio_pdrv_genirq",
 584         .id             = 2,
 585         .dev = {
 586                 .platform_data  = &veu1_platform_data,
 587         },
 588         .resource       = veu1_resources,
 589         .num_resources  = ARRAY_SIZE(veu1_resources),
 590 };
 591
 592 /* BEU0 */
 593 static struct uio_info beu0_platform_data = {
 594         .name = "BEU0",
 595         .version = "0",
 596         .irq = evt2irq(0x8A0),
 597 };
 598
 599 static struct resource beu0_resources[] = {
 600         [0] = {
 601                 .name   = "BEU0",
 602                 .start  = 0xfe930000,
 603                 .end    = 0xfe933400,
 604                 .flags  = IORESOURCE_MEM,
 605         },
 606         [1] = {
 607                 /* place holder for contiguous memory */
 608         },
 609 };
 610
 611 static struct platform_device beu0_device = {
 612         .name           = "uio_pdrv_genirq",
 613         .id             = 6,
 614         .dev = {
 615                 .platform_data  = &beu0_platform_data,
 616         },
 617         .resource       = beu0_resources,
 618         .num_resources  = ARRAY_SIZE(beu0_resources),
 619 };
 620
 621 /* BEU1 */
 622 static struct uio_info beu1_platform_data = {
 623         .name = "BEU1",
 624         .version = "0",
 625         .irq = evt2irq(0xA00),
 626 };
 627
 628 static struct resource beu1_resources[] = {
 629         [0] = {
 630                 .name   = "BEU1",
 631                 .start  = 0xfe940000,
 632                 .end    = 0xfe943400,
 633                 .flags  = IORESOURCE_MEM,
 634         },
 635         [1] = {
 636                 /* place holder for contiguous memory */
 637         },
 638 };
 639
 640 static struct platform_device beu1_device = {
 641         .name           = "uio_pdrv_genirq",
 642         .id             = 7,
 643         .dev = {
 644                 .platform_data  = &beu1_platform_data,
 645         },
 646         .resource       = beu1_resources,
 647         .num_resources  = ARRAY_SIZE(beu1_resources),
 648 };
 649
 650 static struct sh_timer_config cmt_platform_data = {
 651         .channels_mask = 0x20,
 652 };
 653
 654 static struct resource cmt_resources[] = {
 655         DEFINE_RES_MEM(0x044a0000, 0x70),
 656         DEFINE_RES_IRQ(evt2irq(0xf00)),
 657 };
 658
 659 static struct platform_device cmt_device = {
 660         .name           = "sh-cmt-32",
 661         .id             = 0,
 662         .dev = {
 663                 .platform_data  = &cmt_platform_data,
 664         },
 665         .resource       = cmt_resources,
 666         .num_resources  = ARRAY_SIZE(cmt_resources),
 667 };
 668
 669 static struct sh_timer_config tmu0_platform_data = {
 670         .channel_offset = 0x04,
 671         .timer_bit = 0,
 672         .clockevent_rating = 200,
 673 };
 674
 675 static struct resource tmu0_resources[] = {
 676         [0] = {
 677                 .start  = 0xffd80008,
 678                 .end    = 0xffd80013,
 679                 .flags  = IORESOURCE_MEM,
 680         },
 681         [1] = {
 682                 .start  = evt2irq(0x400),
 683                 .flags  = IORESOURCE_IRQ,
 684         },
 685 };
 686
 687 static struct platform_device tmu0_device = {
 688         .name           = "sh_tmu",
 689         .id             = 0,
 690         .dev = {
 691                 .platform_data  = &tmu0_platform_data,
 692         },
 693         .resource       = tmu0_resources,
 694         .num_resources  = ARRAY_SIZE(tmu0_resources),
 695 };
 696
 697 static struct sh_timer_config tmu1_platform_data = {
 698         .channel_offset = 0x10,
 699         .timer_bit = 1,
 700         .clocksource_rating = 200,
 701 };
 702
 703 static struct resource tmu1_resources[] = {
 704         [0] = {
 705                 .start  = 0xffd80014,
 706                 .end    = 0xffd8001f,
 707                 .flags  = IORESOURCE_MEM,
 708         },
 709         [1] = {
 710                 .start  = evt2irq(0x420),
 711                 .flags  = IORESOURCE_IRQ,
 712         },
 713 };
 714
 715 static struct platform_device tmu1_device = {
 716         .name           = "sh_tmu",
 717         .id             = 1,
 718         .dev = {
 719                 .platform_data  = &tmu1_platform_data,
 720         },
 721         .resource       = tmu1_resources,
 722         .num_resources  = ARRAY_SIZE(tmu1_resources),
 723 };
 724
 725 static struct sh_timer_config tmu2_platform_data = {
 726         .channel_offset = 0x1c,
 727         .timer_bit = 2,
 728 };
 729
 730 static struct resource tmu2_resources[] = {
 731         [0] = {
 732                 .start  = 0xffd80020,
 733                 .end    = 0xffd8002b,
 734                 .flags  = IORESOURCE_MEM,
 735         },
 736         [1] = {
 737                 .start  = evt2irq(0x440),
 738                 .flags  = IORESOURCE_IRQ,
 739         },
 740 };
 741
 742 static struct platform_device tmu2_device = {
 743         .name           = "sh_tmu",
 744         .id             = 2,
 745         .dev = {
 746                 .platform_data  = &tmu2_platform_data,
 747         },
 748         .resource       = tmu2_resources,
 749         .num_resources  = ARRAY_SIZE(tmu2_resources),
 750 };
 751
 752
 753 static struct sh_timer_config tmu3_platform_data = {
 754         .channel_offset = 0x04,
 755         .timer_bit = 0,
 756 };
 757
 758 static struct resource tmu3_resources[] = {
 759         [0] = {
 760                 .start  = 0xffd90008,
 761                 .end    = 0xffd90013,
 762                 .flags  = IORESOURCE_MEM,
 763         },
 764         [1] = {
 765                 .start  = evt2irq(0x920),
 766                 .flags  = IORESOURCE_IRQ,
 767         },
 768 };
 769
 770 static struct platform_device tmu3_device = {
 771         .name           = "sh_tmu",
 772         .id             = 3,
 773         .dev = {
 774                 .platform_data  = &tmu3_platform_data,
 775         },
 776         .resource       = tmu3_resources,
 777         .num_resources  = ARRAY_SIZE(tmu3_resources),
 778 };
 779
 780 static struct sh_timer_config tmu4_platform_data = {
 781         .channel_offset = 0x10,
 782         .timer_bit = 1,
 783 };
 784
 785 static struct resource tmu4_resources[] = {
 786         [0] = {
 787                 .start  = 0xffd90014,
 788                 .end    = 0xffd9001f,
 789                 .flags  = IORESOURCE_MEM,
 790         },
 791         [1] = {
 792                 .start  = evt2irq(0x940),
 793                 .flags  = IORESOURCE_IRQ,
 794         },
 795 };
 796
 797 static struct platform_device tmu4_device = {
 798         .name           = "sh_tmu",
 799         .id             = 4,
 800         .dev = {
 801                 .platform_data  = &tmu4_platform_data,
 802         },
 803         .resource       = tmu4_resources,
 804         .num_resources  = ARRAY_SIZE(tmu4_resources),
 805 };
 806
 807 static struct sh_timer_config tmu5_platform_data = {
 808         .channel_offset = 0x1c,
 809         .timer_bit = 2,
 810 };
 811
 812 static struct resource tmu5_resources[] = {
 813         [0] = {
 814                 .start  = 0xffd90020,
 815                 .end    = 0xffd9002b,
 816                 .flags  = IORESOURCE_MEM,
 817         },
 818         [1] = {
 819                 .start  = evt2irq(0x920),
 820                 .flags  = IORESOURCE_IRQ,
 821         },
 822 };
 823
 824 static struct platform_device tmu5_device = {
 825         .name           = "sh_tmu",
 826         .id             = 5,
 827         .dev = {
 828                 .platform_data  = &tmu5_platform_data,
 829         },
 830         .resource       = tmu5_resources,
 831         .num_resources  = ARRAY_SIZE(tmu5_resources),
 832 };
 833
 834 /* JPU */
 835 static struct uio_info jpu_platform_data = {
 836         .name = "JPU",
 837         .version = "0",
 838         .irq = evt2irq(0x560),
 839 };
 840
 841 static struct resource jpu_resources[] = {
 842         [0] = {
 843                 .name   = "JPU",
 844                 .start  = 0xfe980000,
 845                 .end    = 0xfe9902d3,
 846                 .flags  = IORESOURCE_MEM,
 847         },
 848         [1] = {
 849                 /* place holder for contiguous memory */
 850         },
 851 };
 852
 853 static struct platform_device jpu_device = {
 854         .name           = "uio_pdrv_genirq",
 855         .id             = 3,
 856         .dev = {
 857                 .platform_data  = &jpu_platform_data,
 858         },
 859         .resource       = jpu_resources,
 860         .num_resources  = ARRAY_SIZE(jpu_resources),
 861 };
 862
 863 /* SPU2DSP0 */
 864 static struct uio_info spu0_platform_data = {
 865         .name = "SPU2DSP0",
 866         .version = "0",
 867         .irq = evt2irq(0xcc0),
 868 };
 869
 870 static struct resource spu0_resources[] = {
 871         [0] = {
 872                 .name   = "SPU2DSP0",
 873                 .start  = 0xFE200000,
 874                 .end    = 0xFE2FFFFF,
 875                 .flags  = IORESOURCE_MEM,
 876         },
 877         [1] = {
 878                 /* place holder for contiguous memory */
 879         },
 880 };
 881
 882 static struct platform_device spu0_device = {
 883         .name           = "uio_pdrv_genirq",
 884         .id             = 4,
 885         .dev = {
 886                 .platform_data  = &spu0_platform_data,
 887         },
 888         .resource       = spu0_resources,
 889         .num_resources  = ARRAY_SIZE(spu0_resources),
 890 };
 891
 892 /* SPU2DSP1 */
 893 static struct uio_info spu1_platform_data = {
 894         .name = "SPU2DSP1",
 895         .version = "0",
 896         .irq = evt2irq(0xce0),
 897 };
 898
 899 static struct resource spu1_resources[] = {
 900         [0] = {
 901                 .name   = "SPU2DSP1",
 902                 .start  = 0xFE300000,
 903                 .end    = 0xFE3FFFFF,
 904                 .flags  = IORESOURCE_MEM,
 905         },
 906         [1] = {
 907                 /* place holder for contiguous memory */
 908         },
 909 };
 910
 911 static struct platform_device spu1_device = {
 912         .name           = "uio_pdrv_genirq",
 913         .id             = 5,
 914         .dev = {
 915                 .platform_data  = &spu1_platform_data,
 916         },
 917         .resource       = spu1_resources,
 918         .num_resources  = ARRAY_SIZE(spu1_resources),
 919 };
 920
 921 static struct platform_device *sh7724_devices[] __initdata = {
 922         &scif0_device,
 923         &scif1_device,
 924         &scif2_device,
 925         &scif3_device,
 926         &scif4_device,
 927         &scif5_device,
 928         &cmt_device,
 929         &tmu0_device,
 930         &tmu1_device,
 931         &tmu2_device,
 932         &tmu3_device,
 933         &tmu4_device,
 934         &tmu5_device,
 935         &dma0_device,
 936         &dma1_device,
 937         &rtc_device,
 938         &iic0_device,
 939         &iic1_device,
 940         &vpu_device,
 941         &veu0_device,
 942         &veu1_device,
 943         &beu0_device,
 944         &beu1_device,
 945         &jpu_device,
 946         &spu0_device,
 947         &spu1_device,
 948 };
 949
 950 static int __init sh7724_devices_setup(void)
 951 {
 952         platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
 953         platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
 954         platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
 955         platform_resource_setup_memory(&jpu_device,  "jpu",  2 << 20);
 956         platform_resource_setup_memory(&spu0_device, "spu0", 2 << 20);
 957         platform_resource_setup_memory(&spu1_device, "spu1", 2 << 20);
 958
 959         return platform_add_devices(sh7724_devices,
 960                                     ARRAY_SIZE(sh7724_devices));
 961 }
 962 arch_initcall(sh7724_devices_setup);
 963
 964 static struct platform_device *sh7724_early_devices[] __initdata = {
 965         &scif0_device,
 966         &scif1_device,
 967         &scif2_device,
 968         &scif3_device,
 969         &scif4_device,
 970         &scif5_device,
 971         &cmt_device,
 972         &tmu0_device,
 973         &tmu1_device,
 974         &tmu2_device,
 975         &tmu3_device,
 976         &tmu4_device,
 977         &tmu5_device,
 978 };
 979
 980 void __init plat_early_device_setup(void)
 981 {
 982         early_platform_add_devices(sh7724_early_devices,
 983                                    ARRAY_SIZE(sh7724_early_devices));
 984 }
 985
 986 #define RAMCR_CACHE_L2FC        0x0002
 987 #define RAMCR_CACHE_L2E         0x0001
 988 #define L2_CACHE_ENABLE         (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
 989
 990 void l2_cache_init(void)
 991 {
 992         /* Enable L2 cache */
 993         __raw_writel(L2_CACHE_ENABLE, RAMCR);
 994 }
 995
 996 enum {
 997         UNUSED = 0,
 998         ENABLED,
 999         DISABLED,
1000
1001         /* interrupt sources */
1002         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
1003         HUDI,
1004         DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3,
1005         _2DG_TRI, _2DG_INI, _2DG_CEI,
1006         DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3,
1007         VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU,
1008         SCIFA3,
1009         VPU,
1010         TPU,
1011         CEU1,
1012         BEU1,
1013         USB0, USB1,
1014         ATAPI,
1015         RTC_ATI, RTC_PRI, RTC_CUI,
1016         DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR,
1017         DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR,
1018         KEYSC,
1019         SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,
1020         VEU0,
1021         MSIOF_MSIOFI0, MSIOF_MSIOFI1,
1022         SPU_SPUI0, SPU_SPUI1,
1023         SCIFA4,
1024         ICB,
1025         ETHI,
1026         I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
1027         I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
1028         CMT,
1029         TSIF,
1030         FSI,
1031         SCIFA5,
1032         TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
1033         IRDA,
1034         JPU,
1035         _2DDMAC,
1036         MMC_MMC2I, MMC_MMC3I,
1037         LCDC,
1038         TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
1039
1040         /* interrupt groups */
1041         DMAC1A, _2DG, DMAC0A, VIO, USB, RTC,
1042         DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMCIF,
1043 };
1044
1045 static struct intc_vect vectors[] __initdata = {
1046         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
1047         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
1048         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
1049         INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
1050
1051         INTC_VECT(DMAC1A_DEI0, 0x700),
1052         INTC_VECT(DMAC1A_DEI1, 0x720),
1053         INTC_VECT(DMAC1A_DEI2, 0x740),
1054         INTC_VECT(DMAC1A_DEI3, 0x760),
1055
1056         INTC_VECT(_2DG_TRI, 0x780),
1057         INTC_VECT(_2DG_INI, 0x7A0),
1058         INTC_VECT(_2DG_CEI, 0x7C0),
1059
1060         INTC_VECT(DMAC0A_DEI0, 0x800),
1061         INTC_VECT(DMAC0A_DEI1, 0x820),
1062         INTC_VECT(DMAC0A_DEI2, 0x840),
1063         INTC_VECT(DMAC0A_DEI3, 0x860),
1064
1065         INTC_VECT(VIO_CEU0, 0x880),
1066         INTC_VECT(VIO_BEU0, 0x8A0),
1067         INTC_VECT(VIO_VEU1, 0x8C0),
1068         INTC_VECT(VIO_VOU,  0x8E0),
1069
1070         INTC_VECT(SCIFA3, 0x900),
1071         INTC_VECT(VPU,    0x980),
1072         INTC_VECT(TPU,    0x9A0),
1073         INTC_VECT(CEU1,   0x9E0),
1074         INTC_VECT(BEU1,   0xA00),
1075         INTC_VECT(USB0,   0xA20),
1076         INTC_VECT(USB1,   0xA40),
1077         INTC_VECT(ATAPI,  0xA60),
1078
1079         INTC_VECT(RTC_ATI, 0xA80),
1080         INTC_VECT(RTC_PRI, 0xAA0),
1081         INTC_VECT(RTC_CUI, 0xAC0),
1082
1083         INTC_VECT(DMAC1B_DEI4, 0xB00),
1084         INTC_VECT(DMAC1B_DEI5, 0xB20),
1085         INTC_VECT(DMAC1B_DADERR, 0xB40),
1086
1087         INTC_VECT(DMAC0B_DEI4, 0xB80),
1088         INTC_VECT(DMAC0B_DEI5, 0xBA0),
1089         INTC_VECT(DMAC0B_DADERR, 0xBC0),
1090
1091         INTC_VECT(KEYSC,      0xBE0),
1092         INTC_VECT(SCIF_SCIF0, 0xC00),
1093         INTC_VECT(SCIF_SCIF1, 0xC20),
1094         INTC_VECT(SCIF_SCIF2, 0xC40),
1095         INTC_VECT(VEU0,       0xC60),
1096         INTC_VECT(MSIOF_MSIOFI0, 0xC80),
1097         INTC_VECT(MSIOF_MSIOFI1, 0xCA0),
1098         INTC_VECT(SPU_SPUI0, 0xCC0),
1099         INTC_VECT(SPU_SPUI1, 0xCE0),
1100         INTC_VECT(SCIFA4,    0xD00),
1101
1102         INTC_VECT(ICB,  0xD20),
1103         INTC_VECT(ETHI, 0xD60),
1104
1105         INTC_VECT(I2C1_ALI, 0xD80),
1106         INTC_VECT(I2C1_TACKI, 0xDA0),
1107         INTC_VECT(I2C1_WAITI, 0xDC0),
1108         INTC_VECT(I2C1_DTEI, 0xDE0),
1109
1110         INTC_VECT(I2C0_ALI, 0xE00),
1111         INTC_VECT(I2C0_TACKI, 0xE20),
1112         INTC_VECT(I2C0_WAITI, 0xE40),
1113         INTC_VECT(I2C0_DTEI, 0xE60),
1114
1115         INTC_VECT(SDHI0, 0xE80),
1116         INTC_VECT(SDHI0, 0xEA0),
1117         INTC_VECT(SDHI0, 0xEC0),
1118         INTC_VECT(SDHI0, 0xEE0),
1119
1120         INTC_VECT(CMT,    0xF00),
1121         INTC_VECT(TSIF,   0xF20),
1122         INTC_VECT(FSI,    0xF80),
1123         INTC_VECT(SCIFA5, 0xFA0),
1124
1125         INTC_VECT(TMU0_TUNI0, 0x400),
1126         INTC_VECT(TMU0_TUNI1, 0x420),
1127         INTC_VECT(TMU0_TUNI2, 0x440),
1128
1129         INTC_VECT(IRDA,    0x480),
1130
1131         INTC_VECT(SDHI1, 0x4E0),
1132         INTC_VECT(SDHI1, 0x500),
1133         INTC_VECT(SDHI1, 0x520),
1134
1135         INTC_VECT(JPU, 0x560),
1136         INTC_VECT(_2DDMAC, 0x4A0),
1137
1138         INTC_VECT(MMC_MMC2I, 0x5A0),
1139         INTC_VECT(MMC_MMC3I, 0x5C0),
1140
1141         INTC_VECT(LCDC, 0xF40),
1142
1143         INTC_VECT(TMU1_TUNI0, 0x920),
1144         INTC_VECT(TMU1_TUNI1, 0x940),
1145         INTC_VECT(TMU1_TUNI2, 0x960),
1146 };
1147
1148 static struct intc_group groups[] __initdata = {
1149         INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3),
1150         INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI),
1151         INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3),
1152         INTC_GROUP(VIO, VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU),
1153         INTC_GROUP(USB, USB0, USB1),
1154         INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
1155         INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR),
1156         INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR),
1157         INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
1158         INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
1159         INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1),
1160         INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I),
1161 };
1162
1163 static struct intc_mask_reg mask_registers[] __initdata = {
1164         { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
1165           { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
1166             0, ENABLED, ENABLED, ENABLED } },
1167         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
1168           { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0,
1169             DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } },
1170         { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
1171           { 0, 0, 0, VPU, ATAPI, ETHI, 0, SCIFA3 } },
1172         { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
1173           { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0,
1174             SPU_SPUI1, SPU_SPUI0, BEU1, IRDA } },
1175         { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
1176           { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0,
1177             JPU, 0, 0, LCDC } },
1178         { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
1179           { KEYSC, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4,
1180             VEU0, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } },
1181         { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
1182           { 0, 0, ICB, SCIFA4,
1183             CEU1, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } },
1184         { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
1185           { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
1186             I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } },
1187         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
1188           { DISABLED, ENABLED, ENABLED, ENABLED,
1189             0, 0, SCIFA5, FSI } },
1190         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
1191           { 0, 0, 0, CMT, 0, USB1, USB0, 0 } },
1192         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
1193           { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4,
1194             0, RTC_CUI, RTC_PRI, RTC_ATI } },
1195         { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
1196           { 0, _2DG_CEI, _2DG_INI, _2DG_TRI,
1197             0, TPU, 0, TSIF } },
1198         { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
1199           { 0, 0, MMC_MMC3I, MMC_MMC2I, 0, 0, 0, _2DDMAC } },
1200         { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
1201           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1202 };
1203
1204 static struct intc_prio_reg prio_registers[] __initdata = {
1205         { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1,
1206                                              TMU0_TUNI2, IRDA } },
1207         { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, DMAC1A, BEU1 } },
1208         { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1,
1209                                              TMU1_TUNI2, SPU } },
1210         { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMCIF, 0, ATAPI } },
1211         { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA3, VPU } },
1212         { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC0B, USB, CMT } },
1213         { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1,
1214                                              SCIF_SCIF2, VEU0 } },
1215         { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1,
1216                                              I2C1, I2C0 } },
1217         { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA4, ICB, TSIF, _2DG } },
1218         { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU1, ETHI, FSI, SDHI1 } },
1219         { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, 0, SDHI0 } },
1220         { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA5, 0, TPU, _2DDMAC } },
1221         { 0xa4140010, 0, 32, 4, /* INTPRI00 */
1222           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1223 };
1224
1225 static struct intc_sense_reg sense_registers[] __initdata = {
1226         { 0xa414001c, 16, 2, /* ICR1 */
1227           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1228 };
1229
1230 static struct intc_mask_reg ack_registers[] __initdata = {
1231         { 0xa4140024, 0, 8, /* INTREQ00 */
1232           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1233 };
1234
1235 static struct intc_desc intc_desc __initdata = {
1236         .name = "sh7724",
1237         .force_enable = ENABLED,
1238         .force_disable = DISABLED,
1239         .hw = INTC_HW_DESC(vectors, groups, mask_registers,
1240                            prio_registers, sense_registers, ack_registers),
1241 };
1242
1243 void __init plat_irq_setup(void)
1244 {
1245         register_intc_controller(&intc_desc);
1246 }
1247
1248 static struct {
1249         /* BSC */
1250         unsigned long mmselr;
1251         unsigned long cs0bcr;
1252         unsigned long cs4bcr;
1253         unsigned long cs5abcr;
1254         unsigned long cs5bbcr;
1255         unsigned long cs6abcr;
1256         unsigned long cs6bbcr;
1257         unsigned long cs4wcr;
1258         unsigned long cs5awcr;
1259         unsigned long cs5bwcr;
1260         unsigned long cs6awcr;
1261         unsigned long cs6bwcr;
1262         /* INTC */
1263         unsigned short ipra;
1264         unsigned short iprb;
1265         unsigned short iprc;
1266         unsigned short iprd;
1267         unsigned short ipre;
1268         unsigned short iprf;
1269         unsigned short iprg;
1270         unsigned short iprh;
1271         unsigned short ipri;
1272         unsigned short iprj;
1273         unsigned short iprk;
1274         unsigned short iprl;
1275         unsigned char imr0;
1276         unsigned char imr1;
1277         unsigned char imr2;
1278         unsigned char imr3;
1279         unsigned char imr4;
1280         unsigned char imr5;
1281         unsigned char imr6;
1282         unsigned char imr7;
1283         unsigned char imr8;
1284         unsigned char imr9;
1285         unsigned char imr10;
1286         unsigned char imr11;
1287         unsigned char imr12;
1288         /* RWDT */
1289         unsigned short rwtcnt;
1290         unsigned short rwtcsr;
1291         /* CPG */
1292         unsigned long irdaclk;
1293         unsigned long spuclk;
1294 } sh7724_rstandby_state;
1295
1296 static int sh7724_pre_sleep_notifier_call(struct notifier_block *nb,
1297                                           unsigned long flags, void *unused)
1298 {
1299         if (!(flags & SUSP_SH_RSTANDBY))
1300                 return NOTIFY_DONE;
1301
1302         /* BCR */
1303         sh7724_rstandby_state.mmselr = __raw_readl(0xff800020); /* MMSELR */
1304         sh7724_rstandby_state.mmselr |= 0xa5a50000;
1305         sh7724_rstandby_state.cs0bcr = __raw_readl(0xfec10004); /* CS0BCR */
1306         sh7724_rstandby_state.cs4bcr = __raw_readl(0xfec10010); /* CS4BCR */
1307         sh7724_rstandby_state.cs5abcr = __raw_readl(0xfec10014); /* CS5ABCR */
1308         sh7724_rstandby_state.cs5bbcr = __raw_readl(0xfec10018); /* CS5BBCR */
1309         sh7724_rstandby_state.cs6abcr = __raw_readl(0xfec1001c); /* CS6ABCR */
1310         sh7724_rstandby_state.cs6bbcr = __raw_readl(0xfec10020); /* CS6BBCR */
1311         sh7724_rstandby_state.cs4wcr = __raw_readl(0xfec10030); /* CS4WCR */
1312         sh7724_rstandby_state.cs5awcr = __raw_readl(0xfec10034); /* CS5AWCR */
1313         sh7724_rstandby_state.cs5bwcr = __raw_readl(0xfec10038); /* CS5BWCR */
1314         sh7724_rstandby_state.cs6awcr = __raw_readl(0xfec1003c); /* CS6AWCR */
1315         sh7724_rstandby_state.cs6bwcr = __raw_readl(0xfec10040); /* CS6BWCR */
1316
1317         /* INTC */
1318         sh7724_rstandby_state.ipra = __raw_readw(0xa4080000); /* IPRA */
1319         sh7724_rstandby_state.iprb = __raw_readw(0xa4080004); /* IPRB */
1320         sh7724_rstandby_state.iprc = __raw_readw(0xa4080008); /* IPRC */
1321         sh7724_rstandby_state.iprd = __raw_readw(0xa408000c); /* IPRD */
1322         sh7724_rstandby_state.ipre = __raw_readw(0xa4080010); /* IPRE */
1323         sh7724_rstandby_state.iprf = __raw_readw(0xa4080014); /* IPRF */
1324         sh7724_rstandby_state.iprg = __raw_readw(0xa4080018); /* IPRG */
1325         sh7724_rstandby_state.iprh = __raw_readw(0xa408001c); /* IPRH */
1326         sh7724_rstandby_state.ipri = __raw_readw(0xa4080020); /* IPRI */
1327         sh7724_rstandby_state.iprj = __raw_readw(0xa4080024); /* IPRJ */
1328         sh7724_rstandby_state.iprk = __raw_readw(0xa4080028); /* IPRK */
1329         sh7724_rstandby_state.iprl = __raw_readw(0xa408002c); /* IPRL */
1330         sh7724_rstandby_state.imr0 = __raw_readb(0xa4080080); /* IMR0 */
1331         sh7724_rstandby_state.imr1 = __raw_readb(0xa4080084); /* IMR1 */
1332         sh7724_rstandby_state.imr2 = __raw_readb(0xa4080088); /* IMR2 */
1333         sh7724_rstandby_state.imr3 = __raw_readb(0xa408008c); /* IMR3 */
1334         sh7724_rstandby_state.imr4 = __raw_readb(0xa4080090); /* IMR4 */
1335         sh7724_rstandby_state.imr5 = __raw_readb(0xa4080094); /* IMR5 */
1336         sh7724_rstandby_state.imr6 = __raw_readb(0xa4080098); /* IMR6 */
1337         sh7724_rstandby_state.imr7 = __raw_readb(0xa408009c); /* IMR7 */
1338         sh7724_rstandby_state.imr8 = __raw_readb(0xa40800a0); /* IMR8 */
1339         sh7724_rstandby_state.imr9 = __raw_readb(0xa40800a4); /* IMR9 */
1340         sh7724_rstandby_state.imr10 = __raw_readb(0xa40800a8); /* IMR10 */
1341         sh7724_rstandby_state.imr11 = __raw_readb(0xa40800ac); /* IMR11 */
1342         sh7724_rstandby_state.imr12 = __raw_readb(0xa40800b0); /* IMR12 */
1343
1344         /* RWDT */
1345         sh7724_rstandby_state.rwtcnt = __raw_readb(0xa4520000); /* RWTCNT */
1346         sh7724_rstandby_state.rwtcnt |= 0x5a00;
1347         sh7724_rstandby_state.rwtcsr = __raw_readb(0xa4520004); /* RWTCSR */
1348         sh7724_rstandby_state.rwtcsr |= 0xa500;
1349         __raw_writew(sh7724_rstandby_state.rwtcsr & 0x07, 0xa4520004);
1350
1351         /* CPG */
1352         sh7724_rstandby_state.irdaclk = __raw_readl(0xa4150018); /* IRDACLKCR */
1353         sh7724_rstandby_state.spuclk = __raw_readl(0xa415003c); /* SPUCLKCR */
1354
1355         return NOTIFY_DONE;
1356 }
1357
1358 static int sh7724_post_sleep_notifier_call(struct notifier_block *nb,
1359                                            unsigned long flags, void *unused)
1360 {
1361         if (!(flags & SUSP_SH_RSTANDBY))
1362                 return NOTIFY_DONE;
1363
1364         /* BCR */
1365         __raw_writel(sh7724_rstandby_state.mmselr, 0xff800020); /* MMSELR */
1366         __raw_writel(sh7724_rstandby_state.cs0bcr, 0xfec10004); /* CS0BCR */
1367         __raw_writel(sh7724_rstandby_state.cs4bcr, 0xfec10010); /* CS4BCR */
1368         __raw_writel(sh7724_rstandby_state.cs5abcr, 0xfec10014); /* CS5ABCR */
1369         __raw_writel(sh7724_rstandby_state.cs5bbcr, 0xfec10018); /* CS5BBCR */
1370         __raw_writel(sh7724_rstandby_state.cs6abcr, 0xfec1001c); /* CS6ABCR */
1371         __raw_writel(sh7724_rstandby_state.cs6bbcr, 0xfec10020); /* CS6BBCR */
1372         __raw_writel(sh7724_rstandby_state.cs4wcr, 0xfec10030); /* CS4WCR */
1373         __raw_writel(sh7724_rstandby_state.cs5awcr, 0xfec10034); /* CS5AWCR */
1374         __raw_writel(sh7724_rstandby_state.cs5bwcr, 0xfec10038); /* CS5BWCR */
1375         __raw_writel(sh7724_rstandby_state.cs6awcr, 0xfec1003c); /* CS6AWCR */
1376         __raw_writel(sh7724_rstandby_state.cs6bwcr, 0xfec10040); /* CS6BWCR */
1377
1378         /* INTC */
1379         __raw_writew(sh7724_rstandby_state.ipra, 0xa4080000); /* IPRA */
1380         __raw_writew(sh7724_rstandby_state.iprb, 0xa4080004); /* IPRB */
1381         __raw_writew(sh7724_rstandby_state.iprc, 0xa4080008); /* IPRC */
1382         __raw_writew(sh7724_rstandby_state.iprd, 0xa408000c); /* IPRD */
1383         __raw_writew(sh7724_rstandby_state.ipre, 0xa4080010); /* IPRE */
1384         __raw_writew(sh7724_rstandby_state.iprf, 0xa4080014); /* IPRF */
1385         __raw_writew(sh7724_rstandby_state.iprg, 0xa4080018); /* IPRG */
1386         __raw_writew(sh7724_rstandby_state.iprh, 0xa408001c); /* IPRH */
1387         __raw_writew(sh7724_rstandby_state.ipri, 0xa4080020); /* IPRI */
1388         __raw_writew(sh7724_rstandby_state.iprj, 0xa4080024); /* IPRJ */
1389         __raw_writew(sh7724_rstandby_state.iprk, 0xa4080028); /* IPRK */
1390         __raw_writew(sh7724_rstandby_state.iprl, 0xa408002c); /* IPRL */
1391         __raw_writeb(sh7724_rstandby_state.imr0, 0xa4080080); /* IMR0 */
1392         __raw_writeb(sh7724_rstandby_state.imr1, 0xa4080084); /* IMR1 */
1393         __raw_writeb(sh7724_rstandby_state.imr2, 0xa4080088); /* IMR2 */
1394         __raw_writeb(sh7724_rstandby_state.imr3, 0xa408008c); /* IMR3 */
1395         __raw_writeb(sh7724_rstandby_state.imr4, 0xa4080090); /* IMR4 */
1396         __raw_writeb(sh7724_rstandby_state.imr5, 0xa4080094); /* IMR5 */
1397         __raw_writeb(sh7724_rstandby_state.imr6, 0xa4080098); /* IMR6 */
1398         __raw_writeb(sh7724_rstandby_state.imr7, 0xa408009c); /* IMR7 */
1399         __raw_writeb(sh7724_rstandby_state.imr8, 0xa40800a0); /* IMR8 */
1400         __raw_writeb(sh7724_rstandby_state.imr9, 0xa40800a4); /* IMR9 */
1401         __raw_writeb(sh7724_rstandby_state.imr10, 0xa40800a8); /* IMR10 */
1402         __raw_writeb(sh7724_rstandby_state.imr11, 0xa40800ac); /* IMR11 */
1403         __raw_writeb(sh7724_rstandby_state.imr12, 0xa40800b0); /* IMR12 */
1404
1405         /* RWDT */
1406         __raw_writew(sh7724_rstandby_state.rwtcnt, 0xa4520000); /* RWTCNT */
1407         __raw_writew(sh7724_rstandby_state.rwtcsr, 0xa4520004); /* RWTCSR */
1408
1409         /* CPG */
1410         __raw_writel(sh7724_rstandby_state.irdaclk, 0xa4150018); /* IRDACLKCR */
1411         __raw_writel(sh7724_rstandby_state.spuclk, 0xa415003c); /* SPUCLKCR */
1412
1413         return NOTIFY_DONE;
1414 }
1415
1416 static struct notifier_block sh7724_pre_sleep_notifier = {
1417         .notifier_call = sh7724_pre_sleep_notifier_call,
1418         .priority = SH_MOBILE_PRE(SH_MOBILE_SLEEP_CPU),
1419 };
1420
1421 static struct notifier_block sh7724_post_sleep_notifier = {
1422         .notifier_call = sh7724_post_sleep_notifier_call,
1423         .priority = SH_MOBILE_POST(SH_MOBILE_SLEEP_CPU),
1424 };
1425
1426 static int __init sh7724_sleep_setup(void)
1427 {
1428         atomic_notifier_chain_register(&sh_mobile_pre_sleep_notifier_list,
1429                                        &sh7724_pre_sleep_notifier);
1430
1431         atomic_notifier_chain_register(&sh_mobile_post_sleep_notifier_list,
1432                                        &sh7724_post_sleep_notifier);
1433         return 0;
1434 }
1435 arch_initcall(sh7724_sleep_setup);
1436