4 * Copyright (C) 2006 - 2008 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/serial_sci.h>
15 #include <linux/uio_driver.h>
16 #include <linux/usb/m66592.h>
17 #include <linux/sh_timer.h>
18 #include <asm/clock.h>
19 #include <asm/mmzone.h>
20 #include <cpu/sh7722.h>
22 static struct resource rtc_resources[] = {
25 .end = 0xa465fec0 + 0x58 - 1,
26 .flags = IORESOURCE_IO,
31 .flags = IORESOURCE_IRQ,
36 .flags = IORESOURCE_IRQ,
41 .flags = IORESOURCE_IRQ,
45 static struct platform_device rtc_device = {
48 .num_resources = ARRAY_SIZE(rtc_resources),
49 .resource = rtc_resources,
51 .hwblk_id = HWBLK_RTC,
55 static struct m66592_platdata usbf_platdata = {
59 static struct resource usbf_resources[] = {
64 .flags = IORESOURCE_MEM,
69 .flags = IORESOURCE_IRQ,
73 static struct platform_device usbf_device = {
75 .id = 0, /* "usbf0" clock */
78 .coherent_dma_mask = 0xffffffff,
79 .platform_data = &usbf_platdata,
81 .num_resources = ARRAY_SIZE(usbf_resources),
82 .resource = usbf_resources,
84 .hwblk_id = HWBLK_USBF,
88 static struct resource iic_resources[] = {
93 .flags = IORESOURCE_MEM,
98 .flags = IORESOURCE_IRQ,
102 static struct platform_device iic_device = {
103 .name = "i2c-sh_mobile",
104 .id = 0, /* "i2c0" clock */
105 .num_resources = ARRAY_SIZE(iic_resources),
106 .resource = iic_resources,
108 .hwblk_id = HWBLK_IIC,
112 static struct uio_info vpu_platform_data = {
118 static struct resource vpu_resources[] = {
123 .flags = IORESOURCE_MEM,
126 /* place holder for contiguous memory */
130 static struct platform_device vpu_device = {
131 .name = "uio_pdrv_genirq",
134 .platform_data = &vpu_platform_data,
136 .resource = vpu_resources,
137 .num_resources = ARRAY_SIZE(vpu_resources),
139 .hwblk_id = HWBLK_VPU,
143 static struct uio_info veu_platform_data = {
149 static struct resource veu_resources[] = {
154 .flags = IORESOURCE_MEM,
157 /* place holder for contiguous memory */
161 static struct platform_device veu_device = {
162 .name = "uio_pdrv_genirq",
165 .platform_data = &veu_platform_data,
167 .resource = veu_resources,
168 .num_resources = ARRAY_SIZE(veu_resources),
170 .hwblk_id = HWBLK_VEU,
174 static struct uio_info jpu_platform_data = {
180 static struct resource jpu_resources[] = {
185 .flags = IORESOURCE_MEM,
188 /* place holder for contiguous memory */
192 static struct platform_device jpu_device = {
193 .name = "uio_pdrv_genirq",
196 .platform_data = &jpu_platform_data,
198 .resource = jpu_resources,
199 .num_resources = ARRAY_SIZE(jpu_resources),
201 .hwblk_id = HWBLK_JPU,
205 static struct sh_timer_config cmt_platform_data = {
207 .channel_offset = 0x60,
210 .clockevent_rating = 125,
211 .clocksource_rating = 125,
214 static struct resource cmt_resources[] = {
219 .flags = IORESOURCE_MEM,
223 .flags = IORESOURCE_IRQ,
227 static struct platform_device cmt_device = {
231 .platform_data = &cmt_platform_data,
233 .resource = cmt_resources,
234 .num_resources = ARRAY_SIZE(cmt_resources),
236 .hwblk_id = HWBLK_CMT,
240 static struct sh_timer_config tmu0_platform_data = {
242 .channel_offset = 0x04,
245 .clockevent_rating = 200,
248 static struct resource tmu0_resources[] = {
253 .flags = IORESOURCE_MEM,
257 .flags = IORESOURCE_IRQ,
261 static struct platform_device tmu0_device = {
265 .platform_data = &tmu0_platform_data,
267 .resource = tmu0_resources,
268 .num_resources = ARRAY_SIZE(tmu0_resources),
270 .hwblk_id = HWBLK_TMU,
274 static struct sh_timer_config tmu1_platform_data = {
276 .channel_offset = 0x10,
279 .clocksource_rating = 200,
282 static struct resource tmu1_resources[] = {
287 .flags = IORESOURCE_MEM,
291 .flags = IORESOURCE_IRQ,
295 static struct platform_device tmu1_device = {
299 .platform_data = &tmu1_platform_data,
301 .resource = tmu1_resources,
302 .num_resources = ARRAY_SIZE(tmu1_resources),
304 .hwblk_id = HWBLK_TMU,
308 static struct sh_timer_config tmu2_platform_data = {
310 .channel_offset = 0x1c,
315 static struct resource tmu2_resources[] = {
320 .flags = IORESOURCE_MEM,
324 .flags = IORESOURCE_IRQ,
328 static struct platform_device tmu2_device = {
332 .platform_data = &tmu2_platform_data,
334 .resource = tmu2_resources,
335 .num_resources = ARRAY_SIZE(tmu2_resources),
337 .hwblk_id = HWBLK_TMU,
341 static struct plat_sci_port sci_platform_data[] = {
343 .mapbase = 0xffe00000,
344 .flags = UPF_BOOT_AUTOCONF,
346 .irqs = { 80, 80, 80, 80 },
350 .mapbase = 0xffe10000,
351 .flags = UPF_BOOT_AUTOCONF,
353 .irqs = { 81, 81, 81, 81 },
357 .mapbase = 0xffe20000,
358 .flags = UPF_BOOT_AUTOCONF,
360 .irqs = { 82, 82, 82, 82 },
368 static struct platform_device sci_device = {
372 .platform_data = sci_platform_data,
376 static struct platform_device *sh7722_devices[] __initdata = {
390 static int __init sh7722_devices_setup(void)
392 platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
393 platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
394 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
396 return platform_add_devices(sh7722_devices,
397 ARRAY_SIZE(sh7722_devices));
399 arch_initcall(sh7722_devices_setup);
401 static struct platform_device *sh7722_early_devices[] __initdata = {
408 void __init plat_early_device_setup(void)
410 early_platform_add_devices(sh7722_early_devices,
411 ARRAY_SIZE(sh7722_early_devices));
417 /* interrupt sources */
418 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
420 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
421 RTC_ATI, RTC_PRI, RTC_CUI,
422 DMAC0, DMAC1, DMAC2, DMAC3,
423 VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
425 USB_USBI0, USB_USBI1,
426 DMAC4, DMAC5, DMAC_DADERR,
428 SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
429 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
430 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
431 SDHI0, SDHI1, SDHI2, SDHI3,
432 CMT, TSIF, SIU, TWODG,
436 /* interrupt groups */
437 SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
440 static struct intc_vect vectors[] __initdata = {
441 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
442 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
443 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
444 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
445 INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720),
446 INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760),
447 INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0),
448 INTC_VECT(RTC_CUI, 0x7c0),
449 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
450 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
451 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
452 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
453 INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),
454 INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40),
455 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
456 INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
457 INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20),
458 INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80),
459 INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00),
460 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
461 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
462 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
463 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
464 INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0),
465 INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0),
466 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
467 INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
468 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
469 INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480),
470 INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
473 static struct intc_group groups[] __initdata = {
474 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
475 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
476 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
477 INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
478 INTC_GROUP(USB, USB_USBI0, USB_USBI1),
479 INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
480 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
481 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
482 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
483 INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
486 static struct intc_mask_reg mask_registers[] __initdata = {
487 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
489 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
490 { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
491 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
493 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
494 { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
495 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
496 { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
497 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
498 { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } },
499 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
500 { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } },
501 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
502 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
503 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
504 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
505 { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, TWODG, SIU } },
506 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
507 { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
508 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
510 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
511 { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },
512 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
513 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
516 static struct intc_prio_reg prio_registers[] __initdata = {
517 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
518 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
519 { 0xa4080008, 0, 16, 4, /* IPRC */ { } },
520 { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
521 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
522 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
523 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
524 { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
525 { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
526 { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
527 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
528 { 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
529 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
530 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
533 static struct intc_sense_reg sense_registers[] __initdata = {
534 { 0xa414001c, 16, 2, /* ICR1 */
535 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
538 static struct intc_mask_reg ack_registers[] __initdata = {
539 { 0xa4140024, 0, 8, /* INTREQ00 */
540 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
543 static DECLARE_INTC_DESC_ACK(intc_desc, "sh7722", vectors, groups,
544 mask_registers, prio_registers, sense_registers,
547 void __init plat_irq_setup(void)
549 register_intc_controller(&intc_desc);
552 void __init plat_mem_setup(void)
554 /* Register the URAM space as Node 1 */
555 setup_bootmem_node(1, 0x055f0000, 0x05610000);