4 * Copyright (C) 2006 - 2008 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/init.h>
12 #include <linux/platform_device.h>
13 #include <linux/serial.h>
14 #include <linux/serial_sci.h>
15 #include <linux/sh_timer.h>
16 #include <linux/uio_driver.h>
17 #include <linux/usb/m66592.h>
19 #include <asm/clock.h>
20 #include <asm/mmzone.h>
23 #include <cpu/dma-register.h>
24 #include <cpu/sh7722.h>
26 static const struct sh_dmae_slave_config sh7722_dmae_slaves[] = {
28 .slave_id = SHDMA_SLAVE_SCIF0_TX,
30 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
33 .slave_id = SHDMA_SLAVE_SCIF0_RX,
35 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
38 .slave_id = SHDMA_SLAVE_SCIF1_TX,
40 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
43 .slave_id = SHDMA_SLAVE_SCIF1_RX,
45 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
48 .slave_id = SHDMA_SLAVE_SCIF2_TX,
50 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
53 .slave_id = SHDMA_SLAVE_SCIF2_RX,
55 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
58 .slave_id = SHDMA_SLAVE_SIUA_TX,
60 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
63 .slave_id = SHDMA_SLAVE_SIUA_RX,
65 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
68 .slave_id = SHDMA_SLAVE_SIUB_TX,
70 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
73 .slave_id = SHDMA_SLAVE_SIUB_RX,
75 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
78 .slave_id = SHDMA_SLAVE_SDHI0_TX,
80 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
83 .slave_id = SHDMA_SLAVE_SDHI0_RX,
85 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
90 static const struct sh_dmae_channel sh7722_dmae_channels[] = {
118 static const unsigned int ts_shift[] = TS_SHIFT;
120 static struct sh_dmae_pdata dma_platform_data = {
121 .slave = sh7722_dmae_slaves,
122 .slave_num = ARRAY_SIZE(sh7722_dmae_slaves),
123 .channel = sh7722_dmae_channels,
124 .channel_num = ARRAY_SIZE(sh7722_dmae_channels),
125 .ts_low_shift = CHCR_TS_LOW_SHIFT,
126 .ts_low_mask = CHCR_TS_LOW_MASK,
127 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
128 .ts_high_mask = CHCR_TS_HIGH_MASK,
129 .ts_shift = ts_shift,
130 .ts_shift_num = ARRAY_SIZE(ts_shift),
131 .dmaor_init = DMAOR_INIT,
134 static struct resource sh7722_dmae_resources[] = {
136 /* Channel registers and DMAOR */
139 .flags = IORESOURCE_MEM,
145 .flags = IORESOURCE_MEM,
151 .flags = IORESOURCE_IRQ,
154 /* IRQ for channels 0-3 */
157 .flags = IORESOURCE_IRQ,
160 /* IRQ for channels 4-5 */
163 .flags = IORESOURCE_IRQ,
167 struct platform_device dma_device = {
168 .name = "sh-dma-engine",
170 .resource = sh7722_dmae_resources,
171 .num_resources = ARRAY_SIZE(sh7722_dmae_resources),
173 .platform_data = &dma_platform_data,
176 .hwblk_id = HWBLK_DMAC,
181 static struct plat_sci_port scif0_platform_data = {
182 .mapbase = 0xffe00000,
183 .flags = UPF_BOOT_AUTOCONF,
185 .irqs = { 80, 80, 80, 80 },
188 static struct platform_device scif0_device = {
192 .platform_data = &scif0_platform_data,
196 static struct plat_sci_port scif1_platform_data = {
197 .mapbase = 0xffe10000,
198 .flags = UPF_BOOT_AUTOCONF,
200 .irqs = { 81, 81, 81, 81 },
203 static struct platform_device scif1_device = {
207 .platform_data = &scif1_platform_data,
211 static struct plat_sci_port scif2_platform_data = {
212 .mapbase = 0xffe20000,
213 .flags = UPF_BOOT_AUTOCONF,
215 .irqs = { 82, 82, 82, 82 },
218 static struct platform_device scif2_device = {
222 .platform_data = &scif2_platform_data,
226 static struct resource rtc_resources[] = {
229 .end = 0xa465fec0 + 0x58 - 1,
230 .flags = IORESOURCE_IO,
235 .flags = IORESOURCE_IRQ,
240 .flags = IORESOURCE_IRQ,
245 .flags = IORESOURCE_IRQ,
249 static struct platform_device rtc_device = {
252 .num_resources = ARRAY_SIZE(rtc_resources),
253 .resource = rtc_resources,
255 .hwblk_id = HWBLK_RTC,
259 static struct m66592_platdata usbf_platdata = {
263 static struct resource usbf_resources[] = {
268 .flags = IORESOURCE_MEM,
273 .flags = IORESOURCE_IRQ,
277 static struct platform_device usbf_device = {
278 .name = "m66592_udc",
279 .id = 0, /* "usbf0" clock */
282 .coherent_dma_mask = 0xffffffff,
283 .platform_data = &usbf_platdata,
285 .num_resources = ARRAY_SIZE(usbf_resources),
286 .resource = usbf_resources,
288 .hwblk_id = HWBLK_USBF,
292 static struct resource iic_resources[] = {
297 .flags = IORESOURCE_MEM,
302 .flags = IORESOURCE_IRQ,
306 static struct platform_device iic_device = {
307 .name = "i2c-sh_mobile",
308 .id = 0, /* "i2c0" clock */
309 .num_resources = ARRAY_SIZE(iic_resources),
310 .resource = iic_resources,
312 .hwblk_id = HWBLK_IIC,
316 static struct uio_info vpu_platform_data = {
322 static struct resource vpu_resources[] = {
327 .flags = IORESOURCE_MEM,
330 /* place holder for contiguous memory */
334 static struct platform_device vpu_device = {
335 .name = "uio_pdrv_genirq",
338 .platform_data = &vpu_platform_data,
340 .resource = vpu_resources,
341 .num_resources = ARRAY_SIZE(vpu_resources),
343 .hwblk_id = HWBLK_VPU,
347 static struct uio_info veu_platform_data = {
353 static struct resource veu_resources[] = {
358 .flags = IORESOURCE_MEM,
361 /* place holder for contiguous memory */
365 static struct platform_device veu_device = {
366 .name = "uio_pdrv_genirq",
369 .platform_data = &veu_platform_data,
371 .resource = veu_resources,
372 .num_resources = ARRAY_SIZE(veu_resources),
374 .hwblk_id = HWBLK_VEU,
378 static struct uio_info jpu_platform_data = {
384 static struct resource jpu_resources[] = {
389 .flags = IORESOURCE_MEM,
392 /* place holder for contiguous memory */
396 static struct platform_device jpu_device = {
397 .name = "uio_pdrv_genirq",
400 .platform_data = &jpu_platform_data,
402 .resource = jpu_resources,
403 .num_resources = ARRAY_SIZE(jpu_resources),
405 .hwblk_id = HWBLK_JPU,
409 static struct sh_timer_config cmt_platform_data = {
410 .channel_offset = 0x60,
412 .clockevent_rating = 125,
413 .clocksource_rating = 125,
416 static struct resource cmt_resources[] = {
420 .flags = IORESOURCE_MEM,
424 .flags = IORESOURCE_IRQ,
428 static struct platform_device cmt_device = {
432 .platform_data = &cmt_platform_data,
434 .resource = cmt_resources,
435 .num_resources = ARRAY_SIZE(cmt_resources),
437 .hwblk_id = HWBLK_CMT,
441 static struct sh_timer_config tmu0_platform_data = {
442 .channel_offset = 0x04,
444 .clockevent_rating = 200,
447 static struct resource tmu0_resources[] = {
451 .flags = IORESOURCE_MEM,
455 .flags = IORESOURCE_IRQ,
459 static struct platform_device tmu0_device = {
463 .platform_data = &tmu0_platform_data,
465 .resource = tmu0_resources,
466 .num_resources = ARRAY_SIZE(tmu0_resources),
468 .hwblk_id = HWBLK_TMU,
472 static struct sh_timer_config tmu1_platform_data = {
473 .channel_offset = 0x10,
475 .clocksource_rating = 200,
478 static struct resource tmu1_resources[] = {
482 .flags = IORESOURCE_MEM,
486 .flags = IORESOURCE_IRQ,
490 static struct platform_device tmu1_device = {
494 .platform_data = &tmu1_platform_data,
496 .resource = tmu1_resources,
497 .num_resources = ARRAY_SIZE(tmu1_resources),
499 .hwblk_id = HWBLK_TMU,
503 static struct sh_timer_config tmu2_platform_data = {
504 .channel_offset = 0x1c,
508 static struct resource tmu2_resources[] = {
512 .flags = IORESOURCE_MEM,
516 .flags = IORESOURCE_IRQ,
520 static struct platform_device tmu2_device = {
524 .platform_data = &tmu2_platform_data,
526 .resource = tmu2_resources,
527 .num_resources = ARRAY_SIZE(tmu2_resources),
529 .hwblk_id = HWBLK_TMU,
533 static struct siu_platform siu_platform_data = {
534 .dma_dev = &dma_device.dev,
535 .dma_slave_tx_a = SHDMA_SLAVE_SIUA_TX,
536 .dma_slave_rx_a = SHDMA_SLAVE_SIUA_RX,
537 .dma_slave_tx_b = SHDMA_SLAVE_SIUB_TX,
538 .dma_slave_rx_b = SHDMA_SLAVE_SIUB_RX,
541 static struct resource siu_resources[] = {
545 .flags = IORESOURCE_MEM,
549 .flags = IORESOURCE_IRQ,
553 static struct platform_device siu_device = {
554 .name = "siu-pcm-audio",
557 .platform_data = &siu_platform_data,
559 .resource = siu_resources,
560 .num_resources = ARRAY_SIZE(siu_resources),
562 .hwblk_id = HWBLK_SIU,
566 static struct platform_device *sh7722_devices[] __initdata = {
584 static int __init sh7722_devices_setup(void)
586 platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
587 platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
588 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
590 return platform_add_devices(sh7722_devices,
591 ARRAY_SIZE(sh7722_devices));
593 arch_initcall(sh7722_devices_setup);
595 static struct platform_device *sh7722_early_devices[] __initdata = {
605 void __init plat_early_device_setup(void)
607 early_platform_add_devices(sh7722_early_devices,
608 ARRAY_SIZE(sh7722_early_devices));
616 /* interrupt sources */
617 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
619 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
620 RTC_ATI, RTC_PRI, RTC_CUI,
621 DMAC0, DMAC1, DMAC2, DMAC3,
622 VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
624 USB_USBI0, USB_USBI1,
625 DMAC4, DMAC5, DMAC_DADERR,
627 SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
628 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
629 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
630 CMT, TSIF, SIU, TWODG,
634 /* interrupt groups */
635 SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
638 static struct intc_vect vectors[] __initdata = {
639 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
640 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
641 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
642 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
643 INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720),
644 INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760),
645 INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0),
646 INTC_VECT(RTC_CUI, 0x7c0),
647 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
648 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
649 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
650 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
651 INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),
652 INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40),
653 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
654 INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
655 INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20),
656 INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80),
657 INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00),
658 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
659 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
660 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
661 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
662 INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
663 INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
664 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
665 INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
666 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
667 INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480),
668 INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
671 static struct intc_group groups[] __initdata = {
672 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
673 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
674 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
675 INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
676 INTC_GROUP(USB, USB_USBI0, USB_USBI1),
677 INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
678 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
679 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
680 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
683 static struct intc_mask_reg mask_registers[] __initdata = {
684 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
686 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
687 { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
688 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
690 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
691 { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
692 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
693 { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
694 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
695 { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } },
696 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
697 { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } },
698 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
699 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
700 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
701 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
702 { DISABLED, DISABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } },
703 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
704 { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
705 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
707 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
708 { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },
709 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
710 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
713 static struct intc_prio_reg prio_registers[] __initdata = {
714 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
715 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
716 { 0xa4080008, 0, 16, 4, /* IPRC */ { } },
717 { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
718 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
719 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
720 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
721 { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
722 { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
723 { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
724 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
725 { 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
726 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
727 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
730 static struct intc_sense_reg sense_registers[] __initdata = {
731 { 0xa414001c, 16, 2, /* ICR1 */
732 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
735 static struct intc_mask_reg ack_registers[] __initdata = {
736 { 0xa4140024, 0, 8, /* INTREQ00 */
737 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
740 static struct intc_desc intc_desc __initdata = {
742 .force_enable = ENABLED,
743 .force_disable = DISABLED,
744 .hw = INTC_HW_DESC(vectors, groups, mask_registers,
745 prio_registers, sense_registers, ack_registers),
748 void __init plat_irq_setup(void)
750 register_intc_controller(&intc_desc);
753 void __init plat_mem_setup(void)
755 /* Register the URAM space as Node 1 */
756 setup_bootmem_node(1, 0x055f0000, 0x05610000);