4 * Copyright (C) 2006 Paul Mundt
5 * Copyright (C) 2006 Jamie Lenehan
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
11 #include <linux/platform_device.h>
12 #include <linux/init.h>
13 #include <linux/serial.h>
15 #include <linux/sh_timer.h>
16 #include <linux/serial_sci.h>
18 static struct resource rtc_resources[] = {
21 .end = 0xffc80000 + 0x58 - 1,
22 .flags = IORESOURCE_IO,
25 /* Shared Period/Carry/Alarm IRQ */
27 .flags = IORESOURCE_IRQ,
31 static struct platform_device rtc_device = {
34 .num_resources = ARRAY_SIZE(rtc_resources),
35 .resource = rtc_resources,
38 static struct plat_sci_port scif0_platform_data = {
39 .mapbase = 0xffe00000,
40 .flags = UPF_BOOT_AUTOCONF,
42 .irqs = { 23, 23, 23, 0 },
45 static struct platform_device scif0_device = {
49 .platform_data = &scif0_platform_data,
53 static struct plat_sci_port scif1_platform_data = {
54 .mapbase = 0xffe80000,
55 .flags = UPF_BOOT_AUTOCONF,
57 .irqs = { 40, 40, 40, 40 },
60 static struct platform_device scif1_device = {
64 .platform_data = &scif1_platform_data,
68 static struct sh_timer_config tmu0_platform_data = {
70 .channel_offset = 0x04,
72 .clk = "peripheral_clk",
73 .clockevent_rating = 200,
76 static struct resource tmu0_resources[] = {
81 .flags = IORESOURCE_MEM,
85 .flags = IORESOURCE_IRQ,
89 static struct platform_device tmu0_device = {
93 .platform_data = &tmu0_platform_data,
95 .resource = tmu0_resources,
96 .num_resources = ARRAY_SIZE(tmu0_resources),
99 static struct sh_timer_config tmu1_platform_data = {
101 .channel_offset = 0x10,
103 .clk = "peripheral_clk",
104 .clocksource_rating = 200,
107 static struct resource tmu1_resources[] = {
112 .flags = IORESOURCE_MEM,
116 .flags = IORESOURCE_IRQ,
120 static struct platform_device tmu1_device = {
124 .platform_data = &tmu1_platform_data,
126 .resource = tmu1_resources,
127 .num_resources = ARRAY_SIZE(tmu1_resources),
130 static struct sh_timer_config tmu2_platform_data = {
132 .channel_offset = 0x1c,
134 .clk = "peripheral_clk",
137 static struct resource tmu2_resources[] = {
142 .flags = IORESOURCE_MEM,
146 .flags = IORESOURCE_IRQ,
150 static struct platform_device tmu2_device = {
154 .platform_data = &tmu2_platform_data,
156 .resource = tmu2_resources,
157 .num_resources = ARRAY_SIZE(tmu2_resources),
160 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
161 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
162 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
163 defined(CONFIG_CPU_SUBTYPE_SH7751R)
165 static struct sh_timer_config tmu3_platform_data = {
167 .channel_offset = 0x04,
169 .clk = "peripheral_clk",
172 static struct resource tmu3_resources[] = {
177 .flags = IORESOURCE_MEM,
181 .flags = IORESOURCE_IRQ,
185 static struct platform_device tmu3_device = {
189 .platform_data = &tmu3_platform_data,
191 .resource = tmu3_resources,
192 .num_resources = ARRAY_SIZE(tmu3_resources),
195 static struct sh_timer_config tmu4_platform_data = {
197 .channel_offset = 0x10,
199 .clk = "peripheral_clk",
202 static struct resource tmu4_resources[] = {
207 .flags = IORESOURCE_MEM,
211 .flags = IORESOURCE_IRQ,
215 static struct platform_device tmu4_device = {
219 .platform_data = &tmu4_platform_data,
221 .resource = tmu4_resources,
222 .num_resources = ARRAY_SIZE(tmu4_resources),
227 static struct platform_device *sh7750_devices[] __initdata = {
234 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
235 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
236 defined(CONFIG_CPU_SUBTYPE_SH7751R)
242 static int __init sh7750_devices_setup(void)
244 return platform_add_devices(sh7750_devices,
245 ARRAY_SIZE(sh7750_devices));
247 arch_initcall(sh7750_devices_setup);
249 static struct platform_device *sh7750_early_devices[] __initdata = {
255 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
256 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
257 defined(CONFIG_CPU_SUBTYPE_SH7751R)
263 void __init plat_early_device_setup(void)
265 early_platform_add_devices(sh7750_early_devices,
266 ARRAY_SIZE(sh7750_early_devices));
272 /* interrupt sources */
273 IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
275 PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
276 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
277 TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF,
279 /* interrupt groups */
283 static struct intc_vect vectors[] __initdata = {
284 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
285 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
286 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
287 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
288 INTC_VECT(RTC, 0x4c0),
289 INTC_VECT(SCI1, 0x4e0), INTC_VECT(SCI1, 0x500),
290 INTC_VECT(SCI1, 0x520), INTC_VECT(SCI1, 0x540),
291 INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
292 INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
293 INTC_VECT(WDT, 0x560),
294 INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
297 static struct intc_prio_reg prio_registers[] __initdata = {
298 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
299 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
300 { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
301 { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
302 { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
304 PCIC1, PCIC0_PCISERR } },
307 static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, NULL,
308 NULL, prio_registers, NULL);
310 /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
311 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
312 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
313 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
314 defined(CONFIG_CPU_SUBTYPE_SH7091)
315 static struct intc_vect vectors_dma4[] __initdata = {
316 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
317 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
318 INTC_VECT(DMAC, 0x6c0),
321 static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
323 NULL, prio_registers, NULL);
326 /* SH7750R and SH7751R both have 8-channel DMA controllers */
327 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
328 static struct intc_vect vectors_dma8[] __initdata = {
329 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
330 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
331 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
332 INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
333 INTC_VECT(DMAC, 0x6c0),
336 static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
338 NULL, prio_registers, NULL);
341 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
342 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
343 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
344 defined(CONFIG_CPU_SUBTYPE_SH7751R)
345 static struct intc_vect vectors_tmu34[] __initdata = {
346 INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
349 static struct intc_mask_reg mask_registers[] __initdata = {
350 { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
351 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
352 0, 0, 0, 0, 0, 0, TMU4, TMU3,
353 PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
354 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
355 PCIC1_PCIDMA3, PCIC0_PCISERR } },
358 static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34",
360 mask_registers, prio_registers, NULL);
363 /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
364 static struct intc_vect vectors_irlm[] __initdata = {
365 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
366 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
369 static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL,
370 NULL, prio_registers, NULL);
372 /* SH7751 and SH7751R both have PCI */
373 #if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
374 static struct intc_vect vectors_pci[] __initdata = {
375 INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
376 INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
377 INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
378 INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
381 static struct intc_group groups_pci[] __initdata = {
382 INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
383 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
386 static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci,
387 mask_registers, prio_registers, NULL);
390 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
391 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
392 defined(CONFIG_CPU_SUBTYPE_SH7091)
393 void __init plat_irq_setup(void)
396 * same vectors for SH7750, SH7750S and SH7091 except for IRLM,
399 register_intc_controller(&intc_desc);
400 register_intc_controller(&intc_desc_dma4);
404 #if defined(CONFIG_CPU_SUBTYPE_SH7750R)
405 void __init plat_irq_setup(void)
407 register_intc_controller(&intc_desc);
408 register_intc_controller(&intc_desc_dma8);
409 register_intc_controller(&intc_desc_tmu34);
413 #if defined(CONFIG_CPU_SUBTYPE_SH7751)
414 void __init plat_irq_setup(void)
416 register_intc_controller(&intc_desc);
417 register_intc_controller(&intc_desc_dma4);
418 register_intc_controller(&intc_desc_tmu34);
419 register_intc_controller(&intc_desc_pci);
423 #if defined(CONFIG_CPU_SUBTYPE_SH7751R)
424 void __init plat_irq_setup(void)
426 register_intc_controller(&intc_desc);
427 register_intc_controller(&intc_desc_dma8);
428 register_intc_controller(&intc_desc_tmu34);
429 register_intc_controller(&intc_desc_pci);
433 #define INTC_ICR 0xffd00000UL
434 #define INTC_ICR_IRLM (1<<7)
436 void __init plat_irq_setup_pins(int mode)
438 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091)
439 BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */
444 case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
445 ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
446 register_intc_controller(&intc_desc_irlm);