4 * Copyright (C) 2006 Paul Mundt
5 * Copyright (C) 2006 Jamie Lenehan
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
11 #include <linux/platform_device.h>
12 #include <linux/init.h>
13 #include <linux/serial.h>
15 #include <linux/sh_timer.h>
16 #include <linux/serial_sci.h>
18 static struct resource rtc_resources[] = {
21 .end = 0xffc80000 + 0x58 - 1,
22 .flags = IORESOURCE_IO,
25 /* Shared Period/Carry/Alarm IRQ */
27 .flags = IORESOURCE_IRQ,
31 static struct platform_device rtc_device = {
34 .num_resources = ARRAY_SIZE(rtc_resources),
35 .resource = rtc_resources,
38 static struct plat_sci_port scif0_platform_data = {
39 .mapbase = 0xffe00000,
40 .flags = UPF_BOOT_AUTOCONF,
42 .irqs = { 23, 23, 23, 0 },
45 static struct platform_device scif0_device = {
49 .platform_data = &scif0_platform_data,
53 static struct plat_sci_port scif1_platform_data = {
54 .mapbase = 0xffe80000,
55 .flags = UPF_BOOT_AUTOCONF,
57 .irqs = { 40, 40, 40, 40 },
60 static struct platform_device scif1_device = {
64 .platform_data = &scif1_platform_data,
68 static struct sh_timer_config tmu0_platform_data = {
69 .channel_offset = 0x04,
71 .clockevent_rating = 200,
74 static struct resource tmu0_resources[] = {
78 .flags = IORESOURCE_MEM,
82 .flags = IORESOURCE_IRQ,
86 static struct platform_device tmu0_device = {
90 .platform_data = &tmu0_platform_data,
92 .resource = tmu0_resources,
93 .num_resources = ARRAY_SIZE(tmu0_resources),
96 static struct sh_timer_config tmu1_platform_data = {
97 .channel_offset = 0x10,
99 .clocksource_rating = 200,
102 static struct resource tmu1_resources[] = {
106 .flags = IORESOURCE_MEM,
110 .flags = IORESOURCE_IRQ,
114 static struct platform_device tmu1_device = {
118 .platform_data = &tmu1_platform_data,
120 .resource = tmu1_resources,
121 .num_resources = ARRAY_SIZE(tmu1_resources),
124 static struct sh_timer_config tmu2_platform_data = {
125 .channel_offset = 0x1c,
129 static struct resource tmu2_resources[] = {
133 .flags = IORESOURCE_MEM,
137 .flags = IORESOURCE_IRQ,
141 static struct platform_device tmu2_device = {
145 .platform_data = &tmu2_platform_data,
147 .resource = tmu2_resources,
148 .num_resources = ARRAY_SIZE(tmu2_resources),
151 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
152 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
153 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
154 defined(CONFIG_CPU_SUBTYPE_SH7751R)
156 static struct sh_timer_config tmu3_platform_data = {
157 .channel_offset = 0x04,
161 static struct resource tmu3_resources[] = {
165 .flags = IORESOURCE_MEM,
169 .flags = IORESOURCE_IRQ,
173 static struct platform_device tmu3_device = {
177 .platform_data = &tmu3_platform_data,
179 .resource = tmu3_resources,
180 .num_resources = ARRAY_SIZE(tmu3_resources),
183 static struct sh_timer_config tmu4_platform_data = {
184 .channel_offset = 0x10,
188 static struct resource tmu4_resources[] = {
192 .flags = IORESOURCE_MEM,
196 .flags = IORESOURCE_IRQ,
200 static struct platform_device tmu4_device = {
204 .platform_data = &tmu4_platform_data,
206 .resource = tmu4_resources,
207 .num_resources = ARRAY_SIZE(tmu4_resources),
212 static struct platform_device *sh7750_devices[] __initdata = {
219 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
220 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
221 defined(CONFIG_CPU_SUBTYPE_SH7751R)
227 static int __init sh7750_devices_setup(void)
229 return platform_add_devices(sh7750_devices,
230 ARRAY_SIZE(sh7750_devices));
232 arch_initcall(sh7750_devices_setup);
234 static struct platform_device *sh7750_early_devices[] __initdata = {
240 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
241 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
242 defined(CONFIG_CPU_SUBTYPE_SH7751R)
248 void __init plat_early_device_setup(void)
250 early_platform_add_devices(sh7750_early_devices,
251 ARRAY_SIZE(sh7750_early_devices));
257 /* interrupt sources */
258 IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
260 PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
261 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
262 TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF,
264 /* interrupt groups */
268 static struct intc_vect vectors[] __initdata = {
269 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
270 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
271 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
272 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
273 INTC_VECT(RTC, 0x4c0),
274 INTC_VECT(SCI1, 0x4e0), INTC_VECT(SCI1, 0x500),
275 INTC_VECT(SCI1, 0x520), INTC_VECT(SCI1, 0x540),
276 INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
277 INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
278 INTC_VECT(WDT, 0x560),
279 INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
282 static struct intc_prio_reg prio_registers[] __initdata = {
283 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
284 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
285 { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
286 { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
287 { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
289 PCIC1, PCIC0_PCISERR } },
292 static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, NULL,
293 NULL, prio_registers, NULL);
295 /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
296 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
297 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
298 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
299 defined(CONFIG_CPU_SUBTYPE_SH7091)
300 static struct intc_vect vectors_dma4[] __initdata = {
301 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
302 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
303 INTC_VECT(DMAC, 0x6c0),
306 static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
308 NULL, prio_registers, NULL);
311 /* SH7750R and SH7751R both have 8-channel DMA controllers */
312 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
313 static struct intc_vect vectors_dma8[] __initdata = {
314 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
315 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
316 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
317 INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
318 INTC_VECT(DMAC, 0x6c0),
321 static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
323 NULL, prio_registers, NULL);
326 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
327 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
328 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
329 defined(CONFIG_CPU_SUBTYPE_SH7751R)
330 static struct intc_vect vectors_tmu34[] __initdata = {
331 INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
334 static struct intc_mask_reg mask_registers[] __initdata = {
335 { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
336 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
337 0, 0, 0, 0, 0, 0, TMU4, TMU3,
338 PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
339 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
340 PCIC1_PCIDMA3, PCIC0_PCISERR } },
343 static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34",
345 mask_registers, prio_registers, NULL);
348 /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
349 static struct intc_vect vectors_irlm[] __initdata = {
350 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
351 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
354 static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL,
355 NULL, prio_registers, NULL);
357 /* SH7751 and SH7751R both have PCI */
358 #if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
359 static struct intc_vect vectors_pci[] __initdata = {
360 INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
361 INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
362 INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
363 INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
366 static struct intc_group groups_pci[] __initdata = {
367 INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
368 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
371 static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci,
372 mask_registers, prio_registers, NULL);
375 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
376 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
377 defined(CONFIG_CPU_SUBTYPE_SH7091)
378 void __init plat_irq_setup(void)
381 * same vectors for SH7750, SH7750S and SH7091 except for IRLM,
384 register_intc_controller(&intc_desc);
385 register_intc_controller(&intc_desc_dma4);
389 #if defined(CONFIG_CPU_SUBTYPE_SH7750R)
390 void __init plat_irq_setup(void)
392 register_intc_controller(&intc_desc);
393 register_intc_controller(&intc_desc_dma8);
394 register_intc_controller(&intc_desc_tmu34);
398 #if defined(CONFIG_CPU_SUBTYPE_SH7751)
399 void __init plat_irq_setup(void)
401 register_intc_controller(&intc_desc);
402 register_intc_controller(&intc_desc_dma4);
403 register_intc_controller(&intc_desc_tmu34);
404 register_intc_controller(&intc_desc_pci);
408 #if defined(CONFIG_CPU_SUBTYPE_SH7751R)
409 void __init plat_irq_setup(void)
411 register_intc_controller(&intc_desc);
412 register_intc_controller(&intc_desc_dma8);
413 register_intc_controller(&intc_desc_tmu34);
414 register_intc_controller(&intc_desc_pci);
418 #define INTC_ICR 0xffd00000UL
419 #define INTC_ICR_IRLM (1<<7)
421 void __init plat_irq_setup_pins(int mode)
423 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091)
424 BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */
429 case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
430 __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
431 register_intc_controller(&intc_desc_irlm);