2 * Setup code for SH7720, SH7721.
4 * Copyright (C) 2007 Markus Brunner, Mark Jonas
5 * Copyright (C) 2009 Paul Mundt
7 * Based on arch/sh/kernel/cpu/sh4/setup-sh7750.c:
9 * Copyright (C) 2006 Paul Mundt
10 * Copyright (C) 2006 Jamie Lenehan
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file "COPYING" in the main directory of this archive
16 #include <linux/platform_device.h>
17 #include <linux/init.h>
18 #include <linux/serial.h>
20 #include <linux/serial_sci.h>
21 #include <linux/sh_timer.h>
24 static struct resource rtc_resources[] = {
27 .end = 0xa413fec0 + 0x28 - 1,
28 .flags = IORESOURCE_IO,
31 /* Shared Period/Carry/Alarm IRQ */
33 .flags = IORESOURCE_IRQ,
37 static struct sh_rtc_platform_info rtc_info = {
38 .capabilities = RTC_CAP_4_DIGIT_YEAR,
41 static struct platform_device rtc_device = {
44 .num_resources = ARRAY_SIZE(rtc_resources),
45 .resource = rtc_resources,
47 .platform_data = &rtc_info,
51 static struct plat_sci_port scif0_platform_data = {
52 .mapbase = 0xa4430000,
53 .flags = UPF_BOOT_AUTOCONF,
54 .scscr = SCSCR_RE | SCSCR_TE,
55 .scbrr_algo_id = SCBRR_ALGO_4,
57 .irqs = { 80, 80, 80, 80 },
60 static struct platform_device scif0_device = {
64 .platform_data = &scif0_platform_data,
68 static struct plat_sci_port scif1_platform_data = {
69 .mapbase = 0xa4438000,
70 .flags = UPF_BOOT_AUTOCONF,
71 .scscr = SCSCR_RE | SCSCR_TE,
72 .scbrr_algo_id = SCBRR_ALGO_4,
74 .irqs = { 81, 81, 81, 81 },
77 static struct platform_device scif1_device = {
81 .platform_data = &scif1_platform_data,
85 static struct resource usb_ohci_resources[] = {
89 .flags = IORESOURCE_MEM,
94 .flags = IORESOURCE_IRQ,
98 static u64 usb_ohci_dma_mask = 0xffffffffUL;
99 static struct platform_device usb_ohci_device = {
103 .dma_mask = &usb_ohci_dma_mask,
104 .coherent_dma_mask = 0xffffffff,
106 .num_resources = ARRAY_SIZE(usb_ohci_resources),
107 .resource = usb_ohci_resources,
110 static struct resource usbf_resources[] = {
115 .flags = IORESOURCE_MEM,
121 .flags = IORESOURCE_IRQ,
125 static struct platform_device usbf_device = {
130 .coherent_dma_mask = 0xffffffff,
132 .num_resources = ARRAY_SIZE(usbf_resources),
133 .resource = usbf_resources,
136 static struct sh_timer_config cmt0_platform_data = {
137 .channel_offset = 0x10,
139 .clockevent_rating = 125,
140 .clocksource_rating = 125,
143 static struct resource cmt0_resources[] = {
147 .flags = IORESOURCE_MEM,
151 .flags = IORESOURCE_IRQ,
155 static struct platform_device cmt0_device = {
159 .platform_data = &cmt0_platform_data,
161 .resource = cmt0_resources,
162 .num_resources = ARRAY_SIZE(cmt0_resources),
165 static struct sh_timer_config cmt1_platform_data = {
166 .channel_offset = 0x20,
170 static struct resource cmt1_resources[] = {
174 .flags = IORESOURCE_MEM,
178 .flags = IORESOURCE_IRQ,
182 static struct platform_device cmt1_device = {
186 .platform_data = &cmt1_platform_data,
188 .resource = cmt1_resources,
189 .num_resources = ARRAY_SIZE(cmt1_resources),
192 static struct sh_timer_config cmt2_platform_data = {
193 .channel_offset = 0x30,
197 static struct resource cmt2_resources[] = {
201 .flags = IORESOURCE_MEM,
205 .flags = IORESOURCE_IRQ,
209 static struct platform_device cmt2_device = {
213 .platform_data = &cmt2_platform_data,
215 .resource = cmt2_resources,
216 .num_resources = ARRAY_SIZE(cmt2_resources),
219 static struct sh_timer_config cmt3_platform_data = {
220 .channel_offset = 0x40,
224 static struct resource cmt3_resources[] = {
228 .flags = IORESOURCE_MEM,
232 .flags = IORESOURCE_IRQ,
236 static struct platform_device cmt3_device = {
240 .platform_data = &cmt3_platform_data,
242 .resource = cmt3_resources,
243 .num_resources = ARRAY_SIZE(cmt3_resources),
246 static struct sh_timer_config cmt4_platform_data = {
247 .channel_offset = 0x50,
251 static struct resource cmt4_resources[] = {
255 .flags = IORESOURCE_MEM,
259 .flags = IORESOURCE_IRQ,
263 static struct platform_device cmt4_device = {
267 .platform_data = &cmt4_platform_data,
269 .resource = cmt4_resources,
270 .num_resources = ARRAY_SIZE(cmt4_resources),
273 static struct sh_timer_config tmu0_platform_data = {
274 .channel_offset = 0x02,
276 .clockevent_rating = 200,
279 static struct resource tmu0_resources[] = {
283 .flags = IORESOURCE_MEM,
287 .flags = IORESOURCE_IRQ,
291 static struct platform_device tmu0_device = {
295 .platform_data = &tmu0_platform_data,
297 .resource = tmu0_resources,
298 .num_resources = ARRAY_SIZE(tmu0_resources),
301 static struct sh_timer_config tmu1_platform_data = {
302 .channel_offset = 0xe,
304 .clocksource_rating = 200,
307 static struct resource tmu1_resources[] = {
311 .flags = IORESOURCE_MEM,
315 .flags = IORESOURCE_IRQ,
319 static struct platform_device tmu1_device = {
323 .platform_data = &tmu1_platform_data,
325 .resource = tmu1_resources,
326 .num_resources = ARRAY_SIZE(tmu1_resources),
329 static struct sh_timer_config tmu2_platform_data = {
330 .channel_offset = 0x1a,
334 static struct resource tmu2_resources[] = {
338 .flags = IORESOURCE_MEM,
342 .flags = IORESOURCE_IRQ,
346 static struct platform_device tmu2_device = {
350 .platform_data = &tmu2_platform_data,
352 .resource = tmu2_resources,
353 .num_resources = ARRAY_SIZE(tmu2_resources),
356 static struct platform_device *sh7720_devices[] __initdata = {
372 static int __init sh7720_devices_setup(void)
374 return platform_add_devices(sh7720_devices,
375 ARRAY_SIZE(sh7720_devices));
377 arch_initcall(sh7720_devices_setup);
379 static struct platform_device *sh7720_early_devices[] __initdata = {
392 void __init plat_early_device_setup(void)
394 early_platform_add_devices(sh7720_early_devices,
395 ARRAY_SIZE(sh7720_early_devices));
401 /* interrupt sources */
402 TMU0, TMU1, TMU2, RTC,
404 IRQ0, IRQ1, IRQ2, IRQ3,
405 USBF_SPD, TMU_SUNI, IRQ5, IRQ4,
407 ADC, DMAC2, USBFI, CMT,
409 PINT07, PINT815, TPU, IIC,
410 SIOF0, SIOF1, MMC, PCC,
415 static struct intc_vect vectors[] __initdata = {
416 /* IRQ0->5 are handled in setup-sh3.c */
417 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
418 INTC_VECT(TMU2, 0x440), INTC_VECT(RTC, 0x480),
419 INTC_VECT(RTC, 0x4a0), INTC_VECT(RTC, 0x4c0),
420 INTC_VECT(SIM, 0x4e0), INTC_VECT(SIM, 0x500),
421 INTC_VECT(SIM, 0x520), INTC_VECT(SIM, 0x540),
422 INTC_VECT(WDT, 0x560), INTC_VECT(REF_RCMI, 0x580),
423 /* H_UDI cannot be masked */ INTC_VECT(TMU_SUNI, 0x6c0),
424 INTC_VECT(USBF_SPD, 0x6e0), INTC_VECT(DMAC1, 0x800),
425 INTC_VECT(DMAC1, 0x820), INTC_VECT(DMAC1, 0x840),
426 INTC_VECT(DMAC1, 0x860), INTC_VECT(LCDC, 0x900),
427 #if defined(CONFIG_CPU_SUBTYPE_SH7720)
428 INTC_VECT(SSL, 0x980),
430 INTC_VECT(USBFI, 0xa20), INTC_VECT(USBFI, 0xa40),
431 INTC_VECT(USBHI, 0xa60),
432 INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0),
433 INTC_VECT(ADC, 0xbe0), INTC_VECT(SCIF0, 0xc00),
434 INTC_VECT(SCIF1, 0xc20), INTC_VECT(PINT07, 0xc80),
435 INTC_VECT(PINT815, 0xca0), INTC_VECT(SIOF0, 0xd00),
436 INTC_VECT(SIOF1, 0xd20), INTC_VECT(TPU, 0xd80),
437 INTC_VECT(TPU, 0xda0), INTC_VECT(TPU, 0xdc0),
438 INTC_VECT(TPU, 0xde0), INTC_VECT(IIC, 0xe00),
439 INTC_VECT(MMC, 0xe80), INTC_VECT(MMC, 0xea0),
440 INTC_VECT(MMC, 0xec0), INTC_VECT(MMC, 0xee0),
441 INTC_VECT(CMT, 0xf00), INTC_VECT(PCC, 0xf60),
442 INTC_VECT(AFEIF, 0xfe0),
445 static struct intc_prio_reg prio_registers[] __initdata = {
446 { 0xA414FEE2UL, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
447 { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } },
448 { 0xA4140016UL, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
449 { 0xA4140018UL, 0, 16, 4, /* IPRD */ { USBF_SPD, TMU_SUNI, IRQ5, IRQ4 } },
450 { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } },
451 { 0xA4080000UL, 0, 16, 4, /* IPRF */ { ADC, DMAC2, USBFI, CMT } },
452 { 0xA4080002UL, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, 0, 0 } },
453 { 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } },
454 { 0xA4080006UL, 0, 16, 4, /* IPRI */ { SIOF0, SIOF1, MMC, PCC } },
455 { 0xA4080008UL, 0, 16, 4, /* IPRJ */ { 0, USBHI, 0, AFEIF } },
458 static DECLARE_INTC_DESC(intc_desc, "sh7720", vectors, NULL,
459 NULL, prio_registers, NULL);
461 void __init plat_irq_setup(void)
463 register_intc_controller(&intc_desc);
464 plat_irq_setup_sh3();