4 * Copyright (C) 2006 Yoshinori Sato
5 * Copyright (C) 2009 Paul Mundt
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
11 #include <linux/platform_device.h>
12 #include <linux/init.h>
13 #include <linux/serial.h>
14 #include <linux/serial_sci.h>
15 #include <linux/sh_timer.h>
21 /* interrupt sources */
22 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
23 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
26 DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
28 MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
29 MTU3_ABCD, MTU4_ABCD, MTU5, POE2_12, MTU3S_ABCD, MTU4S_ABCD, MTU5S,
34 MTU2_TCI3V, MTU2_TCI4V, MTU2S_TCI3V, MTU2S_TCI4V,
38 SCIF0, SCIF1, SCIF2, SCIF3,
40 /* interrupt groups */
44 static struct intc_vect vectors[] __initdata = {
45 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
46 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
47 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
48 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
49 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
50 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
51 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
52 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
53 INTC_IRQ(ADC_ADI0, 92), INTC_IRQ(ADC_ADI1, 96),
54 INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
55 INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
56 INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
57 INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
58 INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
59 INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
60 INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
61 INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
62 INTC_IRQ(CMT0, 140), INTC_IRQ(CMT1, 144),
63 INTC_IRQ(BSC, 148), INTC_IRQ(WDT, 152),
64 INTC_IRQ(MTU0_ABCD, 156), INTC_IRQ(MTU0_ABCD, 157),
65 INTC_IRQ(MTU0_ABCD, 158), INTC_IRQ(MTU0_ABCD, 159),
66 INTC_IRQ(MTU0_VEF, 160), INTC_IRQ(MTU0_VEF, 161),
67 INTC_IRQ(MTU0_VEF, 162),
68 INTC_IRQ(MTU1_AB, 164), INTC_IRQ(MTU1_AB, 165),
69 INTC_IRQ(MTU1_VU, 168), INTC_IRQ(MTU1_VU, 169),
70 INTC_IRQ(MTU2_AB, 172), INTC_IRQ(MTU2_AB, 173),
71 INTC_IRQ(MTU2_VU, 176), INTC_IRQ(MTU2_VU, 177),
72 INTC_IRQ(MTU3_ABCD, 180), INTC_IRQ(MTU3_ABCD, 181),
73 INTC_IRQ(MTU3_ABCD, 182), INTC_IRQ(MTU3_ABCD, 183),
74 INTC_IRQ(MTU2_TCI3V, 184),
75 INTC_IRQ(MTU4_ABCD, 188), INTC_IRQ(MTU4_ABCD, 189),
76 INTC_IRQ(MTU4_ABCD, 190), INTC_IRQ(MTU4_ABCD, 191),
77 INTC_IRQ(MTU2_TCI4V, 192),
78 INTC_IRQ(MTU5, 196), INTC_IRQ(MTU5, 197),
80 INTC_IRQ(POE2_12, 200), INTC_IRQ(POE2_12, 201),
81 INTC_IRQ(MTU3S_ABCD, 204), INTC_IRQ(MTU3S_ABCD, 205),
82 INTC_IRQ(MTU3S_ABCD, 206), INTC_IRQ(MTU3S_ABCD, 207),
83 INTC_IRQ(MTU2S_TCI3V, 208),
84 INTC_IRQ(MTU4S_ABCD, 212), INTC_IRQ(MTU4S_ABCD, 213),
85 INTC_IRQ(MTU4S_ABCD, 214), INTC_IRQ(MTU4S_ABCD, 215),
86 INTC_IRQ(MTU2S_TCI4V, 216),
87 INTC_IRQ(MTU5S, 220), INTC_IRQ(MTU5S, 221),
89 INTC_IRQ(POE2_OEI3, 224),
90 INTC_IRQ(IIC3, 228), INTC_IRQ(IIC3, 229),
91 INTC_IRQ(IIC3, 230), INTC_IRQ(IIC3, 231),
93 INTC_IRQ(SCIF0, 240), INTC_IRQ(SCIF0, 241),
94 INTC_IRQ(SCIF0, 242), INTC_IRQ(SCIF0, 243),
95 INTC_IRQ(SCIF1, 244), INTC_IRQ(SCIF1, 245),
96 INTC_IRQ(SCIF1, 246), INTC_IRQ(SCIF1, 247),
97 INTC_IRQ(SCIF2, 248), INTC_IRQ(SCIF2, 249),
98 INTC_IRQ(SCIF2, 250), INTC_IRQ(SCIF2, 251),
99 INTC_IRQ(SCIF3, 252), INTC_IRQ(SCIF3, 253),
100 INTC_IRQ(SCIF3, 254), INTC_IRQ(SCIF3, 255),
103 static struct intc_group groups[] __initdata = {
104 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
105 PINT4, PINT5, PINT6, PINT7),
108 static struct intc_prio_reg prio_registers[] __initdata = {
109 { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
110 { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
111 { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI0, ADC_ADI1 } },
112 { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
113 { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
114 { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { CMT0, CMT1, BSC, WDT } },
115 { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { MTU0_ABCD, MTU0_VEF,
116 MTU1_AB, MTU1_VU } },
117 { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU2_AB, MTU2_VU,
118 MTU3_ABCD, MTU2_TCI3V } },
119 { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU4_ABCD, MTU2_TCI4V,
121 { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { MTU3S_ABCD, MTU2S_TCI3V,
122 MTU4S_ABCD, MTU2S_TCI4V } },
123 { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU5S, POE2_OEI3, IIC3, 0 } },
124 { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF0, SCIF1, SCIF2, SCIF3 } },
127 static struct intc_mask_reg mask_registers[] __initdata = {
128 { 0xfffe0808, 0, 16, /* PINTER */
129 { 0, 0, 0, 0, 0, 0, 0, 0,
130 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
133 static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups,
134 mask_registers, prio_registers, NULL);
136 static struct plat_sci_port sci_platform_data[] = {
138 .mapbase = 0xfffe8000,
139 .flags = UPF_BOOT_AUTOCONF,
140 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
141 .scbrr_algo_id = SCBRR_ALGO_2,
143 .irqs = { 240, 240, 240, 240 },
145 .mapbase = 0xfffe8800,
146 .flags = UPF_BOOT_AUTOCONF,
147 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
148 .scbrr_algo_id = SCBRR_ALGO_2,
150 .irqs = { 244, 244, 244, 244 },
152 .mapbase = 0xfffe9000,
153 .flags = UPF_BOOT_AUTOCONF,
154 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
155 .scbrr_algo_id = SCBRR_ALGO_2,
157 .irqs = { 248, 248, 248, 248 },
159 .mapbase = 0xfffe9800,
160 .flags = UPF_BOOT_AUTOCONF,
161 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
162 .scbrr_algo_id = SCBRR_ALGO_2,
164 .irqs = { 252, 252, 252, 252 },
170 static struct platform_device sci_device = {
174 .platform_data = sci_platform_data,
178 static struct sh_timer_config cmt0_platform_data = {
180 .channel_offset = 0x02,
182 .clk = "peripheral_clk",
183 .clockevent_rating = 125,
184 .clocksource_rating = 0, /* disabled due to code generation issues */
187 static struct resource cmt0_resources[] = {
192 .flags = IORESOURCE_MEM,
196 .flags = IORESOURCE_IRQ,
200 static struct platform_device cmt0_device = {
204 .platform_data = &cmt0_platform_data,
206 .resource = cmt0_resources,
207 .num_resources = ARRAY_SIZE(cmt0_resources),
210 static struct sh_timer_config cmt1_platform_data = {
212 .channel_offset = 0x08,
214 .clk = "peripheral_clk",
215 .clockevent_rating = 125,
216 .clocksource_rating = 0, /* disabled due to code generation issues */
219 static struct resource cmt1_resources[] = {
224 .flags = IORESOURCE_MEM,
228 .flags = IORESOURCE_IRQ,
232 static struct platform_device cmt1_device = {
236 .platform_data = &cmt1_platform_data,
238 .resource = cmt1_resources,
239 .num_resources = ARRAY_SIZE(cmt1_resources),
242 static struct sh_timer_config mtu2_0_platform_data = {
244 .channel_offset = -0x80,
246 .clk = "peripheral_clk",
247 .clockevent_rating = 200,
250 static struct resource mtu2_0_resources[] = {
255 .flags = IORESOURCE_MEM,
259 .flags = IORESOURCE_IRQ,
263 static struct platform_device mtu2_0_device = {
267 .platform_data = &mtu2_0_platform_data,
269 .resource = mtu2_0_resources,
270 .num_resources = ARRAY_SIZE(mtu2_0_resources),
273 static struct sh_timer_config mtu2_1_platform_data = {
275 .channel_offset = -0x100,
277 .clk = "peripheral_clk",
278 .clockevent_rating = 200,
281 static struct resource mtu2_1_resources[] = {
286 .flags = IORESOURCE_MEM,
290 .flags = IORESOURCE_IRQ,
294 static struct platform_device mtu2_1_device = {
298 .platform_data = &mtu2_1_platform_data,
300 .resource = mtu2_1_resources,
301 .num_resources = ARRAY_SIZE(mtu2_1_resources),
304 static struct sh_timer_config mtu2_2_platform_data = {
306 .channel_offset = 0x80,
308 .clk = "peripheral_clk",
309 .clockevent_rating = 200,
312 static struct resource mtu2_2_resources[] = {
317 .flags = IORESOURCE_MEM,
321 .flags = IORESOURCE_IRQ,
325 static struct platform_device mtu2_2_device = {
329 .platform_data = &mtu2_2_platform_data,
331 .resource = mtu2_2_resources,
332 .num_resources = ARRAY_SIZE(mtu2_2_resources),
335 static struct platform_device *sh7206_devices[] __initdata = {
344 static int __init sh7206_devices_setup(void)
346 return platform_add_devices(sh7206_devices,
347 ARRAY_SIZE(sh7206_devices));
349 __initcall(sh7206_devices_setup);
351 void __init plat_irq_setup(void)
353 register_intc_controller(&intc_desc);
356 static struct platform_device *sh7206_early_devices[] __initdata = {
364 #define STBCR3 0xfffe0408
365 #define STBCR4 0xfffe040c
367 void __init plat_early_device_setup(void)
369 /* enable CMT clock */
370 __raw_writeb(__raw_readb(STBCR4) & ~0x04, STBCR4);
372 /* enable MTU2 clock */
373 __raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
375 early_platform_add_devices(sh7206_early_devices,
376 ARRAY_SIZE(sh7206_early_devices));