1 #ifndef __ASM_SH_HITACHI_SE7343_H
2 #define __ASM_SH_HITACHI_SE7343_H
5 * include/asm-sh/se/se7343.h
7 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
9 * SH-Mobile SolutionEngine 7343 support
12 /* Box specific addresses. */
15 #define PA_ROM 0x00000000 /* EPROM */
16 #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */
17 #define PA_FROM 0x00400000 /* Flash ROM */
18 #define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */
19 #define PA_SRAM 0x00800000 /* SRAM */
20 #define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */
22 #define PA_EXT1 0x04000000
23 #define PA_EXT1_SIZE 0x04000000
25 #define PA_EXT2 0x08000000
26 #define PA_EXT2_SIZE 0x04000000
28 #define PA_SDRAM 0x0c000000
29 #define PA_SDRAM_SIZE 0x04000000
31 #define PA_PCIC 0x10000000 /* MR-SHPC-01 PCMCIA */
32 #define PA_MRSHPC 0xb03fffe0 /* MR-SHPC-01 PCMCIA controller */
33 #define PA_MRSHPC_MW1 0xb0400000 /* MR-SHPC-01 memory window base */
34 #define PA_MRSHPC_MW2 0xb0500000 /* MR-SHPC-01 attribute window base */
35 #define PA_MRSHPC_IO 0xb0600000 /* MR-SHPC-01 I/O window base */
36 #define MRSHPC_OPTION (PA_MRSHPC + 6)
37 #define MRSHPC_CSR (PA_MRSHPC + 8)
38 #define MRSHPC_ISR (PA_MRSHPC + 10)
39 #define MRSHPC_ICR (PA_MRSHPC + 12)
40 #define MRSHPC_CPWCR (PA_MRSHPC + 14)
41 #define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
42 #define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
43 #define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
44 #define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
45 #define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
46 #define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
47 #define MRSHPC_CDCR (PA_MRSHPC + 28)
48 #define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
49 #define PA_LED 0xb0C00000 /* LED */
51 #define PA_DIPSW 0xb0900000 /* Dip switch 31 */
53 #define PA_EXT5 0x14000000
54 #define PA_EXT5_SIZE 0x04000000
56 #define PA_LCD1 0xb8000000
57 #define PA_LCD2 0xb8800000
59 #define PORT_PACR 0xA4050100
60 #define PORT_PBCR 0xA4050102
61 #define PORT_PCCR 0xA4050104
62 #define PORT_PDCR 0xA4050106
63 #define PORT_PECR 0xA4050108
64 #define PORT_PFCR 0xA405010A
65 #define PORT_PGCR 0xA405010C
66 #define PORT_PHCR 0xA405010E
67 #define PORT_PJCR 0xA4050110
68 #define PORT_PKCR 0xA4050112
69 #define PORT_PLCR 0xA4050114
70 #define PORT_PMCR 0xA4050116
71 #define PORT_PNCR 0xA4050118
72 #define PORT_PQCR 0xA405011A
73 #define PORT_PRCR 0xA405011C
74 #define PORT_PSCR 0xA405011E
75 #define PORT_PTCR 0xA4050140
76 #define PORT_PUCR 0xA4050142
77 #define PORT_PVCR 0xA4050144
78 #define PORT_PWCR 0xA4050146
79 #define PORT_PYCR 0xA4050148
80 #define PORT_PZCR 0xA405014A
82 #define PORT_PSELA 0xA405014C
83 #define PORT_PSELB 0xA405014E
84 #define PORT_PSELC 0xA4050150
85 #define PORT_PSELD 0xA4050152
86 #define PORT_PSELE 0xA4050154
88 #define PORT_HIZCRA 0xA4050156
89 #define PORT_HIZCRB 0xA4050158
90 #define PORT_HIZCRC 0xA405015C
92 #define PORT_DRVCR 0xA4050180
94 #define PORT_PADR 0xA4050120
95 #define PORT_PBDR 0xA4050122
96 #define PORT_PCDR 0xA4050124
97 #define PORT_PDDR 0xA4050126
98 #define PORT_PEDR 0xA4050128
99 #define PORT_PFDR 0xA405012A
100 #define PORT_PGDR 0xA405012C
101 #define PORT_PHDR 0xA405012E
102 #define PORT_PJDR 0xA4050130
103 #define PORT_PKDR 0xA4050132
104 #define PORT_PLDR 0xA4050134
105 #define PORT_PMDR 0xA4050136
106 #define PORT_PNDR 0xA4050138
107 #define PORT_PQDR 0xA405013A
108 #define PORT_PRDR 0xA405013C
109 #define PORT_PTDR 0xA4050160
110 #define PORT_PUDR 0xA4050162
111 #define PORT_PVDR 0xA4050164
112 #define PORT_PWDR 0xA4050166
113 #define PORT_PYDR 0xA4050168
115 #define FPGA_IN 0xb1400000
116 #define FPGA_OUT 0xb1400002
123 #define SE7343_FPGA_IRQ_MRSHPC0 0
124 #define SE7343_FPGA_IRQ_MRSHPC1 1
125 #define SE7343_FPGA_IRQ_MRSHPC2 2
126 #define SE7343_FPGA_IRQ_MRSHPC3 3
127 #define SE7343_FPGA_IRQ_SMC 6 /* EXT_IRQ2 */
128 #define SE7343_FPGA_IRQ_USB 8
129 #define SE7343_FPGA_IRQ_UARTA 10
130 #define SE7343_FPGA_IRQ_UARTB 11
132 #define SE7343_FPGA_IRQ_NR 12
136 /* arch/sh/boards/se/7343/irq.c */
137 extern struct irq_domain *se7343_irq_domain;
139 void init_7343se_IRQ(void);
141 #endif /* __ASM_SH_HITACHI_SE7343_H */