5 * read{b,w,l,q}/write{b,w,l,q} are for PCI,
6 * while in{b,w,l}/out{b,w,l} are for ISA
8 * In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p
9 * and 'string' versions: ins{b,w,l}/outs{b,w,l}
11 * While read{b,w,l,q} and write{b,w,l,q} contain memory barriers
12 * automatically, there are also __raw versions, which do not.
14 * Historically, we have also had ctrl_in{b,w,l,q}/ctrl_out{b,w,l,q} for
15 * SuperH specific I/O (raw I/O to on-chip CPU peripherals). In practice
16 * these have the same semantics as the __raw variants, and as such, all
17 * new code should be using the __raw versions.
19 * All ISA I/O routines are wrapped through the machine vector. If a
20 * board does not provide overrides, a generic set that are copied in
21 * from the default machine vector are used instead. These are largely
22 * for old compat code for I/O offseting to SuperIOs, all of which are
23 * better handled through the machvec ioport mapping routines these days.
25 #include <linux/errno.h>
26 #include <asm/cache.h>
27 #include <asm/system.h>
28 #include <asm/addrspace.h>
29 #include <asm/machvec.h>
30 #include <asm/pgtable.h>
31 #include <asm-generic/iomap.h>
35 * Depending on which platform we are running on, we need different
38 #define __IO_PREFIX generic
39 #include <asm/io_generic.h>
40 #include <asm/io_trapped.h>
42 #define inb(p) sh_mv.mv_inb((p))
43 #define inw(p) sh_mv.mv_inw((p))
44 #define inl(p) sh_mv.mv_inl((p))
45 #define outb(x,p) sh_mv.mv_outb((x),(p))
46 #define outw(x,p) sh_mv.mv_outw((x),(p))
47 #define outl(x,p) sh_mv.mv_outl((x),(p))
49 #define inb_p(p) sh_mv.mv_inb_p((p))
50 #define inw_p(p) sh_mv.mv_inw_p((p))
51 #define inl_p(p) sh_mv.mv_inl_p((p))
52 #define outb_p(x,p) sh_mv.mv_outb_p((x),(p))
53 #define outw_p(x,p) sh_mv.mv_outw_p((x),(p))
54 #define outl_p(x,p) sh_mv.mv_outl_p((x),(p))
56 #define insb(p,b,c) sh_mv.mv_insb((p), (b), (c))
57 #define insw(p,b,c) sh_mv.mv_insw((p), (b), (c))
58 #define insl(p,b,c) sh_mv.mv_insl((p), (b), (c))
59 #define outsb(p,b,c) sh_mv.mv_outsb((p), (b), (c))
60 #define outsw(p,b,c) sh_mv.mv_outsw((p), (b), (c))
61 #define outsl(p,b,c) sh_mv.mv_outsl((p), (b), (c))
63 #define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile u8 __force *)(a) = (v))
64 #define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v))
65 #define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
66 #define __raw_writeq(v,a) (__chk_io_ptr(a), *(volatile u64 __force *)(a) = (v))
68 #define __raw_readb(a) (__chk_io_ptr(a), *(volatile u8 __force *)(a))
69 #define __raw_readw(a) (__chk_io_ptr(a), *(volatile u16 __force *)(a))
70 #define __raw_readl(a) (__chk_io_ptr(a), *(volatile u32 __force *)(a))
71 #define __raw_readq(a) (__chk_io_ptr(a), *(volatile u64 __force *)(a))
73 #define readb(a) ({ u8 r_ = __raw_readb(a); mb(); r_; })
74 #define readw(a) ({ u16 r_ = __raw_readw(a); mb(); r_; })
75 #define readl(a) ({ u32 r_ = __raw_readl(a); mb(); r_; })
76 #define readq(a) ({ u64 r_ = __raw_readq(a); mb(); r_; })
78 #define writeb(v,a) ({ __raw_writeb((v),(a)); mb(); })
79 #define writew(v,a) ({ __raw_writew((v),(a)); mb(); })
80 #define writel(v,a) ({ __raw_writel((v),(a)); mb(); })
81 #define writeq(v,a) ({ __raw_writeq((v),(a)); mb(); })
83 /* SuperH on-chip I/O functions */
84 #define ctrl_inb __raw_readb
85 #define ctrl_inw __raw_readw
86 #define ctrl_inl __raw_readl
87 #define ctrl_inq __raw_readq
89 #define ctrl_outb __raw_writeb
90 #define ctrl_outw __raw_writew
91 #define ctrl_outl __raw_writel
92 #define ctrl_outq __raw_writeq
94 extern unsigned long generic_io_base;
96 static inline void ctrl_delay(void)
98 __raw_readw(generic_io_base);
101 #define __BUILD_MEMORY_STRING(bwlq, type) \
103 static inline void __raw_writes##bwlq(volatile void __iomem *mem, \
104 const void *addr, unsigned int count) \
106 const volatile type *__addr = addr; \
109 __raw_write##bwlq(*__addr, mem); \
114 static inline void __raw_reads##bwlq(volatile void __iomem *mem, \
115 void *addr, unsigned int count) \
117 volatile type *__addr = addr; \
120 *__addr = __raw_read##bwlq(mem); \
125 __BUILD_MEMORY_STRING(b, u8)
126 __BUILD_MEMORY_STRING(w, u16)
128 #ifdef CONFIG_SUPERH32
129 void __raw_writesl(void __iomem *addr, const void *data, int longlen);
130 void __raw_readsl(const void __iomem *addr, void *data, int longlen);
132 __BUILD_MEMORY_STRING(l, u32)
135 __BUILD_MEMORY_STRING(q, u64)
137 #define writesb __raw_writesb
138 #define writesw __raw_writesw
139 #define writesl __raw_writesl
141 #define readsb __raw_readsb
142 #define readsw __raw_readsw
143 #define readsl __raw_readsl
145 #define readb_relaxed(a) readb(a)
146 #define readw_relaxed(a) readw(a)
147 #define readl_relaxed(a) readl(a)
148 #define readq_relaxed(a) readq(a)
150 #ifndef CONFIG_GENERIC_IOMAP
152 #define ioread8(a) __raw_readb(a)
153 #define ioread16(a) __raw_readw(a)
154 #define ioread16be(a) be16_to_cpu(__raw_readw((a)))
155 #define ioread32(a) __raw_readl(a)
156 #define ioread32be(a) be32_to_cpu(__raw_readl((a)))
158 #define iowrite8(v,a) __raw_writeb((v),(a))
159 #define iowrite16(v,a) __raw_writew((v),(a))
160 #define iowrite16be(v,a) __raw_writew(cpu_to_be16((v)),(a))
161 #define iowrite32(v,a) __raw_writel((v),(a))
162 #define iowrite32be(v,a) __raw_writel(cpu_to_be32((v)),(a))
164 #define ioread8_rep(a, d, c) __raw_readsb((a), (d), (c))
165 #define ioread16_rep(a, d, c) __raw_readsw((a), (d), (c))
166 #define ioread32_rep(a, d, c) __raw_readsl((a), (d), (c))
168 #define iowrite8_rep(a, s, c) __raw_writesb((a), (s), (c))
169 #define iowrite16_rep(a, s, c) __raw_writesw((a), (s), (c))
170 #define iowrite32_rep(a, s, c) __raw_writesl((a), (s), (c))
173 #define mmio_insb(p,d,c) __raw_readsb(p,d,c)
174 #define mmio_insw(p,d,c) __raw_readsw(p,d,c)
175 #define mmio_insl(p,d,c) __raw_readsl(p,d,c)
177 #define mmio_outsb(p,s,c) __raw_writesb(p,s,c)
178 #define mmio_outsw(p,s,c) __raw_writesw(p,s,c)
179 #define mmio_outsl(p,s,c) __raw_writesl(p,s,c)
181 /* synco on SH-4A, otherwise a nop */
182 #define mmiowb() wmb()
184 #define IO_SPACE_LIMIT 0xffffffff
187 * This function provides a method for the generic case where a
188 * board-specific ioport_map simply needs to return the port + some
189 * arbitrary port base.
191 * We use this at board setup time to implicitly set the port base, and
192 * as a result, we can use the generic ioport_map.
194 static inline void __set_io_port_base(unsigned long pbase)
196 generic_io_base = pbase;
199 #define __ioport_map(p, n) sh_mv.mv_ioport_map((p), (n))
201 /* We really want to try and get these to memcpy etc */
202 void memcpy_fromio(void *, const volatile void __iomem *, unsigned long);
203 void memcpy_toio(volatile void __iomem *, const void *, unsigned long);
204 void memset_io(volatile void __iomem *, int, unsigned long);
206 /* Quad-word real-mode I/O, don't ask.. */
207 unsigned long long peek_real_address_q(unsigned long long addr);
208 unsigned long long poke_real_address_q(unsigned long long addr,
209 unsigned long long val);
211 #if !defined(CONFIG_MMU)
212 #define virt_to_phys(address) ((unsigned long)(address))
213 #define phys_to_virt(address) ((void *)(address))
215 #define virt_to_phys(address) (__pa(address))
216 #define phys_to_virt(address) (__va(address))
220 * On 32-bit SH, we traditionally have the whole physical address space
221 * mapped at all times (as MIPS does), so "ioremap()" and "iounmap()" do
222 * not need to do anything but place the address in the proper segment.
223 * This is true for P1 and P2 addresses, as well as some P3 ones.
224 * However, most of the P3 addresses and newer cores using extended
225 * addressing need to map through page tables, so the ioremap()
226 * implementation becomes a bit more complicated.
228 * See arch/sh/mm/ioremap.c for additional notes on this.
230 * We cheat a bit and always return uncachable areas until we've fixed
231 * the drivers to handle caching properly.
233 * On the SH-5 the concept of segmentation in the 1:1 PXSEG sense simply
234 * doesn't exist, so everything must go through page tables.
237 void __iomem *__ioremap_caller(unsigned long offset, unsigned long size,
238 pgprot_t prot, void *caller);
239 void __iounmap(void __iomem *addr);
241 #ifdef CONFIG_IOREMAP_FIXED
242 extern void __iomem *ioremap_fixed(resource_size_t, unsigned long, pgprot_t);
243 extern int iounmap_fixed(void __iomem *);
244 extern void ioremap_fixed_init(void);
246 static inline void __iomem *
247 ioremap_fixed(resource_size t phys_addr, unsigned long size, pgprot_t prot)
252 static inline void ioremap_fixed_init(void) { }
253 static inline int iounmap_fixed(void __iomem *addr) { return -EINVAL; }
256 static inline void __iomem *
257 __ioremap(unsigned long offset, unsigned long size, pgprot_t prot)
259 return __ioremap_caller(offset, size, prot, __builtin_return_address(0));
262 static inline void __iomem *
263 __ioremap_29bit(unsigned long offset, unsigned long size, pgprot_t prot)
266 unsigned long last_addr = offset + size - 1;
269 * For P1 and P2 space this is trivial, as everything is already
270 * mapped. Uncached access for P1 addresses are done through P2.
271 * In the P3 case or for addresses outside of the 29-bit space,
272 * mapping must be done by the PMB or by using page tables.
274 if (likely(PXSEG(offset) < P3SEG && PXSEG(last_addr) < P3SEG)) {
275 if (unlikely(pgprot_val(prot) & _PAGE_CACHABLE))
276 return (void __iomem *)P1SEGADDR(offset);
278 return (void __iomem *)P2SEGADDR(offset);
281 /* P4 above the store queues are always mapped. */
282 if (unlikely(offset >= P3_ADDR_MAX))
283 return (void __iomem *)P4SEGADDR(offset);
289 static inline void __iomem *
290 __ioremap_mode(unsigned long offset, unsigned long size, pgprot_t prot)
294 ret = __ioremap_trapped(offset, size);
298 ret = __ioremap_29bit(offset, size, prot);
302 return __ioremap(offset, size, prot);
305 #define __ioremap(offset, size, prot) ((void __iomem *)(offset))
306 #define __ioremap_mode(offset, size, prot) ((void __iomem *)(offset))
307 #define __iounmap(addr) do { } while (0)
308 #endif /* CONFIG_MMU */
310 static inline void __iomem *
311 ioremap(unsigned long offset, unsigned long size)
313 return __ioremap_mode(offset, size, PAGE_KERNEL_NOCACHE);
316 static inline void __iomem *
317 ioremap_cache(unsigned long offset, unsigned long size)
319 return __ioremap_mode(offset, size, PAGE_KERNEL);
322 static inline void __iomem *
323 ioremap_prot(resource_size_t offset, unsigned long size, unsigned long flags)
325 return __ioremap_mode(offset, size, __pgprot(flags));
328 #define ioremap_nocache ioremap
329 #define p3_ioremap __ioremap
330 #define iounmap __iounmap
332 #define maybebadio(port) \
333 printk(KERN_ERR "bad PC-like io %s:%u for port 0x%lx at 0x%08x\n", \
334 __func__, __LINE__, (port), (u32)__builtin_return_address(0))
337 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
340 #define xlate_dev_mem_ptr(p) __va(p)
343 * Convert a virtual cached pointer to an uncached pointer
345 #define xlate_dev_kmem_ptr(p) p
347 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
348 int valid_phys_addr_range(unsigned long addr, size_t size);
349 int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
351 #endif /* __KERNEL__ */
353 #endif /* __ASM_SH_IO_H */