2 * linux/arch/sh/boards/se/7724/setup.c
4 * Copyright (C) 2009 Renesas Solutions Corp.
6 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/init.h>
14 #include <linux/device.h>
15 #include <linux/interrupt.h>
16 #include <linux/platform_device.h>
17 #include <linux/mtd/physmap.h>
18 #include <linux/delay.h>
19 #include <linux/smc91x.h>
20 #include <linux/gpio.h>
21 #include <linux/input.h>
22 #include <linux/input/sh_keysc.h>
23 #include <linux/usb/r8a66597.h>
24 #include <video/sh_mobile_lcdc.h>
25 #include <media/sh_mobile_ceu.h>
26 #include <sound/sh_fsi.h>
28 #include <asm/heartbeat.h>
29 #include <asm/sh_eth.h>
30 #include <asm/clock.h>
31 #include <asm/suspend.h>
32 #include <cpu/sh7724.h>
33 #include <mach-se/mach/se7724.h>
37 * ------------------------------------
38 * SW31 : 1001 1100 : default
39 * SW32 : 0111 1111 : use on board flash
41 * SW41 : abxx xxxx -> a = 0 : Analog monitor
50 * When you use 1280 x 720 lcdc output,
51 * you should change OSC6 lcdc clock from 25.175MHz to 74.25MHz,
52 * and change SW41 to use 720p
58 * This setup.c supports FSI slave mode.
59 * Please change J20, J21, J22 pin to 1-2 connection.
63 static struct resource heartbeat_resource = {
66 .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
69 static struct platform_device heartbeat_device = {
73 .resource = &heartbeat_resource,
77 static struct smc91x_platdata smc91x_info = {
78 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
81 static struct resource smc91x_eth_resources[] = {
86 .flags = IORESOURCE_MEM,
90 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
94 static struct platform_device smc91x_eth_device = {
96 .num_resources = ARRAY_SIZE(smc91x_eth_resources),
97 .resource = smc91x_eth_resources,
99 .platform_data = &smc91x_info,
104 static struct mtd_partition nor_flash_partitions[] = {
108 .size = (1 * 1024 * 1024),
109 .mask_flags = MTD_WRITEABLE, /* Read-only */
112 .offset = MTDPART_OFS_APPEND,
113 .size = (2 * 1024 * 1024),
116 .offset = MTDPART_OFS_APPEND,
117 .size = MTDPART_SIZ_FULL,
121 static struct physmap_flash_data nor_flash_data = {
123 .parts = nor_flash_partitions,
124 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
127 static struct resource nor_flash_resources[] = {
132 .flags = IORESOURCE_MEM,
136 static struct platform_device nor_flash_device = {
137 .name = "physmap-flash",
138 .resource = nor_flash_resources,
139 .num_resources = ARRAY_SIZE(nor_flash_resources),
141 .platform_data = &nor_flash_data,
146 static struct sh_mobile_lcdc_info lcdc_info = {
147 .clock_source = LCDC_CLK_EXTERNAL,
149 .chan = LCDC_CHAN_MAINLCD,
154 .sync = 0, /* hsync and vsync are active low */
156 .lcd_size_cfg = { /* 7.0 inch */
165 static struct resource lcdc_resources[] = {
170 .flags = IORESOURCE_MEM,
174 .flags = IORESOURCE_IRQ,
178 static struct platform_device lcdc_device = {
179 .name = "sh_mobile_lcdc_fb",
180 .num_resources = ARRAY_SIZE(lcdc_resources),
181 .resource = lcdc_resources,
183 .platform_data = &lcdc_info,
186 .hwblk_id = HWBLK_LCDC,
191 static struct sh_mobile_ceu_info sh_mobile_ceu0_info = {
192 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
195 static struct resource ceu0_resources[] = {
200 .flags = IORESOURCE_MEM,
204 .flags = IORESOURCE_IRQ,
207 /* place holder for contiguous memory */
211 static struct platform_device ceu0_device = {
212 .name = "sh_mobile_ceu",
213 .id = 0, /* "ceu0" clock */
214 .num_resources = ARRAY_SIZE(ceu0_resources),
215 .resource = ceu0_resources,
217 .platform_data = &sh_mobile_ceu0_info,
220 .hwblk_id = HWBLK_CEU0,
225 static struct sh_mobile_ceu_info sh_mobile_ceu1_info = {
226 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
229 static struct resource ceu1_resources[] = {
234 .flags = IORESOURCE_MEM,
238 .flags = IORESOURCE_IRQ,
241 /* place holder for contiguous memory */
245 static struct platform_device ceu1_device = {
246 .name = "sh_mobile_ceu",
247 .id = 1, /* "ceu1" clock */
248 .num_resources = ARRAY_SIZE(ceu1_resources),
249 .resource = ceu1_resources,
251 .platform_data = &sh_mobile_ceu1_info,
254 .hwblk_id = HWBLK_CEU1,
260 * FSI-A use external clock which came from ak464x.
261 * So, we should change parent of fsi
263 #define FCLKACR 0xa4150008
264 static void fsimck_init(struct clk *clk)
266 u32 status = __raw_readl(clk->enable_reg);
268 /* use external clock */
269 status &= ~0x000000ff;
270 status |= 0x00000080;
271 __raw_writel(status, clk->enable_reg);
274 static struct clk_ops fsimck_clk_ops = {
278 static struct clk fsimcka_clk = {
279 .name = "fsimcka_clk",
281 .ops = &fsimck_clk_ops,
282 .enable_reg = (void __iomem *)FCLKACR,
283 .rate = 0, /* unknown */
286 /* change J20, J21, J22 pin to 1-2 connection to use slave mode */
287 struct sh_fsi_platform_info fsi_info = {
288 .porta_flags = SH_FSI_BRS_INV |
289 SH_FSI_OUT_SLAVE_MODE |
290 SH_FSI_IN_SLAVE_MODE |
295 static struct resource fsi_resources[] = {
300 .flags = IORESOURCE_MEM,
304 .flags = IORESOURCE_IRQ,
308 static struct platform_device fsi_device = {
311 .num_resources = ARRAY_SIZE(fsi_resources),
312 .resource = fsi_resources,
314 .platform_data = &fsi_info,
317 .hwblk_id = HWBLK_SPU, /* FSI needs SPU hwblk */
321 /* KEYSC in SoC (Needs SW33-2 set to ON) */
322 static struct sh_keysc_info keysc_info = {
323 .mode = SH_KEYSC_MODE_1,
327 KEY_1, KEY_2, KEY_3, KEY_4, KEY_5,
328 KEY_6, KEY_7, KEY_8, KEY_9, KEY_A,
329 KEY_B, KEY_C, KEY_D, KEY_E, KEY_F,
330 KEY_G, KEY_H, KEY_I, KEY_K, KEY_L,
331 KEY_M, KEY_N, KEY_O, KEY_P, KEY_Q,
332 KEY_R, KEY_S, KEY_T, KEY_U, KEY_V,
336 static struct resource keysc_resources[] = {
341 .flags = IORESOURCE_MEM,
345 .flags = IORESOURCE_IRQ,
349 static struct platform_device keysc_device = {
351 .id = 0, /* "keysc0" clock */
352 .num_resources = ARRAY_SIZE(keysc_resources),
353 .resource = keysc_resources,
355 .platform_data = &keysc_info,
358 .hwblk_id = HWBLK_KEYSC,
363 static struct resource sh_eth_resources[] = {
365 .start = SH_ETH_ADDR,
366 .end = SH_ETH_ADDR + 0x1FC,
367 .flags = IORESOURCE_MEM,
371 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
375 struct sh_eth_plat_data sh_eth_plat = {
376 .phy = 0x1f, /* SMSC LAN8187 */
377 .edmac_endian = EDMAC_LITTLE_ENDIAN,
380 static struct platform_device sh_eth_device = {
384 .platform_data = &sh_eth_plat,
386 .num_resources = ARRAY_SIZE(sh_eth_resources),
387 .resource = sh_eth_resources,
389 .hwblk_id = HWBLK_ETHER,
393 static struct r8a66597_platdata sh7724_usb0_host_data = {
397 static struct resource sh7724_usb0_host_resources[] = {
400 .end = 0xa4d80124 - 1,
401 .flags = IORESOURCE_MEM,
406 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
410 static struct platform_device sh7724_usb0_host_device = {
411 .name = "r8a66597_hcd",
414 .dma_mask = NULL, /* not use dma */
415 .coherent_dma_mask = 0xffffffff,
416 .platform_data = &sh7724_usb0_host_data,
418 .num_resources = ARRAY_SIZE(sh7724_usb0_host_resources),
419 .resource = sh7724_usb0_host_resources,
421 .hwblk_id = HWBLK_USB0,
425 static struct r8a66597_platdata sh7724_usb1_gadget_data = {
429 static struct resource sh7724_usb1_gadget_resources[] = {
433 .flags = IORESOURCE_MEM,
438 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
442 static struct platform_device sh7724_usb1_gadget_device = {
443 .name = "r8a66597_udc",
446 .dma_mask = NULL, /* not use dma */
447 .coherent_dma_mask = 0xffffffff,
448 .platform_data = &sh7724_usb1_gadget_data,
450 .num_resources = ARRAY_SIZE(sh7724_usb1_gadget_resources),
451 .resource = sh7724_usb1_gadget_resources,
454 static struct resource sdhi0_cn7_resources[] = {
459 .flags = IORESOURCE_MEM,
463 .flags = IORESOURCE_IRQ,
467 static struct platform_device sdhi0_cn7_device = {
468 .name = "sh_mobile_sdhi",
470 .num_resources = ARRAY_SIZE(sdhi0_cn7_resources),
471 .resource = sdhi0_cn7_resources,
473 .hwblk_id = HWBLK_SDHI0,
477 static struct resource sdhi1_cn8_resources[] = {
482 .flags = IORESOURCE_MEM,
486 .flags = IORESOURCE_IRQ,
490 static struct platform_device sdhi1_cn8_device = {
491 .name = "sh_mobile_sdhi",
493 .num_resources = ARRAY_SIZE(sdhi1_cn8_resources),
494 .resource = sdhi1_cn8_resources,
496 .hwblk_id = HWBLK_SDHI1,
501 static struct resource irda_resources[] = {
506 .flags = IORESOURCE_MEM,
510 .flags = IORESOURCE_IRQ,
514 static struct platform_device irda_device = {
516 .num_resources = ARRAY_SIZE(irda_resources),
517 .resource = irda_resources,
520 static struct platform_device *ms7724se_devices[] __initdata = {
529 &sh7724_usb0_host_device,
530 &sh7724_usb1_gadget_device,
538 static struct i2c_board_info i2c0_devices[] = {
540 I2C_BOARD_INFO("ak4642", 0x12),
544 #define EEPROM_OP 0xBA206000
545 #define EEPROM_ADR 0xBA206004
546 #define EEPROM_DATA 0xBA20600C
547 #define EEPROM_STAT 0xBA206010
548 #define EEPROM_STRT 0xBA206014
549 static int __init sh_eth_is_eeprom_ready(void)
554 if (!__raw_readw(EEPROM_STAT))
559 printk(KERN_ERR "ms7724se can not access to eeprom\n");
563 static void __init sh_eth_init(void)
568 /* check EEPROM status */
569 if (!sh_eth_is_eeprom_ready())
572 /* read MAC addr from EEPROM */
573 for (i = 0 ; i < 3 ; i++) {
574 __raw_writew(0x0, EEPROM_OP); /* read */
575 __raw_writew(i*2, EEPROM_ADR);
576 __raw_writew(0x1, EEPROM_STRT);
577 if (!sh_eth_is_eeprom_ready())
580 mac = __raw_readw(EEPROM_DATA);
581 sh_eth_plat.mac_addr[i << 1] = mac & 0xff;
582 sh_eth_plat.mac_addr[(i << 1) + 1] = mac >> 8;
586 #define SW4140 0xBA201000
587 #define FPGA_OUT 0xBA200400
588 #define PORT_HIZA 0xA4050158
589 #define PORT_MSELCRB 0xA4050182
591 #define SW41_A 0x0100
592 #define SW41_B 0x0200
593 #define SW41_C 0x0400
594 #define SW41_D 0x0800
595 #define SW41_E 0x1000
596 #define SW41_F 0x2000
597 #define SW41_G 0x4000
598 #define SW41_H 0x8000
600 extern char ms7724se_sdram_enter_start;
601 extern char ms7724se_sdram_enter_end;
602 extern char ms7724se_sdram_leave_start;
603 extern char ms7724se_sdram_leave_end;
606 static int __init arch_setup(void)
608 /* enable I2C device */
609 i2c_register_board_info(0, i2c0_devices,
610 ARRAY_SIZE(i2c0_devices));
613 arch_initcall(arch_setup);
615 static int __init devices_setup(void)
617 u16 sw = __raw_readw(SW4140); /* select camera, monitor */
620 /* register board specific self-refresh code */
621 sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF |
623 &ms7724se_sdram_enter_start,
624 &ms7724se_sdram_enter_end,
625 &ms7724se_sdram_leave_start,
626 &ms7724se_sdram_leave_end);
628 __raw_writew(__raw_readw(FPGA_OUT) &
629 ~((1 << 1) | /* LAN */
630 (1 << 6) | /* VIDEO DAC */
631 (1 << 7) | /* AK4643 */
632 (1 << 8) | /* IrDA */
633 (1 << 12) | /* USB0 */
634 (1 << 14)), /* RMII */
637 /* turn on USB clocks, use external clock */
638 __raw_writew((__raw_readw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB);
640 /* Let LED9 show STATUS2 */
641 gpio_request(GPIO_FN_STATUS2, NULL);
643 /* Lit LED10 show STATUS0 */
644 gpio_request(GPIO_FN_STATUS0, NULL);
646 /* Lit LED11 show PDSTATUS */
647 gpio_request(GPIO_FN_PDSTATUS, NULL);
649 /* enable USB0 port */
650 __raw_writew(0x0600, 0xa40501d4);
652 /* enable USB1 port */
653 __raw_writew(0x0600, 0xa4050192);
655 /* enable IRQ 0,1,2 */
656 gpio_request(GPIO_FN_INTC_IRQ0, NULL);
657 gpio_request(GPIO_FN_INTC_IRQ1, NULL);
658 gpio_request(GPIO_FN_INTC_IRQ2, NULL);
661 gpio_request(GPIO_FN_SCIF3_I_SCK, NULL);
662 gpio_request(GPIO_FN_SCIF3_I_RXD, NULL);
663 gpio_request(GPIO_FN_SCIF3_I_TXD, NULL);
664 gpio_request(GPIO_FN_SCIF3_I_CTS, NULL);
665 gpio_request(GPIO_FN_SCIF3_I_RTS, NULL);
668 gpio_request(GPIO_FN_LCDD23, NULL);
669 gpio_request(GPIO_FN_LCDD22, NULL);
670 gpio_request(GPIO_FN_LCDD21, NULL);
671 gpio_request(GPIO_FN_LCDD20, NULL);
672 gpio_request(GPIO_FN_LCDD19, NULL);
673 gpio_request(GPIO_FN_LCDD18, NULL);
674 gpio_request(GPIO_FN_LCDD17, NULL);
675 gpio_request(GPIO_FN_LCDD16, NULL);
676 gpio_request(GPIO_FN_LCDD15, NULL);
677 gpio_request(GPIO_FN_LCDD14, NULL);
678 gpio_request(GPIO_FN_LCDD13, NULL);
679 gpio_request(GPIO_FN_LCDD12, NULL);
680 gpio_request(GPIO_FN_LCDD11, NULL);
681 gpio_request(GPIO_FN_LCDD10, NULL);
682 gpio_request(GPIO_FN_LCDD9, NULL);
683 gpio_request(GPIO_FN_LCDD8, NULL);
684 gpio_request(GPIO_FN_LCDD7, NULL);
685 gpio_request(GPIO_FN_LCDD6, NULL);
686 gpio_request(GPIO_FN_LCDD5, NULL);
687 gpio_request(GPIO_FN_LCDD4, NULL);
688 gpio_request(GPIO_FN_LCDD3, NULL);
689 gpio_request(GPIO_FN_LCDD2, NULL);
690 gpio_request(GPIO_FN_LCDD1, NULL);
691 gpio_request(GPIO_FN_LCDD0, NULL);
692 gpio_request(GPIO_FN_LCDDISP, NULL);
693 gpio_request(GPIO_FN_LCDHSYN, NULL);
694 gpio_request(GPIO_FN_LCDDCK, NULL);
695 gpio_request(GPIO_FN_LCDVSYN, NULL);
696 gpio_request(GPIO_FN_LCDDON, NULL);
697 gpio_request(GPIO_FN_LCDVEPWC, NULL);
698 gpio_request(GPIO_FN_LCDVCPWC, NULL);
699 gpio_request(GPIO_FN_LCDRD, NULL);
700 gpio_request(GPIO_FN_LCDLCLK, NULL);
701 __raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA);
704 gpio_request(GPIO_FN_VIO0_D15, NULL);
705 gpio_request(GPIO_FN_VIO0_D14, NULL);
706 gpio_request(GPIO_FN_VIO0_D13, NULL);
707 gpio_request(GPIO_FN_VIO0_D12, NULL);
708 gpio_request(GPIO_FN_VIO0_D11, NULL);
709 gpio_request(GPIO_FN_VIO0_D10, NULL);
710 gpio_request(GPIO_FN_VIO0_D9, NULL);
711 gpio_request(GPIO_FN_VIO0_D8, NULL);
712 gpio_request(GPIO_FN_VIO0_D7, NULL);
713 gpio_request(GPIO_FN_VIO0_D6, NULL);
714 gpio_request(GPIO_FN_VIO0_D5, NULL);
715 gpio_request(GPIO_FN_VIO0_D4, NULL);
716 gpio_request(GPIO_FN_VIO0_D3, NULL);
717 gpio_request(GPIO_FN_VIO0_D2, NULL);
718 gpio_request(GPIO_FN_VIO0_D1, NULL);
719 gpio_request(GPIO_FN_VIO0_D0, NULL);
720 gpio_request(GPIO_FN_VIO0_VD, NULL);
721 gpio_request(GPIO_FN_VIO0_CLK, NULL);
722 gpio_request(GPIO_FN_VIO0_FLD, NULL);
723 gpio_request(GPIO_FN_VIO0_HD, NULL);
724 platform_resource_setup_memory(&ceu0_device, "ceu0", 4 << 20);
727 gpio_request(GPIO_FN_VIO1_D7, NULL);
728 gpio_request(GPIO_FN_VIO1_D6, NULL);
729 gpio_request(GPIO_FN_VIO1_D5, NULL);
730 gpio_request(GPIO_FN_VIO1_D4, NULL);
731 gpio_request(GPIO_FN_VIO1_D3, NULL);
732 gpio_request(GPIO_FN_VIO1_D2, NULL);
733 gpio_request(GPIO_FN_VIO1_D1, NULL);
734 gpio_request(GPIO_FN_VIO1_D0, NULL);
735 gpio_request(GPIO_FN_VIO1_FLD, NULL);
736 gpio_request(GPIO_FN_VIO1_HD, NULL);
737 gpio_request(GPIO_FN_VIO1_VD, NULL);
738 gpio_request(GPIO_FN_VIO1_CLK, NULL);
739 platform_resource_setup_memory(&ceu1_device, "ceu1", 4 << 20);
742 gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
743 gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
744 gpio_request(GPIO_FN_KEYIN4, NULL);
745 gpio_request(GPIO_FN_KEYIN3, NULL);
746 gpio_request(GPIO_FN_KEYIN2, NULL);
747 gpio_request(GPIO_FN_KEYIN1, NULL);
748 gpio_request(GPIO_FN_KEYIN0, NULL);
749 gpio_request(GPIO_FN_KEYOUT3, NULL);
750 gpio_request(GPIO_FN_KEYOUT2, NULL);
751 gpio_request(GPIO_FN_KEYOUT1, NULL);
752 gpio_request(GPIO_FN_KEYOUT0, NULL);
755 gpio_request(GPIO_FN_FSIMCKB, NULL);
756 gpio_request(GPIO_FN_FSIMCKA, NULL);
757 gpio_request(GPIO_FN_FSIOASD, NULL);
758 gpio_request(GPIO_FN_FSIIABCK, NULL);
759 gpio_request(GPIO_FN_FSIIALRCK, NULL);
760 gpio_request(GPIO_FN_FSIOABCK, NULL);
761 gpio_request(GPIO_FN_FSIOALRCK, NULL);
762 gpio_request(GPIO_FN_CLKAUDIOAO, NULL);
763 gpio_request(GPIO_FN_FSIIBSD, NULL);
764 gpio_request(GPIO_FN_FSIOBSD, NULL);
765 gpio_request(GPIO_FN_FSIIBBCK, NULL);
766 gpio_request(GPIO_FN_FSIIBLRCK, NULL);
767 gpio_request(GPIO_FN_FSIOBBCK, NULL);
768 gpio_request(GPIO_FN_FSIOBLRCK, NULL);
769 gpio_request(GPIO_FN_CLKAUDIOBO, NULL);
770 gpio_request(GPIO_FN_FSIIASD, NULL);
772 /* set SPU2 clock to 83.4 MHz */
773 clk = clk_get(NULL, "spu_clk");
774 clk_set_rate(clk, clk_round_rate(clk, 83333333));
777 /* change parent of FSI A */
778 clk = clk_get(NULL, "fsia_clk");
779 clk_register(&fsimcka_clk);
780 clk_set_parent(clk, &fsimcka_clk);
781 clk_set_rate(clk, 11000);
782 clk_set_rate(&fsimcka_clk, 11000);
785 /* SDHI0 connected to cn7 */
786 gpio_request(GPIO_FN_SDHI0CD, NULL);
787 gpio_request(GPIO_FN_SDHI0WP, NULL);
788 gpio_request(GPIO_FN_SDHI0D3, NULL);
789 gpio_request(GPIO_FN_SDHI0D2, NULL);
790 gpio_request(GPIO_FN_SDHI0D1, NULL);
791 gpio_request(GPIO_FN_SDHI0D0, NULL);
792 gpio_request(GPIO_FN_SDHI0CMD, NULL);
793 gpio_request(GPIO_FN_SDHI0CLK, NULL);
795 /* SDHI1 connected to cn8 */
796 gpio_request(GPIO_FN_SDHI1CD, NULL);
797 gpio_request(GPIO_FN_SDHI1WP, NULL);
798 gpio_request(GPIO_FN_SDHI1D3, NULL);
799 gpio_request(GPIO_FN_SDHI1D2, NULL);
800 gpio_request(GPIO_FN_SDHI1D1, NULL);
801 gpio_request(GPIO_FN_SDHI1D0, NULL);
802 gpio_request(GPIO_FN_SDHI1CMD, NULL);
803 gpio_request(GPIO_FN_SDHI1CLK, NULL);
806 gpio_request(GPIO_FN_IRDA_OUT, NULL);
807 gpio_request(GPIO_FN_IRDA_IN, NULL);
812 * please remove J33 pin from your board !!
814 * ms7724 board should not use GPIO_FN_LNKSTA pin
815 * So, This time PTX5 is set to input pin
817 gpio_request(GPIO_FN_RMII_RXD0, NULL);
818 gpio_request(GPIO_FN_RMII_RXD1, NULL);
819 gpio_request(GPIO_FN_RMII_TXD0, NULL);
820 gpio_request(GPIO_FN_RMII_TXD1, NULL);
821 gpio_request(GPIO_FN_RMII_REF_CLK, NULL);
822 gpio_request(GPIO_FN_RMII_TX_EN, NULL);
823 gpio_request(GPIO_FN_RMII_RX_ER, NULL);
824 gpio_request(GPIO_FN_RMII_CRS_DV, NULL);
825 gpio_request(GPIO_FN_MDIO, NULL);
826 gpio_request(GPIO_FN_MDC, NULL);
827 gpio_request(GPIO_PTX5, NULL);
828 gpio_direction_input(GPIO_PTX5);
833 lcdc_info.ch[0].lcd_cfg.xres = 1280;
834 lcdc_info.ch[0].lcd_cfg.yres = 720;
835 lcdc_info.ch[0].lcd_cfg.left_margin = 220;
836 lcdc_info.ch[0].lcd_cfg.right_margin = 110;
837 lcdc_info.ch[0].lcd_cfg.hsync_len = 40;
838 lcdc_info.ch[0].lcd_cfg.upper_margin = 20;
839 lcdc_info.ch[0].lcd_cfg.lower_margin = 5;
840 lcdc_info.ch[0].lcd_cfg.vsync_len = 5;
843 lcdc_info.ch[0].lcd_cfg.xres = 640;
844 lcdc_info.ch[0].lcd_cfg.yres = 480;
845 lcdc_info.ch[0].lcd_cfg.left_margin = 105;
846 lcdc_info.ch[0].lcd_cfg.right_margin = 50;
847 lcdc_info.ch[0].lcd_cfg.hsync_len = 96;
848 lcdc_info.ch[0].lcd_cfg.upper_margin = 33;
849 lcdc_info.ch[0].lcd_cfg.lower_margin = 10;
850 lcdc_info.ch[0].lcd_cfg.vsync_len = 2;
854 /* Digital monitor */
855 lcdc_info.ch[0].interface_type = RGB18;
856 lcdc_info.ch[0].flags = 0;
859 lcdc_info.ch[0].interface_type = RGB24;
860 lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL;
863 return platform_add_devices(ms7724se_devices,
864 ARRAY_SIZE(ms7724se_devices));
866 device_initcall(devices_setup);
868 static struct sh_machine_vector mv_ms7724se __initmv = {
869 .mv_name = "ms7724se",
870 .mv_init_irq = init_se7724_IRQ,
871 .mv_nr_irqs = SE7724_FPGA_IRQ_BASE + SE7724_FPGA_IRQ_NR,