2 * Copyright IBM Corp. 1999, 2009
4 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
10 #include <linux/kernel.h>
11 #include <linux/errno.h>
12 #include <asm/types.h>
13 #include <asm/ptrace.h>
14 #include <asm/setup.h>
15 #include <asm/processor.h>
16 #include <asm/lowcore.h>
22 extern struct task_struct *__switch_to(void *, void *);
24 static inline void save_fp_regs(s390_fp_regs *fpregs)
31 : "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory");
32 if (!MACHINE_HAS_IEEE)
48 : "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory");
51 static inline void restore_fp_regs(s390_fp_regs *fpregs)
58 : : "a" (fpregs), "m" (*fpregs));
59 if (!MACHINE_HAS_IEEE)
75 : : "a" (fpregs), "m" (*fpregs));
78 static inline void save_access_regs(unsigned int *acrs)
80 asm volatile("stam 0,15,0(%0)" : : "a" (acrs) : "memory");
83 static inline void restore_access_regs(unsigned int *acrs)
85 asm volatile("lam 0,15,0(%0)" : : "a" (acrs));
88 #define switch_to(prev,next,last) do { \
91 save_fp_regs(&prev->thread.fp_regs); \
92 restore_fp_regs(&next->thread.fp_regs); \
93 save_access_regs(&prev->thread.acrs[0]); \
94 restore_access_regs(&next->thread.acrs[0]); \
95 prev = __switch_to(prev,next); \
98 extern void account_vtime(struct task_struct *, struct task_struct *);
99 extern void account_tick_vtime(struct task_struct *);
100 extern void account_system_vtime(struct task_struct *);
103 extern void pfault_irq_init(void);
104 extern int pfault_init(void);
105 extern void pfault_fini(void);
106 #else /* CONFIG_PFAULT */
107 #define pfault_irq_init() do { } while (0)
108 #define pfault_init() ({-1;})
109 #define pfault_fini() do { } while (0)
110 #endif /* CONFIG_PFAULT */
112 extern void cmma_init(void);
114 #define finish_arch_switch(prev) do { \
115 set_fs(current->thread.mm_segment); \
116 account_vtime(prev, current); \
119 #define nop() asm volatile("nop")
121 #define xchg(ptr,x) \
123 __typeof__(*(ptr)) __ret; \
124 __ret = (__typeof__(*(ptr))) \
125 __xchg((unsigned long)(x), (void *)(ptr),sizeof(*(ptr))); \
129 extern void __xchg_called_with_bad_pointer(void);
131 static inline unsigned long __xchg(unsigned long x, void * ptr, int size)
133 unsigned long addr, old;
138 addr = (unsigned long) ptr;
139 shift = (3 ^ (addr & 3)) << 3;
148 : "=&d" (old), "=m" (*(int *) addr)
149 : "d" (x << shift), "d" (~(255 << shift)), "a" (addr),
150 "m" (*(int *) addr) : "memory", "cc", "0");
153 addr = (unsigned long) ptr;
154 shift = (2 ^ (addr & 2)) << 3;
163 : "=&d" (old), "=m" (*(int *) addr)
164 : "d" (x << shift), "d" (~(65535 << shift)), "a" (addr),
165 "m" (*(int *) addr) : "memory", "cc", "0");
170 "0: cs %0,%2,0(%3)\n"
172 : "=&d" (old), "=m" (*(int *) ptr)
173 : "d" (x), "a" (ptr), "m" (*(int *) ptr)
180 "0: csg %0,%2,0(%3)\n"
182 : "=&d" (old), "=m" (*(long *) ptr)
183 : "d" (x), "a" (ptr), "m" (*(long *) ptr)
186 #endif /* __s390x__ */
188 __xchg_called_with_bad_pointer();
193 * Atomic compare and exchange. Compare OLD with MEM, if identical,
194 * store NEW in MEM. Return the initial value in MEM. Success is
195 * indicated by comparing RETURN with OLD.
198 #define __HAVE_ARCH_CMPXCHG 1
200 #define cmpxchg(ptr, o, n) \
201 ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \
202 (unsigned long)(n), sizeof(*(ptr))))
204 extern void __cmpxchg_called_with_bad_pointer(void);
206 static inline unsigned long
207 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
209 unsigned long addr, prev, tmp;
214 addr = (unsigned long) ptr;
215 shift = (3 ^ (addr & 3)) << 3;
229 : "=&d" (prev), "=&d" (tmp)
230 : "d" (old << shift), "d" (new << shift), "a" (ptr),
231 "d" (~(255 << shift))
233 return prev >> shift;
235 addr = (unsigned long) ptr;
236 shift = (2 ^ (addr & 2)) << 3;
250 : "=&d" (prev), "=&d" (tmp)
251 : "d" (old << shift), "d" (new << shift), "a" (ptr),
252 "d" (~(65535 << shift))
254 return prev >> shift;
258 : "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
265 : "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
268 #endif /* __s390x__ */
270 __cmpxchg_called_with_bad_pointer();
275 * Force strict CPU ordering.
276 * And yes, this is required on UP too when we're talking
279 * This is very similar to the ppc eieio/sync instruction in that is
280 * does a checkpoint syncronisation & makes sure that
281 * all memory ops have completed wrt other CPU's ( see 7-15 POP DJB ).
284 #define eieio() asm volatile("bcr 15,0" : : : "memory")
285 #define SYNC_OTHER_CORES(x) eieio()
287 #define rmb() eieio()
288 #define wmb() eieio()
289 #define read_barrier_depends() do { } while(0)
290 #define smp_mb() mb()
291 #define smp_rmb() rmb()
292 #define smp_wmb() wmb()
293 #define smp_read_barrier_depends() read_barrier_depends()
294 #define smp_mb__before_clear_bit() smp_mb()
295 #define smp_mb__after_clear_bit() smp_mb()
298 #define set_mb(var, value) do { var = value; mb(); } while (0)
302 #define __ctl_load(array, low, high) ({ \
303 typedef struct { char _[sizeof(array)]; } addrtype; \
305 " lctlg %1,%2,0(%0)\n" \
306 : : "a" (&array), "i" (low), "i" (high), \
307 "m" (*(addrtype *)(&array))); \
310 #define __ctl_store(array, low, high) ({ \
311 typedef struct { char _[sizeof(array)]; } addrtype; \
313 " stctg %2,%3,0(%1)\n" \
314 : "=m" (*(addrtype *)(&array)) \
315 : "a" (&array), "i" (low), "i" (high)); \
318 #else /* __s390x__ */
320 #define __ctl_load(array, low, high) ({ \
321 typedef struct { char _[sizeof(array)]; } addrtype; \
323 " lctl %1,%2,0(%0)\n" \
324 : : "a" (&array), "i" (low), "i" (high), \
325 "m" (*(addrtype *)(&array))); \
328 #define __ctl_store(array, low, high) ({ \
329 typedef struct { char _[sizeof(array)]; } addrtype; \
331 " stctl %2,%3,0(%1)\n" \
332 : "=m" (*(addrtype *)(&array)) \
333 : "a" (&array), "i" (low), "i" (high)); \
336 #endif /* __s390x__ */
338 #define __ctl_set_bit(cr, bit) ({ \
339 unsigned long __dummy; \
340 __ctl_store(__dummy, cr, cr); \
341 __dummy |= 1UL << (bit); \
342 __ctl_load(__dummy, cr, cr); \
345 #define __ctl_clear_bit(cr, bit) ({ \
346 unsigned long __dummy; \
347 __ctl_store(__dummy, cr, cr); \
348 __dummy &= ~(1UL << (bit)); \
349 __ctl_load(__dummy, cr, cr); \
352 #include <linux/irqflags.h>
354 #include <asm-generic/cmpxchg-local.h>
356 static inline unsigned long __cmpxchg_local(volatile void *ptr,
358 unsigned long new, int size)
367 return __cmpxchg(ptr, old, new, size);
369 return __cmpxchg_local_generic(ptr, old, new, size);
376 * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
379 #define cmpxchg_local(ptr, o, n) \
380 ((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
381 (unsigned long)(n), sizeof(*(ptr))))
383 #define cmpxchg64_local(ptr, o, n) \
385 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
386 cmpxchg_local((ptr), (o), (n)); \
389 #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
393 * Use to set psw mask except for the first byte which
394 * won't be changed by this function.
397 __set_psw_mask(unsigned long mask)
399 __load_psw_mask(mask | (__raw_local_irq_stosm(0x00) & ~(-1UL >> 8)));
402 #define local_mcck_enable() __set_psw_mask(psw_kernel_bits)
403 #define local_mcck_disable() __set_psw_mask(psw_kernel_bits & ~PSW_MASK_MCHECK)
407 extern void smp_ctl_set_bit(int cr, int bit);
408 extern void smp_ctl_clear_bit(int cr, int bit);
409 #define ctl_set_bit(cr, bit) smp_ctl_set_bit(cr, bit)
410 #define ctl_clear_bit(cr, bit) smp_ctl_clear_bit(cr, bit)
414 #define ctl_set_bit(cr, bit) __ctl_set_bit(cr, bit)
415 #define ctl_clear_bit(cr, bit) __ctl_clear_bit(cr, bit)
417 #endif /* CONFIG_SMP */
419 static inline unsigned int stfl(void)
422 " .insn s,0xb2b10000,0(0)\n" /* stfl */
425 return S390_lowcore.stfl_fac_list;
428 static inline int __stfle(unsigned long long *list, int doublewords)
430 typedef struct { unsigned long long _[doublewords]; } addrtype;
431 register unsigned long __nr asm("0") = doublewords - 1;
433 asm volatile(".insn s,0xb2b00000,%0" /* stfle */
434 : "=m" (*(addrtype *) list), "+d" (__nr) : : "cc");
438 static inline int stfle(unsigned long long *list, int doublewords)
440 if (!(stfl() & (1UL << 24)))
442 return __stfle(list, doublewords);
445 static inline unsigned short stap(void)
447 unsigned short cpu_address;
449 asm volatile("stap %0" : "=m" (cpu_address));
453 extern void (*_machine_restart)(char *command);
454 extern void (*_machine_halt)(void);
455 extern void (*_machine_power_off)(void);
457 #define arch_align_stack(x) (x)
459 #ifdef CONFIG_TRACE_IRQFLAGS
460 extern psw_t sysc_restore_trace_psw;
461 extern psw_t io_restore_trace_psw;
464 static inline int tprot(unsigned long addr)
474 : "+d" (rc) : "a" (addr) : "cc");
478 #endif /* __KERNEL__ */