3 * Copyright IBM Corp. 1999
4 * Author(s): Hartmut Penner (hp@de.ibm.com),
5 * Martin Schwidefsky (schwidefsky@de.ibm.com)
7 * Derived from "include/asm-i386/processor.h"
8 * Copyright (C) 1994, Linus Torvalds
11 #ifndef __ASM_S390_PROCESSOR_H
12 #define __ASM_S390_PROCESSOR_H
14 #define CIF_MCCK_PENDING 0 /* machine check handling is pending */
15 #define CIF_ASCE 1 /* user asce needs fixup / uaccess */
16 #define CIF_NOHZ_DELAY 2 /* delay HZ disable for a tick */
18 #define _CIF_MCCK_PENDING (1<<CIF_MCCK_PENDING)
19 #define _CIF_ASCE (1<<CIF_ASCE)
20 #define _CIF_NOHZ_DELAY (1<<CIF_NOHZ_DELAY)
25 #include <linux/linkage.h>
26 #include <linux/irqflags.h>
29 #include <asm/ptrace.h>
30 #include <asm/setup.h>
31 #include <asm/runtime_instr.h>
33 static inline void set_cpu_flag(int flag)
35 S390_lowcore.cpu_flags |= (1U << flag);
38 static inline void clear_cpu_flag(int flag)
40 S390_lowcore.cpu_flags &= ~(1U << flag);
43 static inline int test_cpu_flag(int flag)
45 return !!(S390_lowcore.cpu_flags & (1U << flag));
48 #define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY)
51 * Default implementation of macro that returns current
52 * instruction pointer ("program counter").
54 #define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })
56 static inline void get_cpu_id(struct cpuid *ptr)
58 asm volatile("stidp %0" : "=Q" (*ptr));
61 extern void s390_adjust_jiffies(void);
62 extern const struct seq_operations cpuinfo_op;
63 extern int sysctl_ieee_emulation_warnings;
64 extern void execve_tail(void);
67 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
71 #define TASK_SIZE (1UL << 31)
72 #define TASK_MAX_SIZE (1UL << 31)
73 #define TASK_UNMAPPED_BASE (1UL << 30)
75 #else /* CONFIG_64BIT */
77 #define TASK_SIZE_OF(tsk) ((tsk)->mm->context.asce_limit)
78 #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \
79 (1UL << 30) : (1UL << 41))
80 #define TASK_SIZE TASK_SIZE_OF(current)
81 #define TASK_MAX_SIZE (1UL << 53)
83 #endif /* CONFIG_64BIT */
86 #define STACK_TOP (1UL << 31)
87 #define STACK_TOP_MAX (1UL << 31)
88 #else /* CONFIG_64BIT */
89 #define STACK_TOP (1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
90 #define STACK_TOP_MAX (1UL << 42)
91 #endif /* CONFIG_64BIT */
93 #define HAVE_ARCH_PICK_MMAP_LAYOUT
102 struct thread_struct {
103 s390_fp_regs fp_regs;
104 unsigned int acrs[NUM_ACRS];
105 unsigned long ksp; /* kernel stack pointer */
106 mm_segment_t mm_segment;
107 unsigned long gmap_addr; /* address of last gmap fault. */
108 unsigned int gmap_pfault; /* signal of a pending guest pfault */
109 struct per_regs per_user; /* User specified PER registers */
110 struct per_event per_event; /* Cause of the last PER trap */
111 unsigned long per_flags; /* Flags to control debug behavior */
112 /* pfault_wait is used to block the process on a pfault event */
113 unsigned long pfault_wait;
114 struct list_head list;
115 /* cpu runtime instrumentation */
116 struct runtime_instr_cb *ri_cb;
119 unsigned char trap_tdb[256]; /* Transaction abort diagnose block */
120 __vector128 *vxrs; /* Vector register save area */
124 /* Flag to disable transactions. */
125 #define PER_FLAG_NO_TE 1UL
126 /* Flag to enable random transaction aborts. */
127 #define PER_FLAG_TE_ABORT_RAND 2UL
128 /* Flag to specify random transaction abort mode:
129 * - abort each transaction at a random instruction before TEND if set.
130 * - abort random transactions at a random instruction if cleared.
132 #define PER_FLAG_TE_ABORT_RAND_TEND 4UL
134 typedef struct thread_struct thread_struct;
137 * Stack layout of a C stack frame.
141 unsigned long back_chain;
142 unsigned long empty1[5];
143 unsigned long gprs[10];
144 unsigned int empty2[8];
148 unsigned long empty1[5];
149 unsigned int empty2[8];
150 unsigned long gprs[10];
151 unsigned long back_chain;
155 #define ARCH_MIN_TASKALIGN 8
157 #define INIT_THREAD { \
158 .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \
162 * Do necessary setup to start up a new thread.
164 #define start_thread(regs, new_psw, new_stackp) do { \
165 regs->psw.mask = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA; \
166 regs->psw.addr = new_psw | PSW_ADDR_AMODE; \
167 regs->gprs[15] = new_stackp; \
171 #define start_thread31(regs, new_psw, new_stackp) do { \
172 regs->psw.mask = PSW_USER_BITS | PSW_MASK_BA; \
173 regs->psw.addr = new_psw | PSW_ADDR_AMODE; \
174 regs->gprs[15] = new_stackp; \
175 crst_table_downgrade(current->mm, 1UL << 31); \
179 /* Forward declaration, a strange C thing */
185 extern void show_cacheinfo(struct seq_file *m);
187 static inline void show_cacheinfo(struct seq_file *m) { }
190 /* Free all resources held by a thread. */
191 extern void release_thread(struct task_struct *);
194 * Return saved PC of a blocked thread.
196 extern unsigned long thread_saved_pc(struct task_struct *t);
198 unsigned long get_wchan(struct task_struct *p);
199 #define task_pt_regs(tsk) ((struct pt_regs *) \
200 (task_stack_page(tsk) + THREAD_SIZE) - 1)
201 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr)
202 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15])
204 /* Has task runtime instrumentation enabled ? */
205 #define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
207 static inline unsigned short stap(void)
209 unsigned short cpu_address;
211 asm volatile("stap %0" : "=m" (cpu_address));
216 * Give up the time slice of the virtual PU.
218 void cpu_relax(void);
220 #define cpu_relax_lowlatency() barrier()
222 static inline void psw_set_key(unsigned int key)
224 asm volatile("spka 0(%0)" : : "d" (key));
228 * Set PSW to specified value.
230 static inline void __load_psw(psw_t psw)
233 asm volatile("lpsw %0" : : "Q" (psw) : "cc");
235 asm volatile("lpswe %0" : : "Q" (psw) : "cc");
240 * Set PSW mask to specified value, while leaving the
241 * PSW addr pointing to the next instruction.
243 static inline void __load_psw_mask (unsigned long mask)
254 " st %0,%O1+4(%R1)\n"
257 : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
258 #else /* CONFIG_64BIT */
261 " stg %0,%O1+8(%R1)\n"
264 : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
265 #endif /* CONFIG_64BIT */
269 * Rewind PSW instruction address by specified number of bytes.
271 static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
274 if (psw.addr & PSW_ADDR_AMODE)
276 return (psw.addr - ilc) | PSW_ADDR_AMODE;
278 return (psw.addr - ilc) & ((1UL << 24) - 1);
282 mask = (psw.mask & PSW_MASK_EA) ? -1UL :
283 (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
285 return (psw.addr - ilc) & mask;
290 * Function to stop a processor until the next interrupt occurs
292 void enabled_wait(void);
295 * Function to drop a processor into disabled wait state
297 static inline void __noreturn disabled_wait(unsigned long code)
299 unsigned long ctl_buf;
302 dw_psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
305 * Store status and then load disabled wait psw,
306 * the processor is dead afterwards
311 " ni 0(%2),0xef\n" /* switch off protection */
313 " stpt 0xd8\n" /* store timer */
314 " stckc 0xe0\n" /* store clock comparator */
315 " stpx 0x108\n" /* store prefix register */
316 " stam 0,15,0x120\n" /* store access registers */
317 " std 0,0x160\n" /* store f0 */
318 " std 2,0x168\n" /* store f2 */
319 " std 4,0x170\n" /* store f4 */
320 " std 6,0x178\n" /* store f6 */
321 " stm 0,15,0x180\n" /* store general registers */
322 " stctl 0,15,0x1c0\n" /* store control registers */
323 " oi 0x1c0,0x10\n" /* fake protection bit */
326 : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc");
327 #else /* CONFIG_64BIT */
330 " ni 4(%2),0xef\n" /* switch off protection */
333 " stpt 0x328(1)\n" /* store timer */
334 " stckc 0x330(1)\n" /* store clock comparator */
335 " stpx 0x318(1)\n" /* store prefix register */
336 " stam 0,15,0x340(1)\n"/* store access registers */
337 " stfpc 0x31c(1)\n" /* store fpu control */
338 " std 0,0x200(1)\n" /* store f0 */
339 " std 1,0x208(1)\n" /* store f1 */
340 " std 2,0x210(1)\n" /* store f2 */
341 " std 3,0x218(1)\n" /* store f3 */
342 " std 4,0x220(1)\n" /* store f4 */
343 " std 5,0x228(1)\n" /* store f5 */
344 " std 6,0x230(1)\n" /* store f6 */
345 " std 7,0x238(1)\n" /* store f7 */
346 " std 8,0x240(1)\n" /* store f8 */
347 " std 9,0x248(1)\n" /* store f9 */
348 " std 10,0x250(1)\n" /* store f10 */
349 " std 11,0x258(1)\n" /* store f11 */
350 " std 12,0x260(1)\n" /* store f12 */
351 " std 13,0x268(1)\n" /* store f13 */
352 " std 14,0x270(1)\n" /* store f14 */
353 " std 15,0x278(1)\n" /* store f15 */
354 " stmg 0,15,0x280(1)\n"/* store general registers */
355 " stctg 0,15,0x380(1)\n"/* store control registers */
356 " oi 0x384(1),0x10\n"/* fake protection bit */
359 : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0", "1");
360 #endif /* CONFIG_64BIT */
365 * Use to set psw mask except for the first byte which
366 * won't be changed by this function.
369 __set_psw_mask(unsigned long mask)
371 __load_psw_mask(mask | (arch_local_save_flags() & ~(-1UL >> 8)));
374 #define local_mcck_enable() \
375 __set_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT | PSW_MASK_MCHECK)
376 #define local_mcck_disable() \
377 __set_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT)
380 * Basic Machine Check/Program Check Handler.
383 extern void s390_base_mcck_handler(void);
384 extern void s390_base_pgm_handler(void);
385 extern void s390_base_ext_handler(void);
387 extern void (*s390_base_mcck_handler_fn)(void);
388 extern void (*s390_base_pgm_handler_fn)(void);
389 extern void (*s390_base_ext_handler_fn)(void);
391 #define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL
393 extern int memcpy_real(void *, void *, size_t);
394 extern void memcpy_absolute(void *, void *, size_t);
396 #define mem_assign_absolute(dest, val) { \
397 __typeof__(dest) __tmp = (val); \
399 BUILD_BUG_ON(sizeof(__tmp) != sizeof(val)); \
400 memcpy_absolute(&(dest), &__tmp, sizeof(__tmp)); \
404 * Helper macro for exception table entries
406 #define EX_TABLE(_fault, _target) \
407 ".section __ex_table,\"a\"\n" \
409 ".long (" #_fault ") - .\n" \
410 ".long (" #_target ") - .\n" \
413 #else /* __ASSEMBLY__ */
415 #define EX_TABLE(_fault, _target) \
416 .section __ex_table,"a" ; \
418 .long (_fault) - . ; \
419 .long (_target) - . ; \
422 #endif /* __ASSEMBLY__ */
424 #endif /* __ASM_S390_PROCESSOR_H */