1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Derived from "include/asm-i386/mmu_context.h"
8 #ifndef __S390_MMU_CONTEXT_H
9 #define __S390_MMU_CONTEXT_H
11 #include <asm/pgalloc.h>
12 #include <linux/uaccess.h>
13 #include <linux/mm_types.h>
14 #include <asm/tlbflush.h>
15 #include <asm/ctl_reg.h>
16 #include <asm-generic/mm_hooks.h>
18 static inline int init_new_context(struct task_struct *tsk,
21 unsigned long asce_type, init_entry;
23 spin_lock_init(&mm->context.lock);
24 INIT_LIST_HEAD(&mm->context.pgtable_list);
25 INIT_LIST_HEAD(&mm->context.gmap_list);
26 cpumask_clear(&mm->context.cpu_attach_mask);
27 atomic_set(&mm->context.flush_count, 0);
28 atomic_set(&mm->context.is_protected, 0);
29 mm->context.gmap_asce = 0;
30 mm->context.flush_mm = 0;
32 mm->context.alloc_pgste = page_table_allocate_pgste ||
33 test_thread_flag(TIF_PGSTE) ||
34 (current->mm && current->mm->context.alloc_pgste);
35 mm->context.has_pgste = 0;
36 mm->context.uses_skeys = 0;
37 mm->context.uses_cmm = 0;
38 mm->context.allow_gmap_hpage_1m = 0;
40 switch (mm->context.asce_limit) {
43 * context created by exec, the value of asce_limit can
44 * only be zero in this case
46 VM_BUG_ON(mm->context.asce_limit);
47 /* continue as 3-level task */
48 mm->context.asce_limit = _REGION2_SIZE;
51 /* forked 3-level task */
52 init_entry = _REGION3_ENTRY_EMPTY;
53 asce_type = _ASCE_TYPE_REGION3;
56 /* forked 5-level task */
57 init_entry = _REGION1_ENTRY_EMPTY;
58 asce_type = _ASCE_TYPE_REGION1;
61 /* forked 4-level task */
62 init_entry = _REGION2_ENTRY_EMPTY;
63 asce_type = _ASCE_TYPE_REGION2;
66 mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH |
67 _ASCE_USER_BITS | asce_type;
68 crst_table_init((unsigned long *) mm->pgd, init_entry);
72 #define destroy_context(mm) do { } while (0)
74 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
75 struct task_struct *tsk)
77 int cpu = smp_processor_id();
80 S390_lowcore.user_asce = s390_invalid_asce;
82 S390_lowcore.user_asce = next->context.asce;
83 cpumask_set_cpu(cpu, &next->context.cpu_attach_mask);
84 /* Clear previous user-ASCE from CR7 */
85 __ctl_load(s390_invalid_asce, 7, 7);
87 cpumask_clear_cpu(cpu, &prev->context.cpu_attach_mask);
90 #define finish_arch_post_lock_switch finish_arch_post_lock_switch
91 static inline void finish_arch_post_lock_switch(void)
93 struct task_struct *tsk = current;
94 struct mm_struct *mm = tsk->mm;
98 while (atomic_read(&mm->context.flush_count))
100 cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
101 __tlb_flush_mm_lazy(mm);
104 __ctl_load(S390_lowcore.user_asce, 7, 7);
107 #define enter_lazy_tlb(mm,tsk) do { } while (0)
108 #define deactivate_mm(tsk,mm) do { } while (0)
110 static inline void activate_mm(struct mm_struct *prev,
111 struct mm_struct *next)
113 switch_mm(prev, next, current);
114 cpumask_set_cpu(smp_processor_id(), mm_cpumask(next));
115 __ctl_load(S390_lowcore.user_asce, 7, 7);
118 #endif /* __S390_MMU_CONTEXT_H */