1 // SPDX-License-Identifier: GPL-2.0
2 /* BPF JIT compiler for RV64G
4 * Copyright(c) 2019 Björn Töpel <bjorn.topel@gmail.com>
8 #include <linux/bitfield.h>
10 #include <linux/filter.h>
11 #include <linux/memory.h>
12 #include <linux/stop_machine.h>
13 #include <asm/patch.h>
16 #define RV_REG_TCC RV_REG_A6
17 #define RV_REG_TCC_SAVED RV_REG_S6 /* Store A6 in S6 if program do calls */
19 static const int regmap[] = {
20 [BPF_REG_0] = RV_REG_A5,
21 [BPF_REG_1] = RV_REG_A0,
22 [BPF_REG_2] = RV_REG_A1,
23 [BPF_REG_3] = RV_REG_A2,
24 [BPF_REG_4] = RV_REG_A3,
25 [BPF_REG_5] = RV_REG_A4,
26 [BPF_REG_6] = RV_REG_S1,
27 [BPF_REG_7] = RV_REG_S2,
28 [BPF_REG_8] = RV_REG_S3,
29 [BPF_REG_9] = RV_REG_S4,
30 [BPF_REG_FP] = RV_REG_S5,
31 [BPF_REG_AX] = RV_REG_T0,
34 static const int pt_regmap[] = {
35 [RV_REG_A0] = offsetof(struct pt_regs, a0),
36 [RV_REG_A1] = offsetof(struct pt_regs, a1),
37 [RV_REG_A2] = offsetof(struct pt_regs, a2),
38 [RV_REG_A3] = offsetof(struct pt_regs, a3),
39 [RV_REG_A4] = offsetof(struct pt_regs, a4),
40 [RV_REG_A5] = offsetof(struct pt_regs, a5),
41 [RV_REG_S1] = offsetof(struct pt_regs, s1),
42 [RV_REG_S2] = offsetof(struct pt_regs, s2),
43 [RV_REG_S3] = offsetof(struct pt_regs, s3),
44 [RV_REG_S4] = offsetof(struct pt_regs, s4),
45 [RV_REG_S5] = offsetof(struct pt_regs, s5),
46 [RV_REG_T0] = offsetof(struct pt_regs, t0),
50 RV_CTX_F_SEEN_TAIL_CALL = 0,
51 RV_CTX_F_SEEN_CALL = RV_REG_RA,
52 RV_CTX_F_SEEN_S1 = RV_REG_S1,
53 RV_CTX_F_SEEN_S2 = RV_REG_S2,
54 RV_CTX_F_SEEN_S3 = RV_REG_S3,
55 RV_CTX_F_SEEN_S4 = RV_REG_S4,
56 RV_CTX_F_SEEN_S5 = RV_REG_S5,
57 RV_CTX_F_SEEN_S6 = RV_REG_S6,
60 static u8 bpf_to_rv_reg(int bpf_reg, struct rv_jit_context *ctx)
62 u8 reg = regmap[bpf_reg];
65 case RV_CTX_F_SEEN_S1:
66 case RV_CTX_F_SEEN_S2:
67 case RV_CTX_F_SEEN_S3:
68 case RV_CTX_F_SEEN_S4:
69 case RV_CTX_F_SEEN_S5:
70 case RV_CTX_F_SEEN_S6:
71 __set_bit(reg, &ctx->flags);
76 static bool seen_reg(int reg, struct rv_jit_context *ctx)
79 case RV_CTX_F_SEEN_CALL:
80 case RV_CTX_F_SEEN_S1:
81 case RV_CTX_F_SEEN_S2:
82 case RV_CTX_F_SEEN_S3:
83 case RV_CTX_F_SEEN_S4:
84 case RV_CTX_F_SEEN_S5:
85 case RV_CTX_F_SEEN_S6:
86 return test_bit(reg, &ctx->flags);
91 static void mark_fp(struct rv_jit_context *ctx)
93 __set_bit(RV_CTX_F_SEEN_S5, &ctx->flags);
96 static void mark_call(struct rv_jit_context *ctx)
98 __set_bit(RV_CTX_F_SEEN_CALL, &ctx->flags);
101 static bool seen_call(struct rv_jit_context *ctx)
103 return test_bit(RV_CTX_F_SEEN_CALL, &ctx->flags);
106 static void mark_tail_call(struct rv_jit_context *ctx)
108 __set_bit(RV_CTX_F_SEEN_TAIL_CALL, &ctx->flags);
111 static bool seen_tail_call(struct rv_jit_context *ctx)
113 return test_bit(RV_CTX_F_SEEN_TAIL_CALL, &ctx->flags);
116 static u8 rv_tail_call_reg(struct rv_jit_context *ctx)
120 if (seen_call(ctx)) {
121 __set_bit(RV_CTX_F_SEEN_S6, &ctx->flags);
127 static bool is_32b_int(s64 val)
129 return -(1L << 31) <= val && val < (1L << 31);
132 static bool in_auipc_jalr_range(s64 val)
135 * auipc+jalr can reach any signed PC-relative offset in the range
136 * [-2^31 - 2^11, 2^31 - 2^11).
138 return (-(1L << 31) - (1L << 11)) <= val &&
139 val < ((1L << 31) - (1L << 11));
142 /* Emit fixed-length instructions for address */
143 static int emit_addr(u8 rd, u64 addr, bool extra_pass, struct rv_jit_context *ctx)
145 u64 ip = (u64)(ctx->insns + ctx->ninsns);
147 s64 upper = (off + (1 << 11)) >> 12;
148 s64 lower = off & 0xfff;
150 if (extra_pass && !in_auipc_jalr_range(off)) {
151 pr_err("bpf-jit: target offset 0x%llx is out of range\n", off);
155 emit(rv_auipc(rd, upper), ctx);
156 emit(rv_addi(rd, rd, lower), ctx);
160 /* Emit variable-length instructions for 32-bit and 64-bit imm */
161 static void emit_imm(u8 rd, s64 val, struct rv_jit_context *ctx)
163 /* Note that the immediate from the add is sign-extended,
164 * which means that we need to compensate this by adding 2^12,
165 * when the 12th bit is set. A simpler way of doing this, and
166 * getting rid of the check, is to just add 2**11 before the
167 * shift. The "Loading a 32-Bit constant" example from the
168 * "Computer Organization and Design, RISC-V edition" book by
169 * Patterson/Hennessy highlights this fact.
171 * This also means that we need to process LSB to MSB.
173 s64 upper = (val + (1 << 11)) >> 12;
174 /* Sign-extend lower 12 bits to 64 bits since immediates for li, addiw,
175 * and addi are signed and RVC checks will perform signed comparisons.
177 s64 lower = ((val & 0xfff) << 52) >> 52;
180 if (is_32b_int(val)) {
182 emit_lui(rd, upper, ctx);
185 emit_li(rd, lower, ctx);
189 emit_addiw(rd, rd, lower, ctx);
193 shift = __ffs(upper);
197 emit_imm(rd, upper, ctx);
199 emit_slli(rd, rd, shift, ctx);
201 emit_addi(rd, rd, lower, ctx);
204 static void __build_epilogue(bool is_tail_call, struct rv_jit_context *ctx)
206 int stack_adjust = ctx->stack_size, store_offset = stack_adjust - 8;
208 if (seen_reg(RV_REG_RA, ctx)) {
209 emit_ld(RV_REG_RA, store_offset, RV_REG_SP, ctx);
212 emit_ld(RV_REG_FP, store_offset, RV_REG_SP, ctx);
214 if (seen_reg(RV_REG_S1, ctx)) {
215 emit_ld(RV_REG_S1, store_offset, RV_REG_SP, ctx);
218 if (seen_reg(RV_REG_S2, ctx)) {
219 emit_ld(RV_REG_S2, store_offset, RV_REG_SP, ctx);
222 if (seen_reg(RV_REG_S3, ctx)) {
223 emit_ld(RV_REG_S3, store_offset, RV_REG_SP, ctx);
226 if (seen_reg(RV_REG_S4, ctx)) {
227 emit_ld(RV_REG_S4, store_offset, RV_REG_SP, ctx);
230 if (seen_reg(RV_REG_S5, ctx)) {
231 emit_ld(RV_REG_S5, store_offset, RV_REG_SP, ctx);
234 if (seen_reg(RV_REG_S6, ctx)) {
235 emit_ld(RV_REG_S6, store_offset, RV_REG_SP, ctx);
239 emit_addi(RV_REG_SP, RV_REG_SP, stack_adjust, ctx);
240 /* Set return value. */
242 emit_mv(RV_REG_A0, RV_REG_A5, ctx);
243 emit_jalr(RV_REG_ZERO, is_tail_call ? RV_REG_T3 : RV_REG_RA,
244 is_tail_call ? 20 : 0, /* skip reserved nops and TCC init */
248 static void emit_bcc(u8 cond, u8 rd, u8 rs, int rvoff,
249 struct rv_jit_context *ctx)
253 emit(rv_beq(rd, rs, rvoff >> 1), ctx);
256 emit(rv_bltu(rs, rd, rvoff >> 1), ctx);
259 emit(rv_bltu(rd, rs, rvoff >> 1), ctx);
262 emit(rv_bgeu(rd, rs, rvoff >> 1), ctx);
265 emit(rv_bgeu(rs, rd, rvoff >> 1), ctx);
268 emit(rv_bne(rd, rs, rvoff >> 1), ctx);
271 emit(rv_blt(rs, rd, rvoff >> 1), ctx);
274 emit(rv_blt(rd, rs, rvoff >> 1), ctx);
277 emit(rv_bge(rd, rs, rvoff >> 1), ctx);
280 emit(rv_bge(rs, rd, rvoff >> 1), ctx);
284 static void emit_branch(u8 cond, u8 rd, u8 rs, int rvoff,
285 struct rv_jit_context *ctx)
289 if (is_13b_int(rvoff)) {
290 emit_bcc(cond, rd, rs, rvoff, ctx);
305 cond = invert_bpf_cond(cond);
306 if (is_21b_int(rvoff)) {
307 emit_bcc(cond, rd, rs, 8, ctx);
308 emit(rv_jal(RV_REG_ZERO, rvoff >> 1), ctx);
312 /* 32b No need for an additional rvoff adjustment, since we
313 * get that from the auipc at PC', where PC = PC' + 4.
315 upper = (rvoff + (1 << 11)) >> 12;
316 lower = rvoff & 0xfff;
318 emit_bcc(cond, rd, rs, 12, ctx);
319 emit(rv_auipc(RV_REG_T1, upper), ctx);
320 emit(rv_jalr(RV_REG_ZERO, RV_REG_T1, lower), ctx);
323 static void emit_zext_32(u8 reg, struct rv_jit_context *ctx)
325 emit_slli(reg, reg, 32, ctx);
326 emit_srli(reg, reg, 32, ctx);
329 static int emit_bpf_tail_call(int insn, struct rv_jit_context *ctx)
331 int tc_ninsn, off, start_insn = ctx->ninsns;
332 u8 tcc = rv_tail_call_reg(ctx);
338 * if (index >= array->map.max_entries)
341 tc_ninsn = insn ? ctx->offset[insn] - ctx->offset[insn - 1] :
343 emit_zext_32(RV_REG_A2, ctx);
345 off = offsetof(struct bpf_array, map.max_entries);
346 if (is_12b_check(off, insn))
348 emit(rv_lwu(RV_REG_T1, off, RV_REG_A1), ctx);
349 off = ninsns_rvoff(tc_ninsn - (ctx->ninsns - start_insn));
350 emit_branch(BPF_JGE, RV_REG_A2, RV_REG_T1, off, ctx);
355 emit_addi(RV_REG_TCC, tcc, -1, ctx);
356 off = ninsns_rvoff(tc_ninsn - (ctx->ninsns - start_insn));
357 emit_branch(BPF_JSLT, RV_REG_TCC, RV_REG_ZERO, off, ctx);
359 /* prog = array->ptrs[index];
363 emit_slli(RV_REG_T2, RV_REG_A2, 3, ctx);
364 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_A1, ctx);
365 off = offsetof(struct bpf_array, ptrs);
366 if (is_12b_check(off, insn))
368 emit_ld(RV_REG_T2, off, RV_REG_T2, ctx);
369 off = ninsns_rvoff(tc_ninsn - (ctx->ninsns - start_insn));
370 emit_branch(BPF_JEQ, RV_REG_T2, RV_REG_ZERO, off, ctx);
372 /* goto *(prog->bpf_func + 4); */
373 off = offsetof(struct bpf_prog, bpf_func);
374 if (is_12b_check(off, insn))
376 emit_ld(RV_REG_T3, off, RV_REG_T2, ctx);
377 __build_epilogue(true, ctx);
381 static void init_regs(u8 *rd, u8 *rs, const struct bpf_insn *insn,
382 struct rv_jit_context *ctx)
384 u8 code = insn->code;
387 case BPF_JMP | BPF_JA:
388 case BPF_JMP | BPF_CALL:
389 case BPF_JMP | BPF_EXIT:
390 case BPF_JMP | BPF_TAIL_CALL:
393 *rd = bpf_to_rv_reg(insn->dst_reg, ctx);
396 if (code & (BPF_ALU | BPF_X) || code & (BPF_ALU64 | BPF_X) ||
397 code & (BPF_JMP | BPF_X) || code & (BPF_JMP32 | BPF_X) ||
398 code & BPF_LDX || code & BPF_STX)
399 *rs = bpf_to_rv_reg(insn->src_reg, ctx);
402 static void emit_zext_32_rd_rs(u8 *rd, u8 *rs, struct rv_jit_context *ctx)
404 emit_mv(RV_REG_T2, *rd, ctx);
405 emit_zext_32(RV_REG_T2, ctx);
406 emit_mv(RV_REG_T1, *rs, ctx);
407 emit_zext_32(RV_REG_T1, ctx);
412 static void emit_sext_32_rd_rs(u8 *rd, u8 *rs, struct rv_jit_context *ctx)
414 emit_addiw(RV_REG_T2, *rd, 0, ctx);
415 emit_addiw(RV_REG_T1, *rs, 0, ctx);
420 static void emit_zext_32_rd_t1(u8 *rd, struct rv_jit_context *ctx)
422 emit_mv(RV_REG_T2, *rd, ctx);
423 emit_zext_32(RV_REG_T2, ctx);
424 emit_zext_32(RV_REG_T1, ctx);
428 static void emit_sext_32_rd(u8 *rd, struct rv_jit_context *ctx)
430 emit_addiw(RV_REG_T2, *rd, 0, ctx);
434 static int emit_jump_and_link(u8 rd, s64 rvoff, bool fixed_addr,
435 struct rv_jit_context *ctx)
439 if (rvoff && fixed_addr && is_21b_int(rvoff)) {
440 emit(rv_jal(rd, rvoff >> 1), ctx);
442 } else if (in_auipc_jalr_range(rvoff)) {
443 upper = (rvoff + (1 << 11)) >> 12;
444 lower = rvoff & 0xfff;
445 emit(rv_auipc(RV_REG_T1, upper), ctx);
446 emit(rv_jalr(rd, RV_REG_T1, lower), ctx);
450 pr_err("bpf-jit: target offset 0x%llx is out of range\n", rvoff);
454 static bool is_signed_bpf_cond(u8 cond)
456 return cond == BPF_JSGT || cond == BPF_JSLT ||
457 cond == BPF_JSGE || cond == BPF_JSLE;
460 static int emit_call(u64 addr, bool fixed_addr, struct rv_jit_context *ctx)
465 if (addr && ctx->insns) {
466 ip = (u64)(long)(ctx->insns + ctx->ninsns);
470 return emit_jump_and_link(RV_REG_RA, off, fixed_addr, ctx);
473 static void emit_atomic(u8 rd, u8 rs, s16 off, s32 imm, bool is64,
474 struct rv_jit_context *ctx)
480 if (is_12b_int(off)) {
481 emit_addi(RV_REG_T1, rd, off, ctx);
483 emit_imm(RV_REG_T1, off, ctx);
484 emit_add(RV_REG_T1, RV_REG_T1, rd, ctx);
490 /* lock *(u32/u64 *)(dst_reg + off16) <op>= src_reg */
492 emit(is64 ? rv_amoadd_d(RV_REG_ZERO, rs, rd, 0, 0) :
493 rv_amoadd_w(RV_REG_ZERO, rs, rd, 0, 0), ctx);
496 emit(is64 ? rv_amoand_d(RV_REG_ZERO, rs, rd, 0, 0) :
497 rv_amoand_w(RV_REG_ZERO, rs, rd, 0, 0), ctx);
500 emit(is64 ? rv_amoor_d(RV_REG_ZERO, rs, rd, 0, 0) :
501 rv_amoor_w(RV_REG_ZERO, rs, rd, 0, 0), ctx);
504 emit(is64 ? rv_amoxor_d(RV_REG_ZERO, rs, rd, 0, 0) :
505 rv_amoxor_w(RV_REG_ZERO, rs, rd, 0, 0), ctx);
507 /* src_reg = atomic_fetch_<op>(dst_reg + off16, src_reg) */
508 case BPF_ADD | BPF_FETCH:
509 emit(is64 ? rv_amoadd_d(rs, rs, rd, 0, 0) :
510 rv_amoadd_w(rs, rs, rd, 0, 0), ctx);
512 emit_zext_32(rs, ctx);
514 case BPF_AND | BPF_FETCH:
515 emit(is64 ? rv_amoand_d(rs, rs, rd, 0, 0) :
516 rv_amoand_w(rs, rs, rd, 0, 0), ctx);
518 emit_zext_32(rs, ctx);
520 case BPF_OR | BPF_FETCH:
521 emit(is64 ? rv_amoor_d(rs, rs, rd, 0, 0) :
522 rv_amoor_w(rs, rs, rd, 0, 0), ctx);
524 emit_zext_32(rs, ctx);
526 case BPF_XOR | BPF_FETCH:
527 emit(is64 ? rv_amoxor_d(rs, rs, rd, 0, 0) :
528 rv_amoxor_w(rs, rs, rd, 0, 0), ctx);
530 emit_zext_32(rs, ctx);
532 /* src_reg = atomic_xchg(dst_reg + off16, src_reg); */
534 emit(is64 ? rv_amoswap_d(rs, rs, rd, 0, 0) :
535 rv_amoswap_w(rs, rs, rd, 0, 0), ctx);
537 emit_zext_32(rs, ctx);
539 /* r0 = atomic_cmpxchg(dst_reg + off16, r0, src_reg); */
541 r0 = bpf_to_rv_reg(BPF_REG_0, ctx);
542 emit(is64 ? rv_addi(RV_REG_T2, r0, 0) :
543 rv_addiw(RV_REG_T2, r0, 0), ctx);
544 emit(is64 ? rv_lr_d(r0, 0, rd, 0, 0) :
545 rv_lr_w(r0, 0, rd, 0, 0), ctx);
546 jmp_offset = ninsns_rvoff(8);
547 emit(rv_bne(RV_REG_T2, r0, jmp_offset >> 1), ctx);
548 emit(is64 ? rv_sc_d(RV_REG_T3, rs, rd, 0, 0) :
549 rv_sc_w(RV_REG_T3, rs, rd, 0, 0), ctx);
550 jmp_offset = ninsns_rvoff(-6);
551 emit(rv_bne(RV_REG_T3, 0, jmp_offset >> 1), ctx);
552 emit(rv_fence(0x3, 0x3), ctx);
557 #define BPF_FIXUP_OFFSET_MASK GENMASK(26, 0)
558 #define BPF_FIXUP_REG_MASK GENMASK(31, 27)
560 bool ex_handler_bpf(const struct exception_table_entry *ex,
561 struct pt_regs *regs)
563 off_t offset = FIELD_GET(BPF_FIXUP_OFFSET_MASK, ex->fixup);
564 int regs_offset = FIELD_GET(BPF_FIXUP_REG_MASK, ex->fixup);
566 *(unsigned long *)((void *)regs + pt_regmap[regs_offset]) = 0;
567 regs->epc = (unsigned long)&ex->fixup - offset;
572 /* For accesses to BTF pointers, add an entry to the exception table */
573 static int add_exception_handler(const struct bpf_insn *insn,
574 struct rv_jit_context *ctx,
575 int dst_reg, int insn_len)
577 struct exception_table_entry *ex;
581 if (!ctx->insns || !ctx->prog->aux->extable || BPF_MODE(insn->code) != BPF_PROBE_MEM)
584 if (WARN_ON_ONCE(ctx->nexentries >= ctx->prog->aux->num_exentries))
587 if (WARN_ON_ONCE(insn_len > ctx->ninsns))
590 if (WARN_ON_ONCE(!rvc_enabled() && insn_len == 1))
593 ex = &ctx->prog->aux->extable[ctx->nexentries];
594 pc = (unsigned long)&ctx->insns[ctx->ninsns - insn_len];
596 offset = pc - (long)&ex->insn;
597 if (WARN_ON_ONCE(offset >= 0 || offset < INT_MIN))
602 * Since the extable follows the program, the fixup offset is always
603 * negative and limited to BPF_JIT_REGION_SIZE. Store a positive value
604 * to keep things simple, and put the destination register in the upper
605 * bits. We don't need to worry about buildtime or runtime sort
606 * modifying the upper bits because the table is already sorted, and
607 * isn't part of the main exception table.
609 offset = (long)&ex->fixup - (pc + insn_len * sizeof(u16));
610 if (!FIELD_FIT(BPF_FIXUP_OFFSET_MASK, offset))
613 ex->fixup = FIELD_PREP(BPF_FIXUP_OFFSET_MASK, offset) |
614 FIELD_PREP(BPF_FIXUP_REG_MASK, dst_reg);
615 ex->type = EX_TYPE_BPF;
621 static int gen_call_or_nops(void *target, void *ip, u32 *insns)
625 struct rv_jit_context ctx;
628 ctx.insns = (u16 *)insns;
631 for (i = 0; i < 4; i++)
632 emit(rv_nop(), &ctx);
636 rvoff = (s64)(target - (ip + 4));
637 emit(rv_sd(RV_REG_SP, -8, RV_REG_RA), &ctx);
638 ret = emit_jump_and_link(RV_REG_RA, rvoff, false, &ctx);
641 emit(rv_ld(RV_REG_RA, -8, RV_REG_SP), &ctx);
646 static int gen_jump_or_nops(void *target, void *ip, u32 *insns)
649 struct rv_jit_context ctx;
652 ctx.insns = (u16 *)insns;
655 emit(rv_nop(), &ctx);
656 emit(rv_nop(), &ctx);
660 rvoff = (s64)(target - ip);
661 return emit_jump_and_link(RV_REG_ZERO, rvoff, false, &ctx);
664 int bpf_arch_text_poke(void *ip, enum bpf_text_poke_type poke_type,
665 void *old_addr, void *new_addr)
667 u32 old_insns[4], new_insns[4];
668 bool is_call = poke_type == BPF_MOD_CALL;
669 int (*gen_insns)(void *target, void *ip, u32 *insns);
670 int ninsns = is_call ? 4 : 2;
673 if (!is_bpf_text_address((unsigned long)ip))
676 gen_insns = is_call ? gen_call_or_nops : gen_jump_or_nops;
678 ret = gen_insns(old_addr, ip, old_insns);
682 if (memcmp(ip, old_insns, ninsns * 4))
685 ret = gen_insns(new_addr, ip, new_insns);
690 mutex_lock(&text_mutex);
691 if (memcmp(ip, new_insns, ninsns * 4))
692 ret = patch_text(ip, new_insns, ninsns);
693 mutex_unlock(&text_mutex);
699 static void store_args(int nregs, int args_off, struct rv_jit_context *ctx)
703 for (i = 0; i < nregs; i++) {
704 emit_sd(RV_REG_FP, -args_off, RV_REG_A0 + i, ctx);
709 static void restore_args(int nregs, int args_off, struct rv_jit_context *ctx)
713 for (i = 0; i < nregs; i++) {
714 emit_ld(RV_REG_A0 + i, -args_off, RV_REG_FP, ctx);
719 static int invoke_bpf_prog(struct bpf_tramp_link *l, int args_off, int retval_off,
720 int run_ctx_off, bool save_ret, struct rv_jit_context *ctx)
723 struct bpf_prog *p = l->link.prog;
724 int cookie_off = offsetof(struct bpf_tramp_run_ctx, bpf_cookie);
727 emit_imm(RV_REG_T1, l->cookie, ctx);
728 emit_sd(RV_REG_FP, -run_ctx_off + cookie_off, RV_REG_T1, ctx);
730 emit_sd(RV_REG_FP, -run_ctx_off + cookie_off, RV_REG_ZERO, ctx);
734 emit_imm(RV_REG_A0, (const s64)p, ctx);
736 emit_addi(RV_REG_A1, RV_REG_FP, -run_ctx_off, ctx);
737 ret = emit_call((const u64)bpf_trampoline_enter(p), true, ctx);
741 /* if (__bpf_prog_enter(prog) == 0)
742 * goto skip_exec_of_prog;
744 branch_off = ctx->ninsns;
745 /* nop reserved for conditional jump */
748 /* store prog start time */
749 emit_mv(RV_REG_S1, RV_REG_A0, ctx);
751 /* arg1: &args_off */
752 emit_addi(RV_REG_A0, RV_REG_FP, -args_off, ctx);
754 /* arg2: progs[i]->insnsi for interpreter */
755 emit_imm(RV_REG_A1, (const s64)p->insnsi, ctx);
756 ret = emit_call((const u64)p->bpf_func, true, ctx);
761 emit_sd(RV_REG_FP, -retval_off, regmap[BPF_REG_0], ctx);
763 /* update branch with beqz */
765 int offset = ninsns_rvoff(ctx->ninsns - branch_off);
766 u32 insn = rv_beq(RV_REG_A0, RV_REG_ZERO, offset >> 1);
767 *(u32 *)(ctx->insns + branch_off) = insn;
771 emit_imm(RV_REG_A0, (const s64)p, ctx);
772 /* arg2: prog start time */
773 emit_mv(RV_REG_A1, RV_REG_S1, ctx);
775 emit_addi(RV_REG_A2, RV_REG_FP, -run_ctx_off, ctx);
776 ret = emit_call((const u64)bpf_trampoline_exit(p), true, ctx);
781 static int __arch_prepare_bpf_trampoline(struct bpf_tramp_image *im,
782 const struct btf_func_model *m,
783 struct bpf_tramp_links *tlinks,
784 void *func_addr, u32 flags,
785 struct rv_jit_context *ctx)
788 int *branches_off = NULL;
789 int stack_size = 0, nregs = m->nr_args;
790 int retaddr_off, fp_off, retval_off, args_off;
791 int nregs_off, ip_off, run_ctx_off, sreg_off;
792 struct bpf_tramp_links *fentry = &tlinks[BPF_TRAMP_FENTRY];
793 struct bpf_tramp_links *fexit = &tlinks[BPF_TRAMP_FEXIT];
794 struct bpf_tramp_links *fmod_ret = &tlinks[BPF_TRAMP_MODIFY_RETURN];
795 void *orig_call = func_addr;
799 /* Generated trampoline stack layout:
801 * FP - 8 [ RA of parent func ] return address of parent
803 * FP - retaddr_off [ RA of traced func ] return address of traced
805 * FP - fp_off [ FP of parent func ]
807 * FP - retval_off [ return value ] BPF_TRAMP_F_CALL_ORIG or
808 * BPF_TRAMP_F_RET_FENTRY_RET
811 * FP - args_off [ arg1 ]
813 * FP - nregs_off [ regs count ]
815 * FP - ip_off [ traced func ] BPF_TRAMP_F_IP_ARG
817 * FP - run_ctx_off [ bpf_tramp_run_ctx ]
819 * FP - sreg_off [ callee saved reg ]
821 * [ pads ] pads for 16 bytes alignment
824 if (flags & (BPF_TRAMP_F_ORIG_STACK | BPF_TRAMP_F_SHARE_IPMODIFY))
827 /* extra regiters for struct arguments */
828 for (i = 0; i < m->nr_args; i++)
829 if (m->arg_flags[i] & BTF_FMODEL_STRUCT_ARG)
830 nregs += round_up(m->arg_size[i], 8) / 8 - 1;
832 /* 8 arguments passed by registers */
836 /* room for parent function return address */
840 retaddr_off = stack_size;
845 save_ret = flags & (BPF_TRAMP_F_CALL_ORIG | BPF_TRAMP_F_RET_FENTRY_RET);
848 retval_off = stack_size;
851 stack_size += nregs * 8;
852 args_off = stack_size;
855 nregs_off = stack_size;
857 if (flags & BPF_TRAMP_F_IP_ARG) {
862 stack_size += round_up(sizeof(struct bpf_tramp_run_ctx), 8);
863 run_ctx_off = stack_size;
866 sreg_off = stack_size;
868 stack_size = round_up(stack_size, 16);
870 emit_addi(RV_REG_SP, RV_REG_SP, -stack_size, ctx);
872 emit_sd(RV_REG_SP, stack_size - retaddr_off, RV_REG_RA, ctx);
873 emit_sd(RV_REG_SP, stack_size - fp_off, RV_REG_FP, ctx);
875 emit_addi(RV_REG_FP, RV_REG_SP, stack_size, ctx);
877 /* callee saved register S1 to pass start time */
878 emit_sd(RV_REG_FP, -sreg_off, RV_REG_S1, ctx);
880 /* store ip address of the traced function */
881 if (flags & BPF_TRAMP_F_IP_ARG) {
882 emit_imm(RV_REG_T1, (const s64)func_addr, ctx);
883 emit_sd(RV_REG_FP, -ip_off, RV_REG_T1, ctx);
886 emit_li(RV_REG_T1, nregs, ctx);
887 emit_sd(RV_REG_FP, -nregs_off, RV_REG_T1, ctx);
889 store_args(nregs, args_off, ctx);
891 /* skip to actual body of traced function */
892 if (flags & BPF_TRAMP_F_SKIP_FRAME)
895 if (flags & BPF_TRAMP_F_CALL_ORIG) {
896 emit_imm(RV_REG_A0, (const s64)im, ctx);
897 ret = emit_call((const u64)__bpf_tramp_enter, true, ctx);
902 for (i = 0; i < fentry->nr_links; i++) {
903 ret = invoke_bpf_prog(fentry->links[i], args_off, retval_off, run_ctx_off,
904 flags & BPF_TRAMP_F_RET_FENTRY_RET, ctx);
909 if (fmod_ret->nr_links) {
910 branches_off = kcalloc(fmod_ret->nr_links, sizeof(int), GFP_KERNEL);
914 /* cleanup to avoid garbage return value confusion */
915 emit_sd(RV_REG_FP, -retval_off, RV_REG_ZERO, ctx);
916 for (i = 0; i < fmod_ret->nr_links; i++) {
917 ret = invoke_bpf_prog(fmod_ret->links[i], args_off, retval_off,
918 run_ctx_off, true, ctx);
921 emit_ld(RV_REG_T1, -retval_off, RV_REG_FP, ctx);
922 branches_off[i] = ctx->ninsns;
923 /* nop reserved for conditional jump */
928 if (flags & BPF_TRAMP_F_CALL_ORIG) {
929 restore_args(nregs, args_off, ctx);
930 ret = emit_call((const u64)orig_call, true, ctx);
933 emit_sd(RV_REG_FP, -retval_off, RV_REG_A0, ctx);
934 im->ip_after_call = ctx->insns + ctx->ninsns;
935 /* 2 nops reserved for auipc+jalr pair */
940 /* update branches saved in invoke_bpf_mod_ret with bnez */
941 for (i = 0; ctx->insns && i < fmod_ret->nr_links; i++) {
942 offset = ninsns_rvoff(ctx->ninsns - branches_off[i]);
943 insn = rv_bne(RV_REG_T1, RV_REG_ZERO, offset >> 1);
944 *(u32 *)(ctx->insns + branches_off[i]) = insn;
947 for (i = 0; i < fexit->nr_links; i++) {
948 ret = invoke_bpf_prog(fexit->links[i], args_off, retval_off,
949 run_ctx_off, false, ctx);
954 if (flags & BPF_TRAMP_F_CALL_ORIG) {
955 im->ip_epilogue = ctx->insns + ctx->ninsns;
956 emit_imm(RV_REG_A0, (const s64)im, ctx);
957 ret = emit_call((const u64)__bpf_tramp_exit, true, ctx);
962 if (flags & BPF_TRAMP_F_RESTORE_REGS)
963 restore_args(nregs, args_off, ctx);
966 emit_ld(RV_REG_A0, -retval_off, RV_REG_FP, ctx);
968 emit_ld(RV_REG_S1, -sreg_off, RV_REG_FP, ctx);
970 if (flags & BPF_TRAMP_F_SKIP_FRAME)
971 /* return address of parent function */
972 emit_ld(RV_REG_RA, stack_size - 8, RV_REG_SP, ctx);
974 /* return address of traced function */
975 emit_ld(RV_REG_RA, stack_size - retaddr_off, RV_REG_SP, ctx);
977 emit_ld(RV_REG_FP, stack_size - fp_off, RV_REG_SP, ctx);
978 emit_addi(RV_REG_SP, RV_REG_SP, stack_size, ctx);
980 emit_jalr(RV_REG_ZERO, RV_REG_RA, 0, ctx);
988 int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *image,
989 void *image_end, const struct btf_func_model *m,
990 u32 flags, struct bpf_tramp_links *tlinks,
994 struct rv_jit_context ctx;
998 ret = __arch_prepare_bpf_trampoline(im, m, tlinks, func_addr, flags, &ctx);
1002 if (ninsns_rvoff(ret) > (long)image_end - (long)image)
1007 ret = __arch_prepare_bpf_trampoline(im, m, tlinks, func_addr, flags, &ctx);
1011 bpf_flush_icache(ctx.insns, ctx.insns + ctx.ninsns);
1013 return ninsns_rvoff(ret);
1016 int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
1019 bool is64 = BPF_CLASS(insn->code) == BPF_ALU64 ||
1020 BPF_CLASS(insn->code) == BPF_JMP;
1021 int s, e, rvoff, ret, i = insn - ctx->prog->insnsi;
1022 struct bpf_prog_aux *aux = ctx->prog->aux;
1023 u8 rd = -1, rs = -1, code = insn->code;
1024 s16 off = insn->off;
1025 s32 imm = insn->imm;
1027 init_regs(&rd, &rs, insn, ctx);
1031 case BPF_ALU | BPF_MOV | BPF_X:
1032 case BPF_ALU64 | BPF_MOV | BPF_X:
1034 /* Special mov32 for zext */
1035 emit_zext_32(rd, ctx);
1038 emit_mv(rd, rs, ctx);
1039 if (!is64 && !aux->verifier_zext)
1040 emit_zext_32(rd, ctx);
1043 /* dst = dst OP src */
1044 case BPF_ALU | BPF_ADD | BPF_X:
1045 case BPF_ALU64 | BPF_ADD | BPF_X:
1046 emit_add(rd, rd, rs, ctx);
1047 if (!is64 && !aux->verifier_zext)
1048 emit_zext_32(rd, ctx);
1050 case BPF_ALU | BPF_SUB | BPF_X:
1051 case BPF_ALU64 | BPF_SUB | BPF_X:
1053 emit_sub(rd, rd, rs, ctx);
1055 emit_subw(rd, rd, rs, ctx);
1057 if (!is64 && !aux->verifier_zext)
1058 emit_zext_32(rd, ctx);
1060 case BPF_ALU | BPF_AND | BPF_X:
1061 case BPF_ALU64 | BPF_AND | BPF_X:
1062 emit_and(rd, rd, rs, ctx);
1063 if (!is64 && !aux->verifier_zext)
1064 emit_zext_32(rd, ctx);
1066 case BPF_ALU | BPF_OR | BPF_X:
1067 case BPF_ALU64 | BPF_OR | BPF_X:
1068 emit_or(rd, rd, rs, ctx);
1069 if (!is64 && !aux->verifier_zext)
1070 emit_zext_32(rd, ctx);
1072 case BPF_ALU | BPF_XOR | BPF_X:
1073 case BPF_ALU64 | BPF_XOR | BPF_X:
1074 emit_xor(rd, rd, rs, ctx);
1075 if (!is64 && !aux->verifier_zext)
1076 emit_zext_32(rd, ctx);
1078 case BPF_ALU | BPF_MUL | BPF_X:
1079 case BPF_ALU64 | BPF_MUL | BPF_X:
1080 emit(is64 ? rv_mul(rd, rd, rs) : rv_mulw(rd, rd, rs), ctx);
1081 if (!is64 && !aux->verifier_zext)
1082 emit_zext_32(rd, ctx);
1084 case BPF_ALU | BPF_DIV | BPF_X:
1085 case BPF_ALU64 | BPF_DIV | BPF_X:
1086 emit(is64 ? rv_divu(rd, rd, rs) : rv_divuw(rd, rd, rs), ctx);
1087 if (!is64 && !aux->verifier_zext)
1088 emit_zext_32(rd, ctx);
1090 case BPF_ALU | BPF_MOD | BPF_X:
1091 case BPF_ALU64 | BPF_MOD | BPF_X:
1092 emit(is64 ? rv_remu(rd, rd, rs) : rv_remuw(rd, rd, rs), ctx);
1093 if (!is64 && !aux->verifier_zext)
1094 emit_zext_32(rd, ctx);
1096 case BPF_ALU | BPF_LSH | BPF_X:
1097 case BPF_ALU64 | BPF_LSH | BPF_X:
1098 emit(is64 ? rv_sll(rd, rd, rs) : rv_sllw(rd, rd, rs), ctx);
1099 if (!is64 && !aux->verifier_zext)
1100 emit_zext_32(rd, ctx);
1102 case BPF_ALU | BPF_RSH | BPF_X:
1103 case BPF_ALU64 | BPF_RSH | BPF_X:
1104 emit(is64 ? rv_srl(rd, rd, rs) : rv_srlw(rd, rd, rs), ctx);
1105 if (!is64 && !aux->verifier_zext)
1106 emit_zext_32(rd, ctx);
1108 case BPF_ALU | BPF_ARSH | BPF_X:
1109 case BPF_ALU64 | BPF_ARSH | BPF_X:
1110 emit(is64 ? rv_sra(rd, rd, rs) : rv_sraw(rd, rd, rs), ctx);
1111 if (!is64 && !aux->verifier_zext)
1112 emit_zext_32(rd, ctx);
1116 case BPF_ALU | BPF_NEG:
1117 case BPF_ALU64 | BPF_NEG:
1118 emit_sub(rd, RV_REG_ZERO, rd, ctx);
1119 if (!is64 && !aux->verifier_zext)
1120 emit_zext_32(rd, ctx);
1123 /* dst = BSWAP##imm(dst) */
1124 case BPF_ALU | BPF_END | BPF_FROM_LE:
1127 emit_slli(rd, rd, 48, ctx);
1128 emit_srli(rd, rd, 48, ctx);
1131 if (!aux->verifier_zext)
1132 emit_zext_32(rd, ctx);
1140 case BPF_ALU | BPF_END | BPF_FROM_BE:
1141 emit_li(RV_REG_T2, 0, ctx);
1143 emit_andi(RV_REG_T1, rd, 0xff, ctx);
1144 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx);
1145 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx);
1146 emit_srli(rd, rd, 8, ctx);
1150 emit_andi(RV_REG_T1, rd, 0xff, ctx);
1151 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx);
1152 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx);
1153 emit_srli(rd, rd, 8, ctx);
1155 emit_andi(RV_REG_T1, rd, 0xff, ctx);
1156 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx);
1157 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx);
1158 emit_srli(rd, rd, 8, ctx);
1162 emit_andi(RV_REG_T1, rd, 0xff, ctx);
1163 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx);
1164 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx);
1165 emit_srli(rd, rd, 8, ctx);
1167 emit_andi(RV_REG_T1, rd, 0xff, ctx);
1168 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx);
1169 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx);
1170 emit_srli(rd, rd, 8, ctx);
1172 emit_andi(RV_REG_T1, rd, 0xff, ctx);
1173 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx);
1174 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx);
1175 emit_srli(rd, rd, 8, ctx);
1177 emit_andi(RV_REG_T1, rd, 0xff, ctx);
1178 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx);
1179 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx);
1180 emit_srli(rd, rd, 8, ctx);
1182 emit_andi(RV_REG_T1, rd, 0xff, ctx);
1183 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx);
1185 emit_mv(rd, RV_REG_T2, ctx);
1189 case BPF_ALU | BPF_MOV | BPF_K:
1190 case BPF_ALU64 | BPF_MOV | BPF_K:
1191 emit_imm(rd, imm, ctx);
1192 if (!is64 && !aux->verifier_zext)
1193 emit_zext_32(rd, ctx);
1196 /* dst = dst OP imm */
1197 case BPF_ALU | BPF_ADD | BPF_K:
1198 case BPF_ALU64 | BPF_ADD | BPF_K:
1199 if (is_12b_int(imm)) {
1200 emit_addi(rd, rd, imm, ctx);
1202 emit_imm(RV_REG_T1, imm, ctx);
1203 emit_add(rd, rd, RV_REG_T1, ctx);
1205 if (!is64 && !aux->verifier_zext)
1206 emit_zext_32(rd, ctx);
1208 case BPF_ALU | BPF_SUB | BPF_K:
1209 case BPF_ALU64 | BPF_SUB | BPF_K:
1210 if (is_12b_int(-imm)) {
1211 emit_addi(rd, rd, -imm, ctx);
1213 emit_imm(RV_REG_T1, imm, ctx);
1214 emit_sub(rd, rd, RV_REG_T1, ctx);
1216 if (!is64 && !aux->verifier_zext)
1217 emit_zext_32(rd, ctx);
1219 case BPF_ALU | BPF_AND | BPF_K:
1220 case BPF_ALU64 | BPF_AND | BPF_K:
1221 if (is_12b_int(imm)) {
1222 emit_andi(rd, rd, imm, ctx);
1224 emit_imm(RV_REG_T1, imm, ctx);
1225 emit_and(rd, rd, RV_REG_T1, ctx);
1227 if (!is64 && !aux->verifier_zext)
1228 emit_zext_32(rd, ctx);
1230 case BPF_ALU | BPF_OR | BPF_K:
1231 case BPF_ALU64 | BPF_OR | BPF_K:
1232 if (is_12b_int(imm)) {
1233 emit(rv_ori(rd, rd, imm), ctx);
1235 emit_imm(RV_REG_T1, imm, ctx);
1236 emit_or(rd, rd, RV_REG_T1, ctx);
1238 if (!is64 && !aux->verifier_zext)
1239 emit_zext_32(rd, ctx);
1241 case BPF_ALU | BPF_XOR | BPF_K:
1242 case BPF_ALU64 | BPF_XOR | BPF_K:
1243 if (is_12b_int(imm)) {
1244 emit(rv_xori(rd, rd, imm), ctx);
1246 emit_imm(RV_REG_T1, imm, ctx);
1247 emit_xor(rd, rd, RV_REG_T1, ctx);
1249 if (!is64 && !aux->verifier_zext)
1250 emit_zext_32(rd, ctx);
1252 case BPF_ALU | BPF_MUL | BPF_K:
1253 case BPF_ALU64 | BPF_MUL | BPF_K:
1254 emit_imm(RV_REG_T1, imm, ctx);
1255 emit(is64 ? rv_mul(rd, rd, RV_REG_T1) :
1256 rv_mulw(rd, rd, RV_REG_T1), ctx);
1257 if (!is64 && !aux->verifier_zext)
1258 emit_zext_32(rd, ctx);
1260 case BPF_ALU | BPF_DIV | BPF_K:
1261 case BPF_ALU64 | BPF_DIV | BPF_K:
1262 emit_imm(RV_REG_T1, imm, ctx);
1263 emit(is64 ? rv_divu(rd, rd, RV_REG_T1) :
1264 rv_divuw(rd, rd, RV_REG_T1), ctx);
1265 if (!is64 && !aux->verifier_zext)
1266 emit_zext_32(rd, ctx);
1268 case BPF_ALU | BPF_MOD | BPF_K:
1269 case BPF_ALU64 | BPF_MOD | BPF_K:
1270 emit_imm(RV_REG_T1, imm, ctx);
1271 emit(is64 ? rv_remu(rd, rd, RV_REG_T1) :
1272 rv_remuw(rd, rd, RV_REG_T1), ctx);
1273 if (!is64 && !aux->verifier_zext)
1274 emit_zext_32(rd, ctx);
1276 case BPF_ALU | BPF_LSH | BPF_K:
1277 case BPF_ALU64 | BPF_LSH | BPF_K:
1278 emit_slli(rd, rd, imm, ctx);
1280 if (!is64 && !aux->verifier_zext)
1281 emit_zext_32(rd, ctx);
1283 case BPF_ALU | BPF_RSH | BPF_K:
1284 case BPF_ALU64 | BPF_RSH | BPF_K:
1286 emit_srli(rd, rd, imm, ctx);
1288 emit(rv_srliw(rd, rd, imm), ctx);
1290 if (!is64 && !aux->verifier_zext)
1291 emit_zext_32(rd, ctx);
1293 case BPF_ALU | BPF_ARSH | BPF_K:
1294 case BPF_ALU64 | BPF_ARSH | BPF_K:
1296 emit_srai(rd, rd, imm, ctx);
1298 emit(rv_sraiw(rd, rd, imm), ctx);
1300 if (!is64 && !aux->verifier_zext)
1301 emit_zext_32(rd, ctx);
1305 case BPF_JMP | BPF_JA:
1306 rvoff = rv_offset(i, off, ctx);
1307 ret = emit_jump_and_link(RV_REG_ZERO, rvoff, true, ctx);
1312 /* IF (dst COND src) JUMP off */
1313 case BPF_JMP | BPF_JEQ | BPF_X:
1314 case BPF_JMP32 | BPF_JEQ | BPF_X:
1315 case BPF_JMP | BPF_JGT | BPF_X:
1316 case BPF_JMP32 | BPF_JGT | BPF_X:
1317 case BPF_JMP | BPF_JLT | BPF_X:
1318 case BPF_JMP32 | BPF_JLT | BPF_X:
1319 case BPF_JMP | BPF_JGE | BPF_X:
1320 case BPF_JMP32 | BPF_JGE | BPF_X:
1321 case BPF_JMP | BPF_JLE | BPF_X:
1322 case BPF_JMP32 | BPF_JLE | BPF_X:
1323 case BPF_JMP | BPF_JNE | BPF_X:
1324 case BPF_JMP32 | BPF_JNE | BPF_X:
1325 case BPF_JMP | BPF_JSGT | BPF_X:
1326 case BPF_JMP32 | BPF_JSGT | BPF_X:
1327 case BPF_JMP | BPF_JSLT | BPF_X:
1328 case BPF_JMP32 | BPF_JSLT | BPF_X:
1329 case BPF_JMP | BPF_JSGE | BPF_X:
1330 case BPF_JMP32 | BPF_JSGE | BPF_X:
1331 case BPF_JMP | BPF_JSLE | BPF_X:
1332 case BPF_JMP32 | BPF_JSLE | BPF_X:
1333 case BPF_JMP | BPF_JSET | BPF_X:
1334 case BPF_JMP32 | BPF_JSET | BPF_X:
1335 rvoff = rv_offset(i, off, ctx);
1338 if (is_signed_bpf_cond(BPF_OP(code)))
1339 emit_sext_32_rd_rs(&rd, &rs, ctx);
1341 emit_zext_32_rd_rs(&rd, &rs, ctx);
1344 /* Adjust for extra insns */
1345 rvoff -= ninsns_rvoff(e - s);
1348 if (BPF_OP(code) == BPF_JSET) {
1349 /* Adjust for and */
1351 emit_and(RV_REG_T1, rd, rs, ctx);
1352 emit_branch(BPF_JNE, RV_REG_T1, RV_REG_ZERO, rvoff,
1355 emit_branch(BPF_OP(code), rd, rs, rvoff, ctx);
1359 /* IF (dst COND imm) JUMP off */
1360 case BPF_JMP | BPF_JEQ | BPF_K:
1361 case BPF_JMP32 | BPF_JEQ | BPF_K:
1362 case BPF_JMP | BPF_JGT | BPF_K:
1363 case BPF_JMP32 | BPF_JGT | BPF_K:
1364 case BPF_JMP | BPF_JLT | BPF_K:
1365 case BPF_JMP32 | BPF_JLT | BPF_K:
1366 case BPF_JMP | BPF_JGE | BPF_K:
1367 case BPF_JMP32 | BPF_JGE | BPF_K:
1368 case BPF_JMP | BPF_JLE | BPF_K:
1369 case BPF_JMP32 | BPF_JLE | BPF_K:
1370 case BPF_JMP | BPF_JNE | BPF_K:
1371 case BPF_JMP32 | BPF_JNE | BPF_K:
1372 case BPF_JMP | BPF_JSGT | BPF_K:
1373 case BPF_JMP32 | BPF_JSGT | BPF_K:
1374 case BPF_JMP | BPF_JSLT | BPF_K:
1375 case BPF_JMP32 | BPF_JSLT | BPF_K:
1376 case BPF_JMP | BPF_JSGE | BPF_K:
1377 case BPF_JMP32 | BPF_JSGE | BPF_K:
1378 case BPF_JMP | BPF_JSLE | BPF_K:
1379 case BPF_JMP32 | BPF_JSLE | BPF_K:
1380 rvoff = rv_offset(i, off, ctx);
1383 emit_imm(RV_REG_T1, imm, ctx);
1386 /* If imm is 0, simply use zero register. */
1390 if (is_signed_bpf_cond(BPF_OP(code)))
1391 emit_sext_32_rd(&rd, ctx);
1393 emit_zext_32_rd_t1(&rd, ctx);
1397 /* Adjust for extra insns */
1398 rvoff -= ninsns_rvoff(e - s);
1399 emit_branch(BPF_OP(code), rd, rs, rvoff, ctx);
1402 case BPF_JMP | BPF_JSET | BPF_K:
1403 case BPF_JMP32 | BPF_JSET | BPF_K:
1404 rvoff = rv_offset(i, off, ctx);
1406 if (is_12b_int(imm)) {
1407 emit_andi(RV_REG_T1, rd, imm, ctx);
1409 emit_imm(RV_REG_T1, imm, ctx);
1410 emit_and(RV_REG_T1, rd, RV_REG_T1, ctx);
1412 /* For jset32, we should clear the upper 32 bits of t1, but
1413 * sign-extension is sufficient here and saves one instruction,
1414 * as t1 is used only in comparison against zero.
1416 if (!is64 && imm < 0)
1417 emit_addiw(RV_REG_T1, RV_REG_T1, 0, ctx);
1419 rvoff -= ninsns_rvoff(e - s);
1420 emit_branch(BPF_JNE, RV_REG_T1, RV_REG_ZERO, rvoff, ctx);
1424 case BPF_JMP | BPF_CALL:
1430 ret = bpf_jit_get_func_addr(ctx->prog, insn, extra_pass,
1431 &addr, &fixed_addr);
1435 ret = emit_call(addr, fixed_addr, ctx);
1439 emit_mv(bpf_to_rv_reg(BPF_REG_0, ctx), RV_REG_A0, ctx);
1443 case BPF_JMP | BPF_TAIL_CALL:
1444 if (emit_bpf_tail_call(i, ctx))
1448 /* function return */
1449 case BPF_JMP | BPF_EXIT:
1450 if (i == ctx->prog->len - 1)
1453 rvoff = epilogue_offset(ctx);
1454 ret = emit_jump_and_link(RV_REG_ZERO, rvoff, true, ctx);
1460 case BPF_LD | BPF_IMM | BPF_DW:
1462 struct bpf_insn insn1 = insn[1];
1465 imm64 = (u64)insn1.imm << 32 | (u32)imm;
1466 if (bpf_pseudo_func(insn)) {
1467 /* fixed-length insns for extra jit pass */
1468 ret = emit_addr(rd, imm64, extra_pass, ctx);
1472 emit_imm(rd, imm64, ctx);
1478 /* LDX: dst = *(size *)(src + off) */
1479 case BPF_LDX | BPF_MEM | BPF_B:
1480 case BPF_LDX | BPF_MEM | BPF_H:
1481 case BPF_LDX | BPF_MEM | BPF_W:
1482 case BPF_LDX | BPF_MEM | BPF_DW:
1483 case BPF_LDX | BPF_PROBE_MEM | BPF_B:
1484 case BPF_LDX | BPF_PROBE_MEM | BPF_H:
1485 case BPF_LDX | BPF_PROBE_MEM | BPF_W:
1486 case BPF_LDX | BPF_PROBE_MEM | BPF_DW:
1488 int insn_len, insns_start;
1490 switch (BPF_SIZE(code)) {
1492 if (is_12b_int(off)) {
1493 insns_start = ctx->ninsns;
1494 emit(rv_lbu(rd, off, rs), ctx);
1495 insn_len = ctx->ninsns - insns_start;
1499 emit_imm(RV_REG_T1, off, ctx);
1500 emit_add(RV_REG_T1, RV_REG_T1, rs, ctx);
1501 insns_start = ctx->ninsns;
1502 emit(rv_lbu(rd, 0, RV_REG_T1), ctx);
1503 insn_len = ctx->ninsns - insns_start;
1504 if (insn_is_zext(&insn[1]))
1508 if (is_12b_int(off)) {
1509 insns_start = ctx->ninsns;
1510 emit(rv_lhu(rd, off, rs), ctx);
1511 insn_len = ctx->ninsns - insns_start;
1515 emit_imm(RV_REG_T1, off, ctx);
1516 emit_add(RV_REG_T1, RV_REG_T1, rs, ctx);
1517 insns_start = ctx->ninsns;
1518 emit(rv_lhu(rd, 0, RV_REG_T1), ctx);
1519 insn_len = ctx->ninsns - insns_start;
1520 if (insn_is_zext(&insn[1]))
1524 if (is_12b_int(off)) {
1525 insns_start = ctx->ninsns;
1526 emit(rv_lwu(rd, off, rs), ctx);
1527 insn_len = ctx->ninsns - insns_start;
1531 emit_imm(RV_REG_T1, off, ctx);
1532 emit_add(RV_REG_T1, RV_REG_T1, rs, ctx);
1533 insns_start = ctx->ninsns;
1534 emit(rv_lwu(rd, 0, RV_REG_T1), ctx);
1535 insn_len = ctx->ninsns - insns_start;
1536 if (insn_is_zext(&insn[1]))
1540 if (is_12b_int(off)) {
1541 insns_start = ctx->ninsns;
1542 emit_ld(rd, off, rs, ctx);
1543 insn_len = ctx->ninsns - insns_start;
1547 emit_imm(RV_REG_T1, off, ctx);
1548 emit_add(RV_REG_T1, RV_REG_T1, rs, ctx);
1549 insns_start = ctx->ninsns;
1550 emit_ld(rd, 0, RV_REG_T1, ctx);
1551 insn_len = ctx->ninsns - insns_start;
1555 ret = add_exception_handler(insn, ctx, rd, insn_len);
1560 /* speculation barrier */
1561 case BPF_ST | BPF_NOSPEC:
1564 /* ST: *(size *)(dst + off) = imm */
1565 case BPF_ST | BPF_MEM | BPF_B:
1566 emit_imm(RV_REG_T1, imm, ctx);
1567 if (is_12b_int(off)) {
1568 emit(rv_sb(rd, off, RV_REG_T1), ctx);
1572 emit_imm(RV_REG_T2, off, ctx);
1573 emit_add(RV_REG_T2, RV_REG_T2, rd, ctx);
1574 emit(rv_sb(RV_REG_T2, 0, RV_REG_T1), ctx);
1577 case BPF_ST | BPF_MEM | BPF_H:
1578 emit_imm(RV_REG_T1, imm, ctx);
1579 if (is_12b_int(off)) {
1580 emit(rv_sh(rd, off, RV_REG_T1), ctx);
1584 emit_imm(RV_REG_T2, off, ctx);
1585 emit_add(RV_REG_T2, RV_REG_T2, rd, ctx);
1586 emit(rv_sh(RV_REG_T2, 0, RV_REG_T1), ctx);
1588 case BPF_ST | BPF_MEM | BPF_W:
1589 emit_imm(RV_REG_T1, imm, ctx);
1590 if (is_12b_int(off)) {
1591 emit_sw(rd, off, RV_REG_T1, ctx);
1595 emit_imm(RV_REG_T2, off, ctx);
1596 emit_add(RV_REG_T2, RV_REG_T2, rd, ctx);
1597 emit_sw(RV_REG_T2, 0, RV_REG_T1, ctx);
1599 case BPF_ST | BPF_MEM | BPF_DW:
1600 emit_imm(RV_REG_T1, imm, ctx);
1601 if (is_12b_int(off)) {
1602 emit_sd(rd, off, RV_REG_T1, ctx);
1606 emit_imm(RV_REG_T2, off, ctx);
1607 emit_add(RV_REG_T2, RV_REG_T2, rd, ctx);
1608 emit_sd(RV_REG_T2, 0, RV_REG_T1, ctx);
1611 /* STX: *(size *)(dst + off) = src */
1612 case BPF_STX | BPF_MEM | BPF_B:
1613 if (is_12b_int(off)) {
1614 emit(rv_sb(rd, off, rs), ctx);
1618 emit_imm(RV_REG_T1, off, ctx);
1619 emit_add(RV_REG_T1, RV_REG_T1, rd, ctx);
1620 emit(rv_sb(RV_REG_T1, 0, rs), ctx);
1622 case BPF_STX | BPF_MEM | BPF_H:
1623 if (is_12b_int(off)) {
1624 emit(rv_sh(rd, off, rs), ctx);
1628 emit_imm(RV_REG_T1, off, ctx);
1629 emit_add(RV_REG_T1, RV_REG_T1, rd, ctx);
1630 emit(rv_sh(RV_REG_T1, 0, rs), ctx);
1632 case BPF_STX | BPF_MEM | BPF_W:
1633 if (is_12b_int(off)) {
1634 emit_sw(rd, off, rs, ctx);
1638 emit_imm(RV_REG_T1, off, ctx);
1639 emit_add(RV_REG_T1, RV_REG_T1, rd, ctx);
1640 emit_sw(RV_REG_T1, 0, rs, ctx);
1642 case BPF_STX | BPF_MEM | BPF_DW:
1643 if (is_12b_int(off)) {
1644 emit_sd(rd, off, rs, ctx);
1648 emit_imm(RV_REG_T1, off, ctx);
1649 emit_add(RV_REG_T1, RV_REG_T1, rd, ctx);
1650 emit_sd(RV_REG_T1, 0, rs, ctx);
1652 case BPF_STX | BPF_ATOMIC | BPF_W:
1653 case BPF_STX | BPF_ATOMIC | BPF_DW:
1654 emit_atomic(rd, rs, off, imm,
1655 BPF_SIZE(code) == BPF_DW, ctx);
1658 pr_err("bpf-jit: unknown opcode %02x\n", code);
1665 void bpf_jit_build_prologue(struct rv_jit_context *ctx)
1667 int i, stack_adjust = 0, store_offset, bpf_stack_adjust;
1669 bpf_stack_adjust = round_up(ctx->prog->aux->stack_depth, 16);
1670 if (bpf_stack_adjust)
1673 if (seen_reg(RV_REG_RA, ctx))
1675 stack_adjust += 8; /* RV_REG_FP */
1676 if (seen_reg(RV_REG_S1, ctx))
1678 if (seen_reg(RV_REG_S2, ctx))
1680 if (seen_reg(RV_REG_S3, ctx))
1682 if (seen_reg(RV_REG_S4, ctx))
1684 if (seen_reg(RV_REG_S5, ctx))
1686 if (seen_reg(RV_REG_S6, ctx))
1689 stack_adjust = round_up(stack_adjust, 16);
1690 stack_adjust += bpf_stack_adjust;
1692 store_offset = stack_adjust - 8;
1694 /* reserve 4 nop insns */
1695 for (i = 0; i < 4; i++)
1696 emit(rv_nop(), ctx);
1698 /* First instruction is always setting the tail-call-counter
1699 * (TCC) register. This instruction is skipped for tail calls.
1700 * Force using a 4-byte (non-compressed) instruction.
1702 emit(rv_addi(RV_REG_TCC, RV_REG_ZERO, MAX_TAIL_CALL_CNT), ctx);
1704 emit_addi(RV_REG_SP, RV_REG_SP, -stack_adjust, ctx);
1706 if (seen_reg(RV_REG_RA, ctx)) {
1707 emit_sd(RV_REG_SP, store_offset, RV_REG_RA, ctx);
1710 emit_sd(RV_REG_SP, store_offset, RV_REG_FP, ctx);
1712 if (seen_reg(RV_REG_S1, ctx)) {
1713 emit_sd(RV_REG_SP, store_offset, RV_REG_S1, ctx);
1716 if (seen_reg(RV_REG_S2, ctx)) {
1717 emit_sd(RV_REG_SP, store_offset, RV_REG_S2, ctx);
1720 if (seen_reg(RV_REG_S3, ctx)) {
1721 emit_sd(RV_REG_SP, store_offset, RV_REG_S3, ctx);
1724 if (seen_reg(RV_REG_S4, ctx)) {
1725 emit_sd(RV_REG_SP, store_offset, RV_REG_S4, ctx);
1728 if (seen_reg(RV_REG_S5, ctx)) {
1729 emit_sd(RV_REG_SP, store_offset, RV_REG_S5, ctx);
1732 if (seen_reg(RV_REG_S6, ctx)) {
1733 emit_sd(RV_REG_SP, store_offset, RV_REG_S6, ctx);
1737 emit_addi(RV_REG_FP, RV_REG_SP, stack_adjust, ctx);
1739 if (bpf_stack_adjust)
1740 emit_addi(RV_REG_S5, RV_REG_SP, bpf_stack_adjust, ctx);
1742 /* Program contains calls and tail calls, so RV_REG_TCC need
1743 * to be saved across calls.
1745 if (seen_tail_call(ctx) && seen_call(ctx))
1746 emit_mv(RV_REG_TCC_SAVED, RV_REG_TCC, ctx);
1748 ctx->stack_size = stack_adjust;
1751 void bpf_jit_build_epilogue(struct rv_jit_context *ctx)
1753 __build_epilogue(false, ctx);