1 // SPDX-License-Identifier: GPL-2.0-only
3 * RISC-V specific functions to support DMA for non-coherent devices
5 * Copyright (c) 2021 Western Digital Corporation or its affiliates.
8 #include <linux/dma-direct.h>
9 #include <linux/dma-map-ops.h>
11 #include <asm/cacheflush.h>
12 #include <asm/dma-noncoherent.h>
14 static bool noncoherent_supported __ro_after_init;
15 int dma_cache_alignment __ro_after_init = ARCH_DMA_MINALIGN;
16 EXPORT_SYMBOL_GPL(dma_cache_alignment);
18 struct riscv_nonstd_cache_ops noncoherent_cache_ops __ro_after_init = {
24 static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size)
26 void *vaddr = phys_to_virt(paddr);
28 #ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
29 if (unlikely(noncoherent_cache_ops.wback)) {
30 noncoherent_cache_ops.wback(paddr, size);
34 ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);
37 static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size)
39 void *vaddr = phys_to_virt(paddr);
41 #ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
42 if (unlikely(noncoherent_cache_ops.inv)) {
43 noncoherent_cache_ops.inv(paddr, size);
48 ALT_CMO_OP(inval, vaddr, size, riscv_cbom_block_size);
51 static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size)
53 void *vaddr = phys_to_virt(paddr);
55 #ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
56 if (unlikely(noncoherent_cache_ops.wback_inv)) {
57 noncoherent_cache_ops.wback_inv(paddr, size);
62 ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size);
65 static inline bool arch_sync_dma_clean_before_fromdevice(void)
70 static inline bool arch_sync_dma_cpu_needs_post_dma_flush(void)
75 void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
76 enum dma_data_direction dir)
80 arch_dma_cache_wback(paddr, size);
84 if (!arch_sync_dma_clean_before_fromdevice()) {
85 arch_dma_cache_inv(paddr, size);
90 case DMA_BIDIRECTIONAL:
91 /* Skip the invalidate here if it's done later */
92 if (IS_ENABLED(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) &&
93 arch_sync_dma_cpu_needs_post_dma_flush())
94 arch_dma_cache_wback(paddr, size);
96 arch_dma_cache_wback_inv(paddr, size);
104 void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
105 enum dma_data_direction dir)
111 case DMA_FROM_DEVICE:
112 case DMA_BIDIRECTIONAL:
113 /* FROM_DEVICE invalidate needed if speculative CPU prefetch only */
114 if (arch_sync_dma_cpu_needs_post_dma_flush())
115 arch_dma_cache_inv(paddr, size);
123 void arch_dma_prep_coherent(struct page *page, size_t size)
125 void *flush_addr = page_address(page);
127 #ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
128 if (unlikely(noncoherent_cache_ops.wback_inv)) {
129 noncoherent_cache_ops.wback_inv(page_to_phys(page), size);
134 ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size);
137 void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
138 const struct iommu_ops *iommu, bool coherent)
140 WARN_TAINT(!coherent && riscv_cbom_block_size > ARCH_DMA_MINALIGN,
141 TAINT_CPU_OUT_OF_SPEC,
142 "%s %s: ARCH_DMA_MINALIGN smaller than riscv,cbom-block-size (%d < %d)",
143 dev_driver_string(dev), dev_name(dev),
144 ARCH_DMA_MINALIGN, riscv_cbom_block_size);
146 WARN_TAINT(!coherent && !noncoherent_supported, TAINT_CPU_OUT_OF_SPEC,
147 "%s %s: device non-coherent but no non-coherent operations supported",
148 dev_driver_string(dev), dev_name(dev));
150 dev->dma_coherent = coherent;
153 void riscv_noncoherent_supported(void)
155 WARN(!riscv_cbom_block_size,
156 "Non-coherent DMA support enabled without a block size\n");
157 noncoherent_supported = true;
160 void __init riscv_set_dma_cache_alignment(void)
162 if (!noncoherent_supported)
163 dma_cache_alignment = 1;
166 void riscv_noncoherent_register_cache_ops(const struct riscv_nonstd_cache_ops *ops)
171 noncoherent_cache_ops = *ops;
173 EXPORT_SYMBOL_GPL(riscv_noncoherent_register_cache_ops);