1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2022 Ventana Micro Systems Inc.
6 #include <linux/bitmap.h>
7 #include <linux/cpumask.h>
8 #include <linux/errno.h>
10 #include <linux/module.h>
11 #include <linux/smp.h>
12 #include <linux/kvm_host.h>
13 #include <asm/cacheflush.h>
15 #include <asm/hwcap.h>
16 #include <asm/insn-def.h>
18 #define has_svinval() \
19 static_branch_unlikely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_SVINVAL])
21 void kvm_riscv_local_hfence_gvma_vmid_gpa(unsigned long vmid,
22 gpa_t gpa, gpa_t gpsz,
27 if (PTRS_PER_PTE < (gpsz >> order)) {
28 kvm_riscv_local_hfence_gvma_vmid_all(vmid);
33 asm volatile (SFENCE_W_INVAL() ::: "memory");
34 for (pos = gpa; pos < (gpa + gpsz); pos += BIT(order))
35 asm volatile (HINVAL_GVMA(%0, %1)
36 : : "r" (pos >> 2), "r" (vmid) : "memory");
37 asm volatile (SFENCE_INVAL_IR() ::: "memory");
39 for (pos = gpa; pos < (gpa + gpsz); pos += BIT(order))
40 asm volatile (HFENCE_GVMA(%0, %1)
41 : : "r" (pos >> 2), "r" (vmid) : "memory");
45 void kvm_riscv_local_hfence_gvma_vmid_all(unsigned long vmid)
47 asm volatile(HFENCE_GVMA(zero, %0) : : "r" (vmid) : "memory");
50 void kvm_riscv_local_hfence_gvma_gpa(gpa_t gpa, gpa_t gpsz,
55 if (PTRS_PER_PTE < (gpsz >> order)) {
56 kvm_riscv_local_hfence_gvma_all();
61 asm volatile (SFENCE_W_INVAL() ::: "memory");
62 for (pos = gpa; pos < (gpa + gpsz); pos += BIT(order))
63 asm volatile(HINVAL_GVMA(%0, zero)
64 : : "r" (pos >> 2) : "memory");
65 asm volatile (SFENCE_INVAL_IR() ::: "memory");
67 for (pos = gpa; pos < (gpa + gpsz); pos += BIT(order))
68 asm volatile(HFENCE_GVMA(%0, zero)
69 : : "r" (pos >> 2) : "memory");
73 void kvm_riscv_local_hfence_gvma_all(void)
75 asm volatile(HFENCE_GVMA(zero, zero) : : : "memory");
78 void kvm_riscv_local_hfence_vvma_asid_gva(unsigned long vmid,
84 unsigned long pos, hgatp;
86 if (PTRS_PER_PTE < (gvsz >> order)) {
87 kvm_riscv_local_hfence_vvma_asid_all(vmid, asid);
91 hgatp = csr_swap(CSR_HGATP, vmid << HGATP_VMID_SHIFT);
94 asm volatile (SFENCE_W_INVAL() ::: "memory");
95 for (pos = gva; pos < (gva + gvsz); pos += BIT(order))
96 asm volatile(HINVAL_VVMA(%0, %1)
97 : : "r" (pos), "r" (asid) : "memory");
98 asm volatile (SFENCE_INVAL_IR() ::: "memory");
100 for (pos = gva; pos < (gva + gvsz); pos += BIT(order))
101 asm volatile(HFENCE_VVMA(%0, %1)
102 : : "r" (pos), "r" (asid) : "memory");
105 csr_write(CSR_HGATP, hgatp);
108 void kvm_riscv_local_hfence_vvma_asid_all(unsigned long vmid,
113 hgatp = csr_swap(CSR_HGATP, vmid << HGATP_VMID_SHIFT);
115 asm volatile(HFENCE_VVMA(zero, %0) : : "r" (asid) : "memory");
117 csr_write(CSR_HGATP, hgatp);
120 void kvm_riscv_local_hfence_vvma_gva(unsigned long vmid,
121 unsigned long gva, unsigned long gvsz,
124 unsigned long pos, hgatp;
126 if (PTRS_PER_PTE < (gvsz >> order)) {
127 kvm_riscv_local_hfence_vvma_all(vmid);
131 hgatp = csr_swap(CSR_HGATP, vmid << HGATP_VMID_SHIFT);
134 asm volatile (SFENCE_W_INVAL() ::: "memory");
135 for (pos = gva; pos < (gva + gvsz); pos += BIT(order))
136 asm volatile(HINVAL_VVMA(%0, zero)
137 : : "r" (pos) : "memory");
138 asm volatile (SFENCE_INVAL_IR() ::: "memory");
140 for (pos = gva; pos < (gva + gvsz); pos += BIT(order))
141 asm volatile(HFENCE_VVMA(%0, zero)
142 : : "r" (pos) : "memory");
145 csr_write(CSR_HGATP, hgatp);
148 void kvm_riscv_local_hfence_vvma_all(unsigned long vmid)
152 hgatp = csr_swap(CSR_HGATP, vmid << HGATP_VMID_SHIFT);
154 asm volatile(HFENCE_VVMA(zero, zero) : : : "memory");
156 csr_write(CSR_HGATP, hgatp);
159 void kvm_riscv_local_tlb_sanitize(struct kvm_vcpu *vcpu)
163 if (!kvm_riscv_gstage_vmid_bits() ||
164 vcpu->arch.last_exit_cpu == vcpu->cpu)
168 * On RISC-V platforms with hardware VMID support, we share same
169 * VMID for all VCPUs of a particular Guest/VM. This means we might
170 * have stale G-stage TLB entries on the current Host CPU due to
171 * some other VCPU of the same Guest which ran previously on the
174 * To cleanup stale TLB entries, we simply flush all G-stage TLB
175 * entries by VMID whenever underlying Host CPU changes for a VCPU.
178 vmid = READ_ONCE(vcpu->kvm->arch.vmid.vmid);
179 kvm_riscv_local_hfence_gvma_vmid_all(vmid);
182 void kvm_riscv_fence_i_process(struct kvm_vcpu *vcpu)
184 local_flush_icache_all();
187 void kvm_riscv_hfence_gvma_vmid_all_process(struct kvm_vcpu *vcpu)
189 struct kvm_vmid *vmid;
191 vmid = &vcpu->kvm->arch.vmid;
192 kvm_riscv_local_hfence_gvma_vmid_all(READ_ONCE(vmid->vmid));
195 void kvm_riscv_hfence_vvma_all_process(struct kvm_vcpu *vcpu)
197 struct kvm_vmid *vmid;
199 vmid = &vcpu->kvm->arch.vmid;
200 kvm_riscv_local_hfence_vvma_all(READ_ONCE(vmid->vmid));
203 static bool vcpu_hfence_dequeue(struct kvm_vcpu *vcpu,
204 struct kvm_riscv_hfence *out_data)
207 struct kvm_vcpu_arch *varch = &vcpu->arch;
209 spin_lock(&varch->hfence_lock);
211 if (varch->hfence_queue[varch->hfence_head].type) {
212 memcpy(out_data, &varch->hfence_queue[varch->hfence_head],
214 varch->hfence_queue[varch->hfence_head].type = 0;
216 varch->hfence_head++;
217 if (varch->hfence_head == KVM_RISCV_VCPU_MAX_HFENCE)
218 varch->hfence_head = 0;
223 spin_unlock(&varch->hfence_lock);
228 static bool vcpu_hfence_enqueue(struct kvm_vcpu *vcpu,
229 const struct kvm_riscv_hfence *data)
232 struct kvm_vcpu_arch *varch = &vcpu->arch;
234 spin_lock(&varch->hfence_lock);
236 if (!varch->hfence_queue[varch->hfence_tail].type) {
237 memcpy(&varch->hfence_queue[varch->hfence_tail],
238 data, sizeof(*data));
240 varch->hfence_tail++;
241 if (varch->hfence_tail == KVM_RISCV_VCPU_MAX_HFENCE)
242 varch->hfence_tail = 0;
247 spin_unlock(&varch->hfence_lock);
252 void kvm_riscv_hfence_process(struct kvm_vcpu *vcpu)
254 struct kvm_riscv_hfence d = { 0 };
255 struct kvm_vmid *v = &vcpu->kvm->arch.vmid;
257 while (vcpu_hfence_dequeue(vcpu, &d)) {
259 case KVM_RISCV_HFENCE_UNKNOWN:
261 case KVM_RISCV_HFENCE_GVMA_VMID_GPA:
262 kvm_riscv_local_hfence_gvma_vmid_gpa(
264 d.addr, d.size, d.order);
266 case KVM_RISCV_HFENCE_VVMA_ASID_GVA:
267 kvm_riscv_local_hfence_vvma_asid_gva(
268 READ_ONCE(v->vmid), d.asid,
269 d.addr, d.size, d.order);
271 case KVM_RISCV_HFENCE_VVMA_ASID_ALL:
272 kvm_riscv_local_hfence_vvma_asid_all(
273 READ_ONCE(v->vmid), d.asid);
275 case KVM_RISCV_HFENCE_VVMA_GVA:
276 kvm_riscv_local_hfence_vvma_gva(
278 d.addr, d.size, d.order);
286 static void make_xfence_request(struct kvm *kvm,
287 unsigned long hbase, unsigned long hmask,
288 unsigned int req, unsigned int fallback_req,
289 const struct kvm_riscv_hfence *data)
292 struct kvm_vcpu *vcpu;
293 unsigned int actual_req = req;
294 DECLARE_BITMAP(vcpu_mask, KVM_MAX_VCPUS);
296 bitmap_clear(vcpu_mask, 0, KVM_MAX_VCPUS);
297 kvm_for_each_vcpu(i, vcpu, kvm) {
299 if (vcpu->vcpu_id < hbase)
301 if (!(hmask & (1UL << (vcpu->vcpu_id - hbase))))
305 bitmap_set(vcpu_mask, i, 1);
307 if (!data || !data->type)
311 * Enqueue hfence data to VCPU hfence queue. If we don't
312 * have space in the VCPU hfence queue then fallback to
313 * a more conservative hfence request.
315 if (!vcpu_hfence_enqueue(vcpu, data))
316 actual_req = fallback_req;
319 kvm_make_vcpus_request_mask(kvm, actual_req, vcpu_mask);
322 void kvm_riscv_fence_i(struct kvm *kvm,
323 unsigned long hbase, unsigned long hmask)
325 make_xfence_request(kvm, hbase, hmask, KVM_REQ_FENCE_I,
326 KVM_REQ_FENCE_I, NULL);
329 void kvm_riscv_hfence_gvma_vmid_gpa(struct kvm *kvm,
330 unsigned long hbase, unsigned long hmask,
331 gpa_t gpa, gpa_t gpsz,
334 struct kvm_riscv_hfence data;
336 data.type = KVM_RISCV_HFENCE_GVMA_VMID_GPA;
341 make_xfence_request(kvm, hbase, hmask, KVM_REQ_HFENCE,
342 KVM_REQ_HFENCE_GVMA_VMID_ALL, &data);
345 void kvm_riscv_hfence_gvma_vmid_all(struct kvm *kvm,
346 unsigned long hbase, unsigned long hmask)
348 make_xfence_request(kvm, hbase, hmask, KVM_REQ_HFENCE_GVMA_VMID_ALL,
349 KVM_REQ_HFENCE_GVMA_VMID_ALL, NULL);
352 void kvm_riscv_hfence_vvma_asid_gva(struct kvm *kvm,
353 unsigned long hbase, unsigned long hmask,
354 unsigned long gva, unsigned long gvsz,
355 unsigned long order, unsigned long asid)
357 struct kvm_riscv_hfence data;
359 data.type = KVM_RISCV_HFENCE_VVMA_ASID_GVA;
364 make_xfence_request(kvm, hbase, hmask, KVM_REQ_HFENCE,
365 KVM_REQ_HFENCE_VVMA_ALL, &data);
368 void kvm_riscv_hfence_vvma_asid_all(struct kvm *kvm,
369 unsigned long hbase, unsigned long hmask,
372 struct kvm_riscv_hfence data;
374 data.type = KVM_RISCV_HFENCE_VVMA_ASID_ALL;
376 data.addr = data.size = data.order = 0;
377 make_xfence_request(kvm, hbase, hmask, KVM_REQ_HFENCE,
378 KVM_REQ_HFENCE_VVMA_ALL, &data);
381 void kvm_riscv_hfence_vvma_gva(struct kvm *kvm,
382 unsigned long hbase, unsigned long hmask,
383 unsigned long gva, unsigned long gvsz,
386 struct kvm_riscv_hfence data;
388 data.type = KVM_RISCV_HFENCE_VVMA_GVA;
393 make_xfence_request(kvm, hbase, hmask, KVM_REQ_HFENCE,
394 KVM_REQ_HFENCE_VVMA_ALL, &data);
397 void kvm_riscv_hfence_vvma_all(struct kvm *kvm,
398 unsigned long hbase, unsigned long hmask)
400 make_xfence_request(kvm, hbase, hmask, KVM_REQ_HFENCE_VVMA_ALL,
401 KVM_REQ_HFENCE_VVMA_ALL, NULL);