1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2021 Western Digital Corporation or its affiliates.
4 * Copyright (C) 2022 Ventana Micro Systems Inc.
7 * Anup Patel <apatel@ventanamicro.com>
10 #include <linux/kvm_host.h>
11 #include <linux/math.h>
12 #include <linux/spinlock.h>
13 #include <linux/swab.h>
14 #include <kvm/iodev.h>
15 #include <asm/kvm_aia_aplic.h>
21 #define APLIC_IRQ_STATE_PENDING BIT(0)
22 #define APLIC_IRQ_STATE_ENABLED BIT(1)
23 #define APLIC_IRQ_STATE_ENPEND (APLIC_IRQ_STATE_PENDING | \
24 APLIC_IRQ_STATE_ENABLED)
25 #define APLIC_IRQ_STATE_INPUT BIT(8)
30 struct kvm_io_device iodev;
37 struct aplic_irq *irqs;
40 static u32 aplic_read_sourcecfg(struct aplic *aplic, u32 irq)
44 struct aplic_irq *irqd;
46 if (!irq || aplic->nr_irqs <= irq)
48 irqd = &aplic->irqs[irq];
50 raw_spin_lock_irqsave(&irqd->lock, flags);
51 ret = irqd->sourcecfg;
52 raw_spin_unlock_irqrestore(&irqd->lock, flags);
57 static void aplic_write_sourcecfg(struct aplic *aplic, u32 irq, u32 val)
60 struct aplic_irq *irqd;
62 if (!irq || aplic->nr_irqs <= irq)
64 irqd = &aplic->irqs[irq];
66 if (val & APLIC_SOURCECFG_D)
69 val &= APLIC_SOURCECFG_SM_MASK;
71 raw_spin_lock_irqsave(&irqd->lock, flags);
72 irqd->sourcecfg = val;
73 raw_spin_unlock_irqrestore(&irqd->lock, flags);
76 static u32 aplic_read_target(struct aplic *aplic, u32 irq)
80 struct aplic_irq *irqd;
82 if (!irq || aplic->nr_irqs <= irq)
84 irqd = &aplic->irqs[irq];
86 raw_spin_lock_irqsave(&irqd->lock, flags);
88 raw_spin_unlock_irqrestore(&irqd->lock, flags);
93 static void aplic_write_target(struct aplic *aplic, u32 irq, u32 val)
96 struct aplic_irq *irqd;
98 if (!irq || aplic->nr_irqs <= irq)
100 irqd = &aplic->irqs[irq];
102 val &= APLIC_TARGET_EIID_MASK |
103 (APLIC_TARGET_HART_IDX_MASK << APLIC_TARGET_HART_IDX_SHIFT) |
104 (APLIC_TARGET_GUEST_IDX_MASK << APLIC_TARGET_GUEST_IDX_SHIFT);
106 raw_spin_lock_irqsave(&irqd->lock, flags);
108 raw_spin_unlock_irqrestore(&irqd->lock, flags);
111 static bool aplic_read_pending(struct aplic *aplic, u32 irq)
115 struct aplic_irq *irqd;
117 if (!irq || aplic->nr_irqs <= irq)
119 irqd = &aplic->irqs[irq];
121 raw_spin_lock_irqsave(&irqd->lock, flags);
122 ret = (irqd->state & APLIC_IRQ_STATE_PENDING) ? true : false;
123 raw_spin_unlock_irqrestore(&irqd->lock, flags);
128 static void aplic_write_pending(struct aplic *aplic, u32 irq, bool pending)
130 unsigned long flags, sm;
131 struct aplic_irq *irqd;
133 if (!irq || aplic->nr_irqs <= irq)
135 irqd = &aplic->irqs[irq];
137 raw_spin_lock_irqsave(&irqd->lock, flags);
139 sm = irqd->sourcecfg & APLIC_SOURCECFG_SM_MASK;
141 ((sm == APLIC_SOURCECFG_SM_LEVEL_HIGH) ||
142 (sm == APLIC_SOURCECFG_SM_LEVEL_LOW)))
143 goto skip_write_pending;
146 irqd->state |= APLIC_IRQ_STATE_PENDING;
148 irqd->state &= ~APLIC_IRQ_STATE_PENDING;
151 raw_spin_unlock_irqrestore(&irqd->lock, flags);
154 static bool aplic_read_enabled(struct aplic *aplic, u32 irq)
158 struct aplic_irq *irqd;
160 if (!irq || aplic->nr_irqs <= irq)
162 irqd = &aplic->irqs[irq];
164 raw_spin_lock_irqsave(&irqd->lock, flags);
165 ret = (irqd->state & APLIC_IRQ_STATE_ENABLED) ? true : false;
166 raw_spin_unlock_irqrestore(&irqd->lock, flags);
171 static void aplic_write_enabled(struct aplic *aplic, u32 irq, bool enabled)
174 struct aplic_irq *irqd;
176 if (!irq || aplic->nr_irqs <= irq)
178 irqd = &aplic->irqs[irq];
180 raw_spin_lock_irqsave(&irqd->lock, flags);
182 irqd->state |= APLIC_IRQ_STATE_ENABLED;
184 irqd->state &= ~APLIC_IRQ_STATE_ENABLED;
185 raw_spin_unlock_irqrestore(&irqd->lock, flags);
188 static bool aplic_read_input(struct aplic *aplic, u32 irq)
192 struct aplic_irq *irqd;
194 if (!irq || aplic->nr_irqs <= irq)
196 irqd = &aplic->irqs[irq];
198 raw_spin_lock_irqsave(&irqd->lock, flags);
199 ret = (irqd->state & APLIC_IRQ_STATE_INPUT) ? true : false;
200 raw_spin_unlock_irqrestore(&irqd->lock, flags);
205 static void aplic_inject_msi(struct kvm *kvm, u32 irq, u32 target)
207 u32 hart_idx, guest_idx, eiid;
209 hart_idx = target >> APLIC_TARGET_HART_IDX_SHIFT;
210 hart_idx &= APLIC_TARGET_HART_IDX_MASK;
211 guest_idx = target >> APLIC_TARGET_GUEST_IDX_SHIFT;
212 guest_idx &= APLIC_TARGET_GUEST_IDX_MASK;
213 eiid = target & APLIC_TARGET_EIID_MASK;
214 kvm_riscv_aia_inject_msi_by_id(kvm, hart_idx, guest_idx, eiid);
217 static void aplic_update_irq_range(struct kvm *kvm, u32 first, u32 last)
222 struct aplic_irq *irqd;
223 struct aplic *aplic = kvm->arch.aia.aplic_state;
225 if (!(aplic->domaincfg & APLIC_DOMAINCFG_IE))
228 for (irq = first; irq <= last; irq++) {
229 if (!irq || aplic->nr_irqs <= irq)
231 irqd = &aplic->irqs[irq];
233 raw_spin_lock_irqsave(&irqd->lock, flags);
236 target = irqd->target;
237 if ((irqd->state & APLIC_IRQ_STATE_ENPEND) ==
238 APLIC_IRQ_STATE_ENPEND) {
239 irqd->state &= ~APLIC_IRQ_STATE_PENDING;
243 raw_spin_unlock_irqrestore(&irqd->lock, flags);
246 aplic_inject_msi(kvm, irq, target);
250 int kvm_riscv_aia_aplic_inject(struct kvm *kvm, u32 source, bool level)
253 bool inject = false, ie;
255 struct aplic_irq *irqd;
256 struct aplic *aplic = kvm->arch.aia.aplic_state;
258 if (!aplic || !source || (aplic->nr_irqs <= source))
260 irqd = &aplic->irqs[source];
261 ie = (aplic->domaincfg & APLIC_DOMAINCFG_IE) ? true : false;
263 raw_spin_lock_irqsave(&irqd->lock, flags);
265 if (irqd->sourcecfg & APLIC_SOURCECFG_D)
268 switch (irqd->sourcecfg & APLIC_SOURCECFG_SM_MASK) {
269 case APLIC_SOURCECFG_SM_EDGE_RISE:
270 if (level && !(irqd->state & APLIC_IRQ_STATE_INPUT) &&
271 !(irqd->state & APLIC_IRQ_STATE_PENDING))
272 irqd->state |= APLIC_IRQ_STATE_PENDING;
274 case APLIC_SOURCECFG_SM_EDGE_FALL:
275 if (!level && (irqd->state & APLIC_IRQ_STATE_INPUT) &&
276 !(irqd->state & APLIC_IRQ_STATE_PENDING))
277 irqd->state |= APLIC_IRQ_STATE_PENDING;
279 case APLIC_SOURCECFG_SM_LEVEL_HIGH:
280 if (level && !(irqd->state & APLIC_IRQ_STATE_PENDING))
281 irqd->state |= APLIC_IRQ_STATE_PENDING;
283 case APLIC_SOURCECFG_SM_LEVEL_LOW:
284 if (!level && !(irqd->state & APLIC_IRQ_STATE_PENDING))
285 irqd->state |= APLIC_IRQ_STATE_PENDING;
290 irqd->state |= APLIC_IRQ_STATE_INPUT;
292 irqd->state &= ~APLIC_IRQ_STATE_INPUT;
294 target = irqd->target;
295 if (ie && ((irqd->state & APLIC_IRQ_STATE_ENPEND) ==
296 APLIC_IRQ_STATE_ENPEND)) {
297 irqd->state &= ~APLIC_IRQ_STATE_PENDING;
302 raw_spin_unlock_irqrestore(&irqd->lock, flags);
305 aplic_inject_msi(kvm, source, target);
310 static u32 aplic_read_input_word(struct aplic *aplic, u32 word)
314 for (i = 0; i < 32; i++)
315 ret |= aplic_read_input(aplic, word * 32 + i) ? BIT(i) : 0;
320 static u32 aplic_read_pending_word(struct aplic *aplic, u32 word)
324 for (i = 0; i < 32; i++)
325 ret |= aplic_read_pending(aplic, word * 32 + i) ? BIT(i) : 0;
330 static void aplic_write_pending_word(struct aplic *aplic, u32 word,
331 u32 val, bool pending)
335 for (i = 0; i < 32; i++) {
337 aplic_write_pending(aplic, word * 32 + i, pending);
341 static u32 aplic_read_enabled_word(struct aplic *aplic, u32 word)
345 for (i = 0; i < 32; i++)
346 ret |= aplic_read_enabled(aplic, word * 32 + i) ? BIT(i) : 0;
351 static void aplic_write_enabled_word(struct aplic *aplic, u32 word,
352 u32 val, bool enabled)
356 for (i = 0; i < 32; i++) {
358 aplic_write_enabled(aplic, word * 32 + i, enabled);
362 static int aplic_mmio_read_offset(struct kvm *kvm, gpa_t off, u32 *val32)
365 struct aplic *aplic = kvm->arch.aia.aplic_state;
367 if ((off & 0x3) != 0)
370 if (off == APLIC_DOMAINCFG) {
371 *val32 = APLIC_DOMAINCFG_RDONLY |
372 aplic->domaincfg | APLIC_DOMAINCFG_DM;
373 } else if ((off >= APLIC_SOURCECFG_BASE) &&
374 (off < (APLIC_SOURCECFG_BASE + (aplic->nr_irqs - 1) * 4))) {
375 i = ((off - APLIC_SOURCECFG_BASE) >> 2) + 1;
376 *val32 = aplic_read_sourcecfg(aplic, i);
377 } else if ((off >= APLIC_SETIP_BASE) &&
378 (off < (APLIC_SETIP_BASE + aplic->nr_words * 4))) {
379 i = (off - APLIC_SETIP_BASE) >> 2;
380 *val32 = aplic_read_pending_word(aplic, i);
381 } else if (off == APLIC_SETIPNUM) {
383 } else if ((off >= APLIC_CLRIP_BASE) &&
384 (off < (APLIC_CLRIP_BASE + aplic->nr_words * 4))) {
385 i = (off - APLIC_CLRIP_BASE) >> 2;
386 *val32 = aplic_read_input_word(aplic, i);
387 } else if (off == APLIC_CLRIPNUM) {
389 } else if ((off >= APLIC_SETIE_BASE) &&
390 (off < (APLIC_SETIE_BASE + aplic->nr_words * 4))) {
391 i = (off - APLIC_SETIE_BASE) >> 2;
392 *val32 = aplic_read_enabled_word(aplic, i);
393 } else if (off == APLIC_SETIENUM) {
395 } else if ((off >= APLIC_CLRIE_BASE) &&
396 (off < (APLIC_CLRIE_BASE + aplic->nr_words * 4))) {
398 } else if (off == APLIC_CLRIENUM) {
400 } else if (off == APLIC_SETIPNUM_LE) {
402 } else if (off == APLIC_SETIPNUM_BE) {
404 } else if (off == APLIC_GENMSI) {
405 *val32 = aplic->genmsi;
406 } else if ((off >= APLIC_TARGET_BASE) &&
407 (off < (APLIC_TARGET_BASE + (aplic->nr_irqs - 1) * 4))) {
408 i = ((off - APLIC_TARGET_BASE) >> 2) + 1;
409 *val32 = aplic_read_target(aplic, i);
416 static int aplic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
417 gpa_t addr, int len, void *val)
422 return aplic_mmio_read_offset(vcpu->kvm,
423 addr - vcpu->kvm->arch.aia.aplic_addr,
427 static int aplic_mmio_write_offset(struct kvm *kvm, gpa_t off, u32 val32)
430 struct aplic *aplic = kvm->arch.aia.aplic_state;
432 if ((off & 0x3) != 0)
435 if (off == APLIC_DOMAINCFG) {
436 /* Only IE bit writeable */
437 aplic->domaincfg = val32 & APLIC_DOMAINCFG_IE;
438 } else if ((off >= APLIC_SOURCECFG_BASE) &&
439 (off < (APLIC_SOURCECFG_BASE + (aplic->nr_irqs - 1) * 4))) {
440 i = ((off - APLIC_SOURCECFG_BASE) >> 2) + 1;
441 aplic_write_sourcecfg(aplic, i, val32);
442 } else if ((off >= APLIC_SETIP_BASE) &&
443 (off < (APLIC_SETIP_BASE + aplic->nr_words * 4))) {
444 i = (off - APLIC_SETIP_BASE) >> 2;
445 aplic_write_pending_word(aplic, i, val32, true);
446 } else if (off == APLIC_SETIPNUM) {
447 aplic_write_pending(aplic, val32, true);
448 } else if ((off >= APLIC_CLRIP_BASE) &&
449 (off < (APLIC_CLRIP_BASE + aplic->nr_words * 4))) {
450 i = (off - APLIC_CLRIP_BASE) >> 2;
451 aplic_write_pending_word(aplic, i, val32, false);
452 } else if (off == APLIC_CLRIPNUM) {
453 aplic_write_pending(aplic, val32, false);
454 } else if ((off >= APLIC_SETIE_BASE) &&
455 (off < (APLIC_SETIE_BASE + aplic->nr_words * 4))) {
456 i = (off - APLIC_SETIE_BASE) >> 2;
457 aplic_write_enabled_word(aplic, i, val32, true);
458 } else if (off == APLIC_SETIENUM) {
459 aplic_write_enabled(aplic, val32, true);
460 } else if ((off >= APLIC_CLRIE_BASE) &&
461 (off < (APLIC_CLRIE_BASE + aplic->nr_words * 4))) {
462 i = (off - APLIC_CLRIE_BASE) >> 2;
463 aplic_write_enabled_word(aplic, i, val32, false);
464 } else if (off == APLIC_CLRIENUM) {
465 aplic_write_enabled(aplic, val32, false);
466 } else if (off == APLIC_SETIPNUM_LE) {
467 aplic_write_pending(aplic, val32, true);
468 } else if (off == APLIC_SETIPNUM_BE) {
469 aplic_write_pending(aplic, __swab32(val32), true);
470 } else if (off == APLIC_GENMSI) {
471 aplic->genmsi = val32 & ~(APLIC_TARGET_GUEST_IDX_MASK <<
472 APLIC_TARGET_GUEST_IDX_SHIFT);
473 kvm_riscv_aia_inject_msi_by_id(kvm,
474 val32 >> APLIC_TARGET_HART_IDX_SHIFT, 0,
475 val32 & APLIC_TARGET_EIID_MASK);
476 } else if ((off >= APLIC_TARGET_BASE) &&
477 (off < (APLIC_TARGET_BASE + (aplic->nr_irqs - 1) * 4))) {
478 i = ((off - APLIC_TARGET_BASE) >> 2) + 1;
479 aplic_write_target(aplic, i, val32);
483 aplic_update_irq_range(kvm, 1, aplic->nr_irqs - 1);
488 static int aplic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
489 gpa_t addr, int len, const void *val)
494 return aplic_mmio_write_offset(vcpu->kvm,
495 addr - vcpu->kvm->arch.aia.aplic_addr,
496 *((const u32 *)val));
499 static struct kvm_io_device_ops aplic_iodoev_ops = {
500 .read = aplic_mmio_read,
501 .write = aplic_mmio_write,
504 int kvm_riscv_aia_aplic_set_attr(struct kvm *kvm, unsigned long type, u32 v)
508 if (!kvm->arch.aia.aplic_state)
511 rc = aplic_mmio_write_offset(kvm, type, v);
518 int kvm_riscv_aia_aplic_get_attr(struct kvm *kvm, unsigned long type, u32 *v)
522 if (!kvm->arch.aia.aplic_state)
525 rc = aplic_mmio_read_offset(kvm, type, v);
532 int kvm_riscv_aia_aplic_has_attr(struct kvm *kvm, unsigned long type)
537 if (!kvm->arch.aia.aplic_state)
540 rc = aplic_mmio_read_offset(kvm, type, &val);
547 int kvm_riscv_aia_aplic_init(struct kvm *kvm)
552 /* Do nothing if we have zero sources */
553 if (!kvm->arch.aia.nr_sources)
556 /* Allocate APLIC global state */
557 aplic = kzalloc(sizeof(*aplic), GFP_KERNEL);
560 kvm->arch.aia.aplic_state = aplic;
562 /* Setup APLIC IRQs */
563 aplic->nr_irqs = kvm->arch.aia.nr_sources + 1;
564 aplic->nr_words = DIV_ROUND_UP(aplic->nr_irqs, 32);
565 aplic->irqs = kcalloc(aplic->nr_irqs,
566 sizeof(*aplic->irqs), GFP_KERNEL);
569 goto fail_free_aplic;
571 for (i = 0; i < aplic->nr_irqs; i++)
572 raw_spin_lock_init(&aplic->irqs[i].lock);
574 /* Setup IO device */
575 kvm_iodevice_init(&aplic->iodev, &aplic_iodoev_ops);
576 mutex_lock(&kvm->slots_lock);
577 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS,
578 kvm->arch.aia.aplic_addr,
579 KVM_DEV_RISCV_APLIC_SIZE,
581 mutex_unlock(&kvm->slots_lock);
583 goto fail_free_aplic_irqs;
585 /* Setup default IRQ routing */
586 ret = kvm_riscv_setup_default_irq_routing(kvm, aplic->nr_irqs);
588 goto fail_unreg_iodev;
593 mutex_lock(&kvm->slots_lock);
594 kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &aplic->iodev);
595 mutex_unlock(&kvm->slots_lock);
596 fail_free_aplic_irqs:
599 kvm->arch.aia.aplic_state = NULL;
604 void kvm_riscv_aia_aplic_cleanup(struct kvm *kvm)
606 struct aplic *aplic = kvm->arch.aia.aplic_state;
611 mutex_lock(&kvm->slots_lock);
612 kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &aplic->iodev);
613 mutex_unlock(&kvm->slots_lock);
617 kvm->arch.aia.aplic_state = NULL;