1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copied from arch/arm64/kernel/cpufeature.c
5 * Copyright (C) 2015 ARM Ltd.
6 * Copyright (C) 2017 SiFive
9 #include <linux/bitmap.h>
10 #include <linux/ctype.h>
11 #include <linux/libfdt.h>
12 #include <linux/module.h>
14 #include <asm/alternative.h>
15 #include <asm/cacheflush.h>
16 #include <asm/errata_list.h>
17 #include <asm/hwcap.h>
18 #include <asm/patch.h>
19 #include <asm/pgtable.h>
20 #include <asm/processor.h>
22 #include <asm/switch_to.h>
24 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
26 unsigned long elf_hwcap __read_mostly;
29 static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
31 __ro_after_init DEFINE_STATIC_KEY_ARRAY_FALSE(riscv_isa_ext_keys, RISCV_ISA_EXT_KEY_MAX);
32 EXPORT_SYMBOL(riscv_isa_ext_keys);
35 * riscv_isa_extension_base() - Get base extension word
37 * @isa_bitmap: ISA bitmap to use
38 * Return: base extension word as unsigned long value
40 * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
42 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap)
48 EXPORT_SYMBOL_GPL(riscv_isa_extension_base);
51 * __riscv_isa_extension_available() - Check whether given extension
54 * @isa_bitmap: ISA bitmap to use
55 * @bit: bit position of the desired extension
56 * Return: true or false
58 * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
60 bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit)
62 const unsigned long *bmap = (isa_bitmap) ? isa_bitmap : riscv_isa;
64 if (bit >= RISCV_ISA_EXT_MAX)
67 return test_bit(bit, bmap) ? true : false;
69 EXPORT_SYMBOL_GPL(__riscv_isa_extension_available);
71 void __init riscv_fill_hwcap(void)
73 struct device_node *node;
75 char print_str[NUM_ALPHA_EXTS + 1];
77 static unsigned long isa2hwcap[256] = {0};
80 isa2hwcap['i'] = isa2hwcap['I'] = COMPAT_HWCAP_ISA_I;
81 isa2hwcap['m'] = isa2hwcap['M'] = COMPAT_HWCAP_ISA_M;
82 isa2hwcap['a'] = isa2hwcap['A'] = COMPAT_HWCAP_ISA_A;
83 isa2hwcap['f'] = isa2hwcap['F'] = COMPAT_HWCAP_ISA_F;
84 isa2hwcap['d'] = isa2hwcap['D'] = COMPAT_HWCAP_ISA_D;
85 isa2hwcap['c'] = isa2hwcap['C'] = COMPAT_HWCAP_ISA_C;
89 bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX);
91 for_each_of_cpu_node(node) {
92 unsigned long this_hwcap = 0;
93 DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);
96 rc = riscv_of_processor_hartid(node, &hartid);
100 if (of_property_read_string(node, "riscv,isa", &isa)) {
101 pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
106 #if IS_ENABLED(CONFIG_32BIT)
107 if (!strncmp(isa, "rv32", 4))
109 #elif IS_ENABLED(CONFIG_64BIT)
110 if (!strncmp(isa, "rv64", 4))
113 /* The riscv,isa DT property must start with rv64 or rv32 */
116 bitmap_zero(this_isa, RISCV_ISA_EXT_MAX);
117 for (; *isa; ++isa) {
118 const char *ext = isa++;
119 const char *ext_end = isa;
120 bool ext_long = false, ext_err = false;
125 * Workaround for invalid single-letter 's' & 'u'(QEMU).
126 * No need to set the bit in riscv_isa as 's' & 'u' are
127 * not valid ISA extensions. It works until multi-letter
128 * extension starting with "Su" appears.
130 if (ext[-1] != '_' && ext[1] == 'u') {
139 /* Multi-letter extension must be delimited */
140 for (; *isa && *isa != '_'; ++isa)
141 if (unlikely(!islower(*isa)
144 /* Parse backwards */
146 if (unlikely(ext_err))
148 if (!isdigit(ext_end[-1]))
150 /* Skip the minor version */
151 while (isdigit(*--ext_end))
153 if (ext_end[0] != 'p'
154 || !isdigit(ext_end[-1])) {
155 /* Advance it to offset the pre-decrement */
159 /* Skip the major version */
160 while (isdigit(*--ext_end))
165 if (unlikely(!islower(*ext))) {
169 /* Find next extension */
172 /* Skip the minor version */
173 while (isdigit(*++isa))
177 if (!isdigit(*++isa)) {
181 /* Skip the major version */
182 while (isdigit(*++isa))
189 #define SET_ISA_EXT_MAP(name, bit) \
191 if ((ext_end - ext == sizeof(name) - 1) && \
192 !memcmp(ext, name, sizeof(name) - 1)) \
193 set_bit(bit, this_isa); \
196 if (unlikely(ext_err))
199 this_hwcap |= isa2hwcap[(unsigned char)(*ext)];
200 set_bit(*ext - 'a', this_isa);
202 SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);
203 SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
204 SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM);
206 #undef SET_ISA_EXT_MAP
210 * All "okay" hart should have same isa. Set HWCAP based on
211 * common capabilities of every "okay" hart, in case they don't
215 elf_hwcap &= this_hwcap;
217 elf_hwcap = this_hwcap;
219 if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
220 bitmap_copy(riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
222 bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
225 /* We don't support systems with F but without D, so mask those out
227 if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) {
228 pr_info("This kernel does not support systems with F but not D\n");
229 elf_hwcap &= ~COMPAT_HWCAP_ISA_F;
232 memset(print_str, 0, sizeof(print_str));
233 for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
234 if (riscv_isa[0] & BIT_MASK(i))
235 print_str[j++] = (char)('a' + i);
236 pr_info("riscv: base ISA extensions %s\n", print_str);
238 memset(print_str, 0, sizeof(print_str));
239 for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
240 if (elf_hwcap & BIT_MASK(i))
241 print_str[j++] = (char)('a' + i);
242 pr_info("riscv: ELF capabilities %s\n", print_str);
244 for_each_set_bit(i, riscv_isa, RISCV_ISA_EXT_MAX) {
245 j = riscv_isa_ext2key(i);
247 static_branch_enable(&riscv_isa_ext_keys[j]);
251 #ifdef CONFIG_RISCV_ALTERNATIVE
252 static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
254 #ifdef CONFIG_RISCV_ISA_SVPBMT
256 case RISCV_ALTERNATIVES_EARLY_BOOT:
259 return riscv_isa_extension_available(NULL, SVPBMT);
266 static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)
268 #ifdef CONFIG_RISCV_ISA_ZICBOM
270 case RISCV_ALTERNATIVES_EARLY_BOOT:
273 if (riscv_isa_extension_available(NULL, ZICBOM)) {
274 riscv_noncoherent_supported();
286 * Probe presence of individual extensions.
288 * This code may also be executed before kernel relocation, so we cannot use
289 * addresses generated by the address-of operator as they won't be valid in
292 static u32 __init_or_module cpufeature_probe(unsigned int stage)
294 u32 cpu_req_feature = 0;
296 if (cpufeature_probe_svpbmt(stage))
297 cpu_req_feature |= (1U << CPUFEATURE_SVPBMT);
299 if (cpufeature_probe_zicbom(stage))
300 cpu_req_feature |= (1U << CPUFEATURE_ZICBOM);
302 return cpu_req_feature;
305 void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin,
306 struct alt_entry *end,
309 u32 cpu_req_feature = cpufeature_probe(stage);
310 struct alt_entry *alt;
313 for (alt = begin; alt < end; alt++) {
314 if (alt->vendor_id != 0)
316 if (alt->errata_id >= CPUFEATURE_NUMBER) {
317 WARN(1, "This feature id:%d is not in kernel cpufeature list",
322 tmp = (1U << alt->errata_id);
323 if (cpu_req_feature & tmp)
324 patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len);