1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Regents of the University of California
7 #include <linux/init.h>
8 #include <linux/seq_file.h>
11 #include <asm/hwcap.h>
14 #include <asm/pgtable.h>
17 * Returns the hart ID of the given device tree node, or -ENODEV if the node
18 * isn't an enabled and valid RISC-V hart node.
20 int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart)
24 if (!of_device_is_compatible(node, "riscv")) {
25 pr_warn("Found incompatible CPU\n");
29 *hart = (unsigned long) of_get_cpu_hwid(node, 0);
31 pr_warn("Found CPU without hart ID\n");
35 if (!of_device_is_available(node)) {
36 pr_info("CPU with hartid=%lu is not available\n", *hart);
40 if (of_property_read_string(node, "riscv,isa", &isa)) {
41 pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart);
44 if (isa[0] != 'r' || isa[1] != 'v') {
45 pr_warn("CPU with hartid=%lu has an invalid ISA of \"%s\"\n", *hart, isa);
53 * Find hart ID of the CPU DT node under which given DT node falls.
55 * To achieve this, we walk up the DT tree until we find an active
56 * RISC-V core (HART) node and extract the cpuid from it.
58 int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid)
62 for (; node; node = node->parent) {
63 if (of_device_is_compatible(node, "riscv")) {
64 rc = riscv_of_processor_hartid(node, hartid);
75 struct riscv_cpuinfo {
76 unsigned long mvendorid;
77 unsigned long marchid;
80 static DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
82 static int riscv_cpuinfo_starting(unsigned int cpu)
84 struct riscv_cpuinfo *ci = this_cpu_ptr(&riscv_cpuinfo);
86 #if IS_ENABLED(CONFIG_RISCV_SBI)
87 ci->mvendorid = sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid();
88 ci->marchid = sbi_spec_is_0_1() ? 0 : sbi_get_marchid();
89 ci->mimpid = sbi_spec_is_0_1() ? 0 : sbi_get_mimpid();
90 #elif IS_ENABLED(CONFIG_RISCV_M_MODE)
91 ci->mvendorid = csr_read(CSR_MVENDORID);
92 ci->marchid = csr_read(CSR_MARCHID);
93 ci->mimpid = csr_read(CSR_MIMPID);
103 static int __init riscv_cpuinfo_init(void)
107 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "riscv/cpuinfo:starting",
108 riscv_cpuinfo_starting, NULL);
110 pr_err("cpuinfo: failed to register hotplug callbacks.\n");
116 device_initcall(riscv_cpuinfo_init);
118 #define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \
121 .isa_ext_id = EXTID, \
124 * Here are the ordering rules of extension naming defined by RISC-V
126 * 1. All extensions should be separated from other multi-letter extensions
128 * 2. The first letter following the 'Z' conventionally indicates the most
129 * closely related alphabetical extension category, IMAFDQLCBKJTPVH.
130 * If multiple 'Z' extensions are named, they should be ordered first
131 * by category, then alphabetically within a category.
132 * 3. Standard supervisor-level extensions (starts with 'S') should be
133 * listed after standard unprivileged extensions. If multiple
134 * supervisor-level extensions are listed, they should be ordered
136 * 4. Non-standard extensions (starts with 'X') must be listed after all
137 * standard extensions. They must be separated from other multi-letter
138 * extensions by an underscore.
140 static struct riscv_isa_ext_data isa_ext_arr[] = {
141 __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
142 __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
143 __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
144 __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
145 __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
146 __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
147 __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
150 static void print_isa_ext(struct seq_file *f)
152 struct riscv_isa_ext_data *edata;
155 arr_sz = ARRAY_SIZE(isa_ext_arr) - 1;
157 /* No extension support available */
161 for (i = 0; i <= arr_sz; i++) {
162 edata = &isa_ext_arr[i];
163 if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id))
165 seq_printf(f, "_%s", edata->uprop);
170 * These are the only valid base (single letter) ISA extensions as per the spec.
171 * It also specifies the canonical order in which it appears in the spec.
172 * Some of the extension may just be a place holder for now (B, K, P, J).
173 * This should be updated once corresponding extensions are ratified.
175 static const char base_riscv_exts[13] = "imafdqcbkjpvh";
177 static void print_isa(struct seq_file *f, const char *isa)
181 seq_puts(f, "isa\t\t: ");
182 /* Print the rv[64/32] part */
183 seq_write(f, isa, 4);
184 for (i = 0; i < sizeof(base_riscv_exts); i++) {
185 if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a'))
186 /* Print only enabled the base ISA extensions */
187 seq_write(f, &base_riscv_exts[i], 1);
193 static void print_mmu(struct seq_file *f)
198 #if defined(CONFIG_32BIT)
199 strncpy(sv_type, "sv32", 5);
200 #elif defined(CONFIG_64BIT)
201 if (pgtable_l5_enabled)
202 strncpy(sv_type, "sv57", 5);
203 else if (pgtable_l4_enabled)
204 strncpy(sv_type, "sv48", 5);
206 strncpy(sv_type, "sv39", 5);
209 strncpy(sv_type, "none", 5);
210 #endif /* CONFIG_MMU */
211 seq_printf(f, "mmu\t\t: %s\n", sv_type);
214 static void *c_start(struct seq_file *m, loff_t *pos)
216 *pos = cpumask_next(*pos - 1, cpu_online_mask);
217 if ((*pos) < nr_cpu_ids)
218 return (void *)(uintptr_t)(1 + *pos);
222 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
225 return c_start(m, pos);
228 static void c_stop(struct seq_file *m, void *v)
232 static int c_show(struct seq_file *m, void *v)
234 unsigned long cpu_id = (unsigned long)v - 1;
235 struct device_node *node = of_get_cpu_node(cpu_id, NULL);
236 struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id);
237 const char *compat, *isa;
239 seq_printf(m, "processor\t: %lu\n", cpu_id);
240 seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id));
241 if (!of_property_read_string(node, "riscv,isa", &isa))
244 if (!of_property_read_string(node, "compatible", &compat)
245 && strcmp(compat, "riscv"))
246 seq_printf(m, "uarch\t\t: %s\n", compat);
247 seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid);
248 seq_printf(m, "marchid\t\t: 0x%lx\n", ci->marchid);
249 seq_printf(m, "mimpid\t\t: 0x%lx\n", ci->mimpid);
256 const struct seq_operations cpuinfo_op = {
263 #endif /* CONFIG_PROC_FS */