2 * {read,write}{b,w,l,q} based on arch/arm64/include/asm/io.h
3 * which was based on arch/arm/include/io.h
5 * Copyright (C) 1996-2000 Russell King
6 * Copyright (C) 2012 ARM Ltd.
7 * Copyright (C) 2014 Regents of the University of California
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation, version 2.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #ifndef _ASM_RISCV_IO_H
20 #define _ASM_RISCV_IO_H
22 #include <linux/types.h>
23 #include <asm/mmiowb.h>
25 extern void __iomem *ioremap(phys_addr_t offset, unsigned long size);
28 * The RISC-V ISA doesn't yet specify how to query or modify PMAs, so we can't
29 * change the properties of memory regions. This should be fixed by the
30 * upcoming platform spec.
32 #define ioremap_nocache(addr, size) ioremap((addr), (size))
33 #define ioremap_wc(addr, size) ioremap((addr), (size))
34 #define ioremap_wt(addr, size) ioremap((addr), (size))
36 extern void iounmap(volatile void __iomem *addr);
38 /* Generic IO read/write. These perform native-endian accesses. */
39 #define __raw_writeb __raw_writeb
40 static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
42 asm volatile("sb %0, 0(%1)" : : "r" (val), "r" (addr));
45 #define __raw_writew __raw_writew
46 static inline void __raw_writew(u16 val, volatile void __iomem *addr)
48 asm volatile("sh %0, 0(%1)" : : "r" (val), "r" (addr));
51 #define __raw_writel __raw_writel
52 static inline void __raw_writel(u32 val, volatile void __iomem *addr)
54 asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
58 #define __raw_writeq __raw_writeq
59 static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
61 asm volatile("sd %0, 0(%1)" : : "r" (val), "r" (addr));
65 #define __raw_readb __raw_readb
66 static inline u8 __raw_readb(const volatile void __iomem *addr)
70 asm volatile("lb %0, 0(%1)" : "=r" (val) : "r" (addr));
74 #define __raw_readw __raw_readw
75 static inline u16 __raw_readw(const volatile void __iomem *addr)
79 asm volatile("lh %0, 0(%1)" : "=r" (val) : "r" (addr));
83 #define __raw_readl __raw_readl
84 static inline u32 __raw_readl(const volatile void __iomem *addr)
88 asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
93 #define __raw_readq __raw_readq
94 static inline u64 __raw_readq(const volatile void __iomem *addr)
98 asm volatile("ld %0, 0(%1)" : "=r" (val) : "r" (addr));
104 * Unordered I/O memory access primitives. These are even more relaxed than
105 * the relaxed versions, as they don't even order accesses between successive
106 * operations to the I/O regions.
108 #define readb_cpu(c) ({ u8 __r = __raw_readb(c); __r; })
109 #define readw_cpu(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; })
110 #define readl_cpu(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
112 #define writeb_cpu(v,c) ((void)__raw_writeb((v),(c)))
113 #define writew_cpu(v,c) ((void)__raw_writew((__force u16)cpu_to_le16(v),(c)))
114 #define writel_cpu(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
117 #define readq_cpu(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; })
118 #define writeq_cpu(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
122 * Relaxed I/O memory access primitives. These follow the Device memory
123 * ordering rules but do not guarantee any ordering relative to Normal memory
124 * accesses. These are defined to order the indicated access (either a read or
125 * write) with all other I/O memory accesses. Since the platform specification
126 * defines that all I/O regions are strongly ordered on channel 2, no explicit
127 * fences are required to enforce this ordering.
129 /* FIXME: These are now the same as asm-generic */
130 #define __io_rbr() do {} while (0)
131 #define __io_rar() do {} while (0)
132 #define __io_rbw() do {} while (0)
133 #define __io_raw() do {} while (0)
135 #define readb_relaxed(c) ({ u8 __v; __io_rbr(); __v = readb_cpu(c); __io_rar(); __v; })
136 #define readw_relaxed(c) ({ u16 __v; __io_rbr(); __v = readw_cpu(c); __io_rar(); __v; })
137 #define readl_relaxed(c) ({ u32 __v; __io_rbr(); __v = readl_cpu(c); __io_rar(); __v; })
139 #define writeb_relaxed(v,c) ({ __io_rbw(); writeb_cpu((v),(c)); __io_raw(); })
140 #define writew_relaxed(v,c) ({ __io_rbw(); writew_cpu((v),(c)); __io_raw(); })
141 #define writel_relaxed(v,c) ({ __io_rbw(); writel_cpu((v),(c)); __io_raw(); })
144 #define readq_relaxed(c) ({ u64 __v; __io_rbr(); __v = readq_cpu(c); __io_rar(); __v; })
145 #define writeq_relaxed(v,c) ({ __io_rbw(); writeq_cpu((v),(c)); __io_raw(); })
149 * I/O memory access primitives. Reads are ordered relative to any
150 * following Normal memory access. Writes are ordered relative to any prior
151 * Normal memory access. The memory barriers here are necessary as RISC-V
152 * doesn't define any ordering between the memory space and the I/O space.
154 #define __io_br() do {} while (0)
155 #define __io_ar(v) __asm__ __volatile__ ("fence i,r" : : : "memory");
156 #define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory");
157 #define __io_aw() mmiowb_set_pending()
159 #define readb(c) ({ u8 __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; })
160 #define readw(c) ({ u16 __v; __io_br(); __v = readw_cpu(c); __io_ar(__v); __v; })
161 #define readl(c) ({ u32 __v; __io_br(); __v = readl_cpu(c); __io_ar(__v); __v; })
163 #define writeb(v,c) ({ __io_bw(); writeb_cpu((v),(c)); __io_aw(); })
164 #define writew(v,c) ({ __io_bw(); writew_cpu((v),(c)); __io_aw(); })
165 #define writel(v,c) ({ __io_bw(); writel_cpu((v),(c)); __io_aw(); })
168 #define readq(c) ({ u64 __v; __io_br(); __v = readq_cpu(c); __io_ar(__v); __v; })
169 #define writeq(v,c) ({ __io_bw(); writeq_cpu((v),(c)); __io_aw(); })
173 * Emulation routines for the port-mapped IO space used by some PCI drivers.
174 * These are defined as being "fully synchronous", but also "not guaranteed to
175 * be fully ordered with respect to other memory and I/O operations". We're
176 * going to be on the safe side here and just make them:
177 * - Fully ordered WRT each other, by bracketing them with two fences. The
178 * outer set contains both I/O so inX is ordered with outX, while the inner just
179 * needs the type of the access (I for inX and O for outX).
180 * - Ordered in the same manner as readX/writeX WRT memory by subsuming their
182 * - Ordered WRT timer reads, so udelay and friends don't get elided by the
184 * Note that there is no way to actually enforce that outX is a non-posted
185 * operation on RISC-V, but hopefully the timer ordering constraint is
186 * sufficient to ensure this works sanely on controllers that support I/O
189 #define __io_pbr() __asm__ __volatile__ ("fence io,i" : : : "memory");
190 #define __io_par(v) __asm__ __volatile__ ("fence i,ior" : : : "memory");
191 #define __io_pbw() __asm__ __volatile__ ("fence iow,o" : : : "memory");
192 #define __io_paw() __asm__ __volatile__ ("fence o,io" : : : "memory");
194 #define inb(c) ({ u8 __v; __io_pbr(); __v = readb_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })
195 #define inw(c) ({ u16 __v; __io_pbr(); __v = readw_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })
196 #define inl(c) ({ u32 __v; __io_pbr(); __v = readl_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })
198 #define outb(v,c) ({ __io_pbw(); writeb_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
199 #define outw(v,c) ({ __io_pbw(); writew_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
200 #define outl(v,c) ({ __io_pbw(); writel_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
203 #define inq(c) ({ u64 __v; __io_pbr(); __v = readq_cpu((void*)(c)); __io_par(__v); __v; })
204 #define outq(v,c) ({ __io_pbw(); writeq_cpu((v),(void*)(c)); __io_paw(); })
208 * Accesses from a single hart to a single I/O address must be ordered. This
209 * allows us to use the raw read macros, but we still need to fence before and
210 * after the block to ensure ordering WRT other macros. These are defined to
211 * perform host-endian accesses so we use __raw instead of __cpu.
213 #define __io_reads_ins(port, ctype, len, bfence, afence) \
214 static inline void __ ## port ## len(const volatile void __iomem *addr, \
216 unsigned int count) \
220 ctype *buf = buffer; \
223 ctype x = __raw_read ## len(addr); \
230 #define __io_writes_outs(port, ctype, len, bfence, afence) \
231 static inline void __ ## port ## len(volatile void __iomem *addr, \
232 const void *buffer, \
233 unsigned int count) \
237 const ctype *buf = buffer; \
240 __raw_write ## len(*buf++, addr); \
246 __io_reads_ins(reads, u8, b, __io_br(), __io_ar(addr))
247 __io_reads_ins(reads, u16, w, __io_br(), __io_ar(addr))
248 __io_reads_ins(reads, u32, l, __io_br(), __io_ar(addr))
249 #define readsb(addr, buffer, count) __readsb(addr, buffer, count)
250 #define readsw(addr, buffer, count) __readsw(addr, buffer, count)
251 #define readsl(addr, buffer, count) __readsl(addr, buffer, count)
253 __io_reads_ins(ins, u8, b, __io_pbr(), __io_par(addr))
254 __io_reads_ins(ins, u16, w, __io_pbr(), __io_par(addr))
255 __io_reads_ins(ins, u32, l, __io_pbr(), __io_par(addr))
256 #define insb(addr, buffer, count) __insb((void __iomem *)(long)addr, buffer, count)
257 #define insw(addr, buffer, count) __insw((void __iomem *)(long)addr, buffer, count)
258 #define insl(addr, buffer, count) __insl((void __iomem *)(long)addr, buffer, count)
260 __io_writes_outs(writes, u8, b, __io_bw(), __io_aw())
261 __io_writes_outs(writes, u16, w, __io_bw(), __io_aw())
262 __io_writes_outs(writes, u32, l, __io_bw(), __io_aw())
263 #define writesb(addr, buffer, count) __writesb(addr, buffer, count)
264 #define writesw(addr, buffer, count) __writesw(addr, buffer, count)
265 #define writesl(addr, buffer, count) __writesl(addr, buffer, count)
267 __io_writes_outs(outs, u8, b, __io_pbw(), __io_paw())
268 __io_writes_outs(outs, u16, w, __io_pbw(), __io_paw())
269 __io_writes_outs(outs, u32, l, __io_pbw(), __io_paw())
270 #define outsb(addr, buffer, count) __outsb((void __iomem *)(long)addr, buffer, count)
271 #define outsw(addr, buffer, count) __outsw((void __iomem *)(long)addr, buffer, count)
272 #define outsl(addr, buffer, count) __outsl((void __iomem *)(long)addr, buffer, count)
275 __io_reads_ins(reads, u64, q, __io_br(), __io_ar(addr))
276 #define readsq(addr, buffer, count) __readsq(addr, buffer, count)
278 __io_reads_ins(ins, u64, q, __io_pbr(), __io_par(addr))
279 #define insq(addr, buffer, count) __insq((void __iomem *)addr, buffer, count)
281 __io_writes_outs(writes, u64, q, __io_bw(), __io_aw())
282 #define writesq(addr, buffer, count) __writesq(addr, buffer, count)
284 __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw())
285 #define outsq(addr, buffer, count) __outsq((void __iomem *)addr, buffer, count)
288 #include <asm-generic/io.h>
290 #endif /* _ASM_RISCV_IO_H */