2 * {read,write}{b,w,l,q} based on arch/arm64/include/asm/io.h
3 * which was based on arch/arm/include/io.h
5 * Copyright (C) 1996-2000 Russell King
6 * Copyright (C) 2012 ARM Ltd.
7 * Copyright (C) 2014 Regents of the University of California
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation, version 2.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #ifndef _ASM_RISCV_IO_H
20 #define _ASM_RISCV_IO_H
24 extern void __iomem *ioremap(phys_addr_t offset, unsigned long size);
27 * The RISC-V ISA doesn't yet specify how to query or modify PMAs, so we can't
28 * change the properties of memory regions. This should be fixed by the
29 * upcoming platform spec.
31 #define ioremap_nocache(addr, size) ioremap((addr), (size))
32 #define ioremap_wc(addr, size) ioremap((addr), (size))
33 #define ioremap_wt(addr, size) ioremap((addr), (size))
35 extern void iounmap(void __iomem *addr);
37 #endif /* CONFIG_MMU */
39 /* Generic IO read/write. These perform native-endian accesses. */
40 #define __raw_writeb __raw_writeb
41 static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
43 asm volatile("sb %0, 0(%1)" : : "r" (val), "r" (addr));
46 #define __raw_writew __raw_writew
47 static inline void __raw_writew(u16 val, volatile void __iomem *addr)
49 asm volatile("sh %0, 0(%1)" : : "r" (val), "r" (addr));
52 #define __raw_writel __raw_writel
53 static inline void __raw_writel(u32 val, volatile void __iomem *addr)
55 asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
59 #define __raw_writeq __raw_writeq
60 static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
62 asm volatile("sd %0, 0(%1)" : : "r" (val), "r" (addr));
66 #define __raw_readb __raw_readb
67 static inline u8 __raw_readb(const volatile void __iomem *addr)
71 asm volatile("lb %0, 0(%1)" : "=r" (val) : "r" (addr));
75 #define __raw_readw __raw_readw
76 static inline u16 __raw_readw(const volatile void __iomem *addr)
80 asm volatile("lh %0, 0(%1)" : "=r" (val) : "r" (addr));
84 #define __raw_readl __raw_readl
85 static inline u32 __raw_readl(const volatile void __iomem *addr)
89 asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
94 #define __raw_readq __raw_readq
95 static inline u64 __raw_readq(const volatile void __iomem *addr)
99 asm volatile("ld %0, 0(%1)" : "=r" (val) : "r" (addr));
105 * FIXME: I'm flip-flopping on whether or not we should keep this or enforce
106 * the ordering with I/O on spinlocks like PowerPC does. The worry is that
107 * drivers won't get this correct, but I also don't want to introduce a fence
108 * into the lock code that otherwise only uses AMOs (and is essentially defined
109 * by the ISA to be correct). For now I'm leaving this here: "o,w" is
110 * sufficient to ensure that all writes to the device have completed before the
111 * write to the spinlock is allowed to commit. I surmised this from reading
112 * "ACQUIRES VS I/O ACCESSES" in memory-barriers.txt.
114 #define mmiowb() __asm__ __volatile__ ("fence o,w" : : : "memory");
117 * Unordered I/O memory access primitives. These are even more relaxed than
118 * the relaxed versions, as they don't even order accesses between successive
119 * operations to the I/O regions.
121 #define readb_cpu(c) ({ u8 __r = __raw_readb(c); __r; })
122 #define readw_cpu(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; })
123 #define readl_cpu(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
125 #define writeb_cpu(v,c) ((void)__raw_writeb((v),(c)))
126 #define writew_cpu(v,c) ((void)__raw_writew((__force u16)cpu_to_le16(v),(c)))
127 #define writel_cpu(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
130 #define readq_cpu(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; })
131 #define writeq_cpu(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
135 * Relaxed I/O memory access primitives. These follow the Device memory
136 * ordering rules but do not guarantee any ordering relative to Normal memory
137 * accesses. These are defined to order the indicated access (either a read or
138 * write) with all other I/O memory accesses. Since the platform specification
139 * defines that all I/O regions are strongly ordered on channel 2, no explicit
140 * fences are required to enforce this ordering.
142 /* FIXME: These are now the same as asm-generic */
143 #define __io_rbr() do {} while (0)
144 #define __io_rar() do {} while (0)
145 #define __io_rbw() do {} while (0)
146 #define __io_raw() do {} while (0)
148 #define readb_relaxed(c) ({ u8 __v; __io_rbr(); __v = readb_cpu(c); __io_rar(); __v; })
149 #define readw_relaxed(c) ({ u16 __v; __io_rbr(); __v = readw_cpu(c); __io_rar(); __v; })
150 #define readl_relaxed(c) ({ u32 __v; __io_rbr(); __v = readl_cpu(c); __io_rar(); __v; })
152 #define writeb_relaxed(v,c) ({ __io_rbw(); writeb_cpu((v),(c)); __io_raw(); })
153 #define writew_relaxed(v,c) ({ __io_rbw(); writew_cpu((v),(c)); __io_raw(); })
154 #define writel_relaxed(v,c) ({ __io_rbw(); writel_cpu((v),(c)); __io_raw(); })
157 #define readq_relaxed(c) ({ u64 __v; __io_rbr(); __v = readq_cpu(c); __io_rar(); __v; })
158 #define writeq_relaxed(v,c) ({ __io_rbw(); writeq_cpu((v),(c)); __io_raw(); })
162 * I/O memory access primitives. Reads are ordered relative to any
163 * following Normal memory access. Writes are ordered relative to any prior
164 * Normal memory access. The memory barriers here are necessary as RISC-V
165 * doesn't define any ordering between the memory space and the I/O space.
167 #define __io_br() do {} while (0)
168 #define __io_ar() __asm__ __volatile__ ("fence i,r" : : : "memory");
169 #define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory");
170 #define __io_aw() do {} while (0)
172 #define readb(c) ({ u8 __v; __io_br(); __v = readb_cpu(c); __io_ar(); __v; })
173 #define readw(c) ({ u16 __v; __io_br(); __v = readw_cpu(c); __io_ar(); __v; })
174 #define readl(c) ({ u32 __v; __io_br(); __v = readl_cpu(c); __io_ar(); __v; })
176 #define writeb(v,c) ({ __io_bw(); writeb_cpu((v),(c)); __io_aw(); })
177 #define writew(v,c) ({ __io_bw(); writew_cpu((v),(c)); __io_aw(); })
178 #define writel(v,c) ({ __io_bw(); writel_cpu((v),(c)); __io_aw(); })
181 #define readq(c) ({ u64 __v; __io_br(); __v = readq_cpu(c); __io_ar(); __v; })
182 #define writeq(v,c) ({ __io_bw(); writeq_cpu((v),(c)); __io_aw(); })
186 * Emulation routines for the port-mapped IO space used by some PCI drivers.
187 * These are defined as being "fully synchronous", but also "not guaranteed to
188 * be fully ordered with respect to other memory and I/O operations". We're
189 * going to be on the safe side here and just make them:
190 * - Fully ordered WRT each other, by bracketing them with two fences. The
191 * outer set contains both I/O so inX is ordered with outX, while the inner just
192 * needs the type of the access (I for inX and O for outX).
193 * - Ordered in the same manner as readX/writeX WRT memory by subsuming their
195 * - Ordered WRT timer reads, so udelay and friends don't get elided by the
197 * Note that there is no way to actually enforce that outX is a non-posted
198 * operation on RISC-V, but hopefully the timer ordering constraint is
199 * sufficient to ensure this works sanely on controllers that support I/O
202 #define __io_pbr() __asm__ __volatile__ ("fence io,i" : : : "memory");
203 #define __io_par() __asm__ __volatile__ ("fence i,ior" : : : "memory");
204 #define __io_pbw() __asm__ __volatile__ ("fence iow,o" : : : "memory");
205 #define __io_paw() __asm__ __volatile__ ("fence o,io" : : : "memory");
207 #define inb(c) ({ u8 __v; __io_pbr(); __v = readb_cpu((void*)(PCI_IOBASE + (c))); __io_par(); __v; })
208 #define inw(c) ({ u16 __v; __io_pbr(); __v = readw_cpu((void*)(PCI_IOBASE + (c))); __io_par(); __v; })
209 #define inl(c) ({ u32 __v; __io_pbr(); __v = readl_cpu((void*)(PCI_IOBASE + (c))); __io_par(); __v; })
211 #define outb(v,c) ({ __io_pbw(); writeb_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
212 #define outw(v,c) ({ __io_pbw(); writew_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
213 #define outl(v,c) ({ __io_pbw(); writel_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
216 #define inq(c) ({ u64 __v; __io_pbr(); __v = readq_cpu((void*)(c)); __io_par(); __v; })
217 #define outq(v,c) ({ __io_pbw(); writeq_cpu((v),(void*)(c)); __io_paw(); })
221 * Accesses from a single hart to a single I/O address must be ordered. This
222 * allows us to use the raw read macros, but we still need to fence before and
223 * after the block to ensure ordering WRT other macros. These are defined to
224 * perform host-endian accesses so we use __raw instead of __cpu.
226 #define __io_reads_ins(port, ctype, len, bfence, afence) \
227 static inline void __ ## port ## len(const volatile void __iomem *addr, \
229 unsigned int count) \
233 ctype *buf = buffer; \
236 ctype x = __raw_read ## len(addr); \
243 #define __io_writes_outs(port, ctype, len, bfence, afence) \
244 static inline void __ ## port ## len(volatile void __iomem *addr, \
245 const void *buffer, \
246 unsigned int count) \
250 const ctype *buf = buffer; \
253 __raw_writeq(*buf++, addr); \
259 __io_reads_ins(reads, u8, b, __io_br(), __io_ar())
260 __io_reads_ins(reads, u16, w, __io_br(), __io_ar())
261 __io_reads_ins(reads, u32, l, __io_br(), __io_ar())
262 #define readsb(addr, buffer, count) __readsb(addr, buffer, count)
263 #define readsw(addr, buffer, count) __readsw(addr, buffer, count)
264 #define readsl(addr, buffer, count) __readsl(addr, buffer, count)
266 __io_reads_ins(ins, u8, b, __io_pbr(), __io_par())
267 __io_reads_ins(ins, u16, w, __io_pbr(), __io_par())
268 __io_reads_ins(ins, u32, l, __io_pbr(), __io_par())
269 #define insb(addr, buffer, count) __insb((void __iomem *)addr, buffer, count)
270 #define insw(addr, buffer, count) __insw((void __iomem *)addr, buffer, count)
271 #define insl(addr, buffer, count) __insl((void __iomem *)addr, buffer, count)
273 __io_writes_outs(writes, u8, b, __io_bw(), __io_aw())
274 __io_writes_outs(writes, u16, w, __io_bw(), __io_aw())
275 __io_writes_outs(writes, u32, l, __io_bw(), __io_aw())
276 #define writesb(addr, buffer, count) __writesb(addr, buffer, count)
277 #define writesw(addr, buffer, count) __writesw(addr, buffer, count)
278 #define writesl(addr, buffer, count) __writesl(addr, buffer, count)
280 __io_writes_outs(outs, u8, b, __io_pbw(), __io_paw())
281 __io_writes_outs(outs, u16, w, __io_pbw(), __io_paw())
282 __io_writes_outs(outs, u32, l, __io_pbw(), __io_paw())
283 #define outsb(addr, buffer, count) __outsb((void __iomem *)addr, buffer, count)
284 #define outsw(addr, buffer, count) __outsw((void __iomem *)addr, buffer, count)
285 #define outsl(addr, buffer, count) __outsl((void __iomem *)addr, buffer, count)
288 __io_reads_ins(reads, u64, q, __io_br(), __io_ar())
289 #define readsq(addr, buffer, count) __readsq(addr, buffer, count)
291 __io_reads_ins(ins, u64, q, __io_pbr(), __io_par())
292 #define insq(addr, buffer, count) __insq((void __iomem *)addr, buffer, count)
294 __io_writes_outs(writes, u64, q, __io_bw(), __io_aw())
295 #define writesq(addr, buffer, count) __writesq(addr, buffer, count)
297 __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw())
298 #define outsq(addr, buffer, count) __outsq((void __iomem *)addr, buffer, count)
301 #include <asm-generic/io.h>
303 #endif /* _ASM_RISCV_IO_H */