1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright 2022-2023 Rivos, Inc
6 #ifndef _ASM_CPUFEATURE_H
7 #define _ASM_CPUFEATURE_H
9 #include <linux/bitmap.h>
10 #include <linux/jump_label.h>
11 #include <asm/hwcap.h>
12 #include <asm/alternative-macros.h>
13 #include <asm/errno.h>
16 * These are probed via a device_initcall(), via either the SBI or directly
17 * from the corresponding CSRs.
19 struct riscv_cpuinfo {
20 unsigned long mvendorid;
21 unsigned long marchid;
25 struct riscv_isainfo {
26 DECLARE_BITMAP(isa, RISCV_ISA_EXT_MAX);
29 DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
31 DECLARE_PER_CPU(long, misaligned_access_speed);
33 /* Per-cpu ISA extensions. */
34 extern struct riscv_isainfo hart_isa[NR_CPUS];
36 void riscv_user_isa_enable(void);
38 #ifdef CONFIG_RISCV_MISALIGNED
39 bool unaligned_ctl_available(void);
40 bool check_unaligned_access_emulated(int cpu);
41 void unaligned_emulation_finish(void);
43 static inline bool unaligned_ctl_available(void)
48 static inline bool check_unaligned_access_emulated(int cpu)
53 static inline void unaligned_emulation_finish(void) {}
56 unsigned long riscv_get_elf_hwcap(void);
58 struct riscv_isa_ext_data {
59 const unsigned int id;
62 const unsigned int *subset_ext_ids;
63 const unsigned int subset_ext_size;
66 extern const struct riscv_isa_ext_data riscv_isa_ext[];
67 extern const size_t riscv_isa_ext_count;
68 extern bool riscv_isa_fallback;
70 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
72 bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, unsigned int bit);
73 #define riscv_isa_extension_available(isa_bitmap, ext) \
74 __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)
76 static __always_inline bool
77 riscv_has_extension_likely(const unsigned long ext)
79 compiletime_assert(ext < RISCV_ISA_EXT_MAX,
80 "ext must be < RISCV_ISA_EXT_MAX");
82 if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
84 ALTERNATIVE("j %l[l_no]", "nop", 0, %[ext], 1)
90 if (!__riscv_isa_extension_available(NULL, ext))
99 static __always_inline bool
100 riscv_has_extension_unlikely(const unsigned long ext)
102 compiletime_assert(ext < RISCV_ISA_EXT_MAX,
103 "ext must be < RISCV_ISA_EXT_MAX");
105 if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
107 ALTERNATIVE("nop", "j %l[l_yes]", 0, %[ext], 1)
113 if (__riscv_isa_extension_available(NULL, ext))
122 static __always_inline bool riscv_cpu_has_extension_likely(int cpu, const unsigned long ext)
124 if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_likely(ext))
127 return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);
130 static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsigned long ext)
132 if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_unlikely(ext))
135 return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);
138 DECLARE_STATIC_KEY_FALSE(fast_misaligned_access_speed_key);