arch/riscv/boot/dts/starfive/jh7100.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /*
   3  * Copyright (C) 2021 StarFive Technology Co., Ltd.
   4  * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
   5  */
   6
   7 /dts-v1/;
   8 #include <dt-bindings/clock/starfive-jh7100.h>
   9 #include <dt-bindings/reset/starfive-jh7100.h>
  10
  11 / {
  12         compatible = "starfive,jh7100";
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 U74_0: cpu@0 {
  21                         compatible = "sifive,u74-mc", "riscv";
  22                         reg = <0>;
  23                         d-cache-block-size = <64>;
  24                         d-cache-sets = <64>;
  25                         d-cache-size = <32768>;
  26                         d-tlb-sets = <1>;
  27                         d-tlb-size = <32>;
  28                         device_type = "cpu";
  29                         i-cache-block-size = <64>;
  30                         i-cache-sets = <64>;
  31                         i-cache-size = <32768>;
  32                         i-tlb-sets = <1>;
  33                         i-tlb-size = <32>;
  34                         mmu-type = "riscv,sv39";
  35                         next-level-cache = <&ccache>;
  36                         riscv,isa = "rv64imafdc";
  37                         riscv,isa-base = "rv64i";
  38                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
  39                                                "zifencei", "zihpm";
  40                         tlb-split;
  41
  42                         cpu0_intc: interrupt-controller {
  43                                 compatible = "riscv,cpu-intc";
  44                                 interrupt-controller;
  45                                 #interrupt-cells = <1>;
  46                         };
  47                 };
  48
  49                 U74_1: cpu@1 {
  50                         compatible = "sifive,u74-mc", "riscv";
  51                         reg = <1>;
  52                         d-cache-block-size = <64>;
  53                         d-cache-sets = <64>;
  54                         d-cache-size = <32768>;
  55                         d-tlb-sets = <1>;
  56                         d-tlb-size = <32>;
  57                         device_type = "cpu";
  58                         i-cache-block-size = <64>;
  59                         i-cache-sets = <64>;
  60                         i-cache-size = <32768>;
  61                         i-tlb-sets = <1>;
  62                         i-tlb-size = <32>;
  63                         mmu-type = "riscv,sv39";
  64                         next-level-cache = <&ccache>;
  65                         riscv,isa = "rv64imafdc";
  66                         riscv,isa-base = "rv64i";
  67                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
  68                                                "zifencei", "zihpm";
  69                         tlb-split;
  70
  71                         cpu1_intc: interrupt-controller {
  72                                 compatible = "riscv,cpu-intc";
  73                                 interrupt-controller;
  74                                 #interrupt-cells = <1>;
  75                         };
  76                 };
  77
  78                 cpu-map {
  79                         cluster0 {
  80                                 core0 {
  81                                         cpu = <&U74_0>;
  82                                 };
  83
  84                                 core1 {
  85                                         cpu = <&U74_1>;
  86                                 };
  87                         };
  88                 };
  89         };
  90
  91         thermal-zones {
  92                 cpu-thermal {
  93                         polling-delay-passive = <250>;
  94                         polling-delay = <15000>;
  95
  96                         thermal-sensors = <&sfctemp>;
  97
  98                         trips {
  99                                 cpu_alert0 {
 100                                         /* milliCelsius */
 101                                         temperature = <75000>;
 102                                         hysteresis = <2000>;
 103                                         type = "passive";
 104                                 };
 105
 106                                 cpu_crit {
 107                                         /* milliCelsius */
 108                                         temperature = <90000>;
 109                                         hysteresis = <2000>;
 110                                         type = "critical";
 111                                 };
 112                         };
 113                 };
 114         };
 115
 116         osc_sys: osc_sys {
 117                 compatible = "fixed-clock";
 118                 #clock-cells = <0>;
 119                 /* This value must be overridden by the board */
 120                 clock-frequency = <0>;
 121         };
 122
 123         osc_aud: osc_aud {
 124                 compatible = "fixed-clock";
 125                 #clock-cells = <0>;
 126                 /* This value must be overridden by the board */
 127                 clock-frequency = <0>;
 128         };
 129
 130         gmac_rmii_ref: gmac_rmii_ref {
 131                 compatible = "fixed-clock";
 132                 #clock-cells = <0>;
 133                 /* Should be overridden by the board when needed */
 134                 clock-frequency = <0>;
 135         };
 136
 137         gmac_gr_mii_rxclk: gmac_gr_mii_rxclk {
 138                 compatible = "fixed-clock";
 139                 #clock-cells = <0>;
 140                 /* Should be overridden by the board when needed */
 141                 clock-frequency = <0>;
 142         };
 143
 144         soc {
 145                 compatible = "simple-bus";
 146                 interrupt-parent = <&plic>;
 147                 #address-cells = <2>;
 148                 #size-cells = <2>;
 149                 dma-noncoherent;
 150                 ranges;
 151
 152                 clint: clint@2000000 {
 153                         compatible = "starfive,jh7100-clint", "sifive,clint0";
 154                         reg = <0x0 0x2000000 0x0 0x10000>;
 155                         interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
 156                                               <&cpu1_intc 3>, <&cpu1_intc 7>;
 157                 };
 158
 159                 ccache: cache-controller@2010000 {
 160                         compatible = "starfive,jh7100-ccache", "sifive,ccache0", "cache";
 161                         reg = <0x0 0x2010000 0x0 0x1000>;
 162                         interrupts = <128>, <130>, <131>, <129>;
 163                         cache-block-size = <64>;
 164                         cache-level = <2>;
 165                         cache-sets = <2048>;
 166                         cache-size = <2097152>;
 167                         cache-unified;
 168                 };
 169
 170                 plic: interrupt-controller@c000000 {
 171                         compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
 172                         reg = <0x0 0xc000000 0x0 0x4000000>;
 173                         interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
 174                                               <&cpu1_intc 11>, <&cpu1_intc 9>;
 175                         interrupt-controller;
 176                         #address-cells = <0>;
 177                         #interrupt-cells = <1>;
 178                         riscv,ndev = <133>;
 179                 };
 180
 181                 sdio0: mmc@10000000 {
 182                         compatible = "snps,dw-mshc";
 183                         reg = <0x0 0x10000000 0x0 0x10000>;
 184                         clocks = <&clkgen JH7100_CLK_SDIO0_AHB>,
 185                                  <&clkgen JH7100_CLK_SDIO0_CCLKINT_INV>;
 186                         clock-names = "biu", "ciu";
 187                         interrupts = <4>;
 188                         data-addr = <0>;
 189                         fifo-depth = <32>;
 190                         fifo-watermark-aligned;
 191                         status = "disabled";
 192                 };
 193
 194                 sdio1: mmc@10010000 {
 195                         compatible = "snps,dw-mshc";
 196                         reg = <0x0 0x10010000 0x0 0x10000>;
 197                         clocks = <&clkgen JH7100_CLK_SDIO1_AHB>,
 198                                  <&clkgen JH7100_CLK_SDIO1_CCLKINT_INV>;
 199                         clock-names = "biu", "ciu";
 200                         interrupts = <5>;
 201                         data-addr = <0>;
 202                         fifo-depth = <32>;
 203                         fifo-watermark-aligned;
 204                         status = "disabled";
 205                 };
 206
 207                 clkgen: clock-controller@11800000 {
 208                         compatible = "starfive,jh7100-clkgen";
 209                         reg = <0x0 0x11800000 0x0 0x10000>;
 210                         clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>;
 211                         clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk";
 212                         #clock-cells = <1>;
 213                 };
 214
 215                 rstgen: reset-controller@11840000 {
 216                         compatible = "starfive,jh7100-reset";
 217                         reg = <0x0 0x11840000 0x0 0x10000>;
 218                         #reset-cells = <1>;
 219                 };
 220
 221                 i2c0: i2c@118b0000 {
 222                         compatible = "snps,designware-i2c";
 223                         reg = <0x0 0x118b0000 0x0 0x10000>;
 224                         clocks = <&clkgen JH7100_CLK_I2C0_CORE>,
 225                                  <&clkgen JH7100_CLK_I2C0_APB>;
 226                         clock-names = "ref", "pclk";
 227                         resets = <&rstgen JH7100_RSTN_I2C0_APB>;
 228                         interrupts = <96>;
 229                         #address-cells = <1>;
 230                         #size-cells = <0>;
 231                         status = "disabled";
 232                 };
 233
 234                 i2c1: i2c@118c0000 {
 235                         compatible = "snps,designware-i2c";
 236                         reg = <0x0 0x118c0000 0x0 0x10000>;
 237                         clocks = <&clkgen JH7100_CLK_I2C1_CORE>,
 238                                  <&clkgen JH7100_CLK_I2C1_APB>;
 239                         clock-names = "ref", "pclk";
 240                         resets = <&rstgen JH7100_RSTN_I2C1_APB>;
 241                         interrupts = <97>;
 242                         #address-cells = <1>;
 243                         #size-cells = <0>;
 244                         status = "disabled";
 245                 };
 246
 247                 gpio: pinctrl@11910000 {
 248                         compatible = "starfive,jh7100-pinctrl";
 249                         reg = <0x0 0x11910000 0x0 0x10000>,
 250                               <0x0 0x11858000 0x0 0x1000>;
 251                         reg-names = "gpio", "padctl";
 252                         clocks = <&clkgen JH7100_CLK_GPIO_APB>;
 253                         resets = <&rstgen JH7100_RSTN_GPIO_APB>;
 254                         interrupts = <32>;
 255                         gpio-controller;
 256                         #gpio-cells = <2>;
 257                         interrupt-controller;
 258                         #interrupt-cells = <2>;
 259                 };
 260
 261                 uart2: serial@12430000 {
 262                         compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
 263                         reg = <0x0 0x12430000 0x0 0x10000>;
 264                         clocks = <&clkgen JH7100_CLK_UART2_CORE>,
 265                                  <&clkgen JH7100_CLK_UART2_APB>;
 266                         clock-names = "baudclk", "apb_pclk";
 267                         resets = <&rstgen JH7100_RSTN_UART2_APB>;
 268                         interrupts = <72>;
 269                         reg-io-width = <4>;
 270                         reg-shift = <2>;
 271                         status = "disabled";
 272                 };
 273
 274                 uart3: serial@12440000 {
 275                         compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
 276                         reg = <0x0 0x12440000 0x0 0x10000>;
 277                         clocks = <&clkgen JH7100_CLK_UART3_CORE>,
 278                                  <&clkgen JH7100_CLK_UART3_APB>;
 279                         clock-names = "baudclk", "apb_pclk";
 280                         resets = <&rstgen JH7100_RSTN_UART3_APB>;
 281                         interrupts = <73>;
 282                         reg-io-width = <4>;
 283                         reg-shift = <2>;
 284                         status = "disabled";
 285                 };
 286
 287                 i2c2: i2c@12450000 {
 288                         compatible = "snps,designware-i2c";
 289                         reg = <0x0 0x12450000 0x0 0x10000>;
 290                         clocks = <&clkgen JH7100_CLK_I2C2_CORE>,
 291                                  <&clkgen JH7100_CLK_I2C2_APB>;
 292                         clock-names = "ref", "pclk";
 293                         resets = <&rstgen JH7100_RSTN_I2C2_APB>;
 294                         interrupts = <74>;
 295                         #address-cells = <1>;
 296                         #size-cells = <0>;
 297                         status = "disabled";
 298                 };
 299
 300                 i2c3: i2c@12460000 {
 301                         compatible = "snps,designware-i2c";
 302                         reg = <0x0 0x12460000 0x0 0x10000>;
 303                         clocks = <&clkgen JH7100_CLK_I2C3_CORE>,
 304                                  <&clkgen JH7100_CLK_I2C3_APB>;
 305                         clock-names = "ref", "pclk";
 306                         resets = <&rstgen JH7100_RSTN_I2C3_APB>;
 307                         interrupts = <75>;
 308                         #address-cells = <1>;
 309                         #size-cells = <0>;
 310                         status = "disabled";
 311                 };
 312
 313                 watchdog@12480000 {
 314                         compatible = "starfive,jh7100-wdt";
 315                         reg = <0x0 0x12480000 0x0 0x10000>;
 316                         clocks = <&clkgen JH7100_CLK_WDTIMER_APB>,
 317                                  <&clkgen JH7100_CLK_WDT_CORE>;
 318                         clock-names = "apb", "core";
 319                         resets = <&rstgen JH7100_RSTN_WDTIMER_APB>,
 320                                  <&rstgen JH7100_RSTN_WDT>;
 321                 };
 322
 323                 sfctemp: temperature-sensor@124a0000 {
 324                         compatible = "starfive,jh7100-temp";
 325                         reg = <0x0 0x124a0000 0x0 0x10000>;
 326                         clocks = <&clkgen JH7100_CLK_TEMP_SENSE>,
 327                                  <&clkgen JH7100_CLK_TEMP_APB>;
 328                         clock-names = "sense", "bus";
 329                         resets = <&rstgen JH7100_RSTN_TEMP_SENSE>,
 330                                  <&rstgen JH7100_RSTN_TEMP_APB>;
 331                         reset-names = "sense", "bus";
 332                         #thermal-sensor-cells = <0>;
 333                 };
 334         };
 335 };