1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
10 model = "Microchip PolarFire SoC";
11 compatible = "microchip,mpfs";
18 compatible = "sifive,e51", "sifive,rocket0", "riscv";
20 i-cache-block-size = <64>;
22 i-cache-size = <16384>;
24 riscv,isa = "rv64imac";
25 clocks = <&clkcfg CLK_CPU>;
28 cpu0_intc: interrupt-controller {
29 #interrupt-cells = <1>;
30 compatible = "riscv,cpu-intc";
36 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
37 d-cache-block-size = <64>;
39 d-cache-size = <32768>;
43 i-cache-block-size = <64>;
45 i-cache-size = <32768>;
48 mmu-type = "riscv,sv39";
50 riscv,isa = "rv64imafdc";
51 clocks = <&clkcfg CLK_CPU>;
53 next-level-cache = <&cctrllr>;
56 cpu1_intc: interrupt-controller {
57 #interrupt-cells = <1>;
58 compatible = "riscv,cpu-intc";
64 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
65 d-cache-block-size = <64>;
67 d-cache-size = <32768>;
71 i-cache-block-size = <64>;
73 i-cache-size = <32768>;
76 mmu-type = "riscv,sv39";
78 riscv,isa = "rv64imafdc";
79 clocks = <&clkcfg CLK_CPU>;
81 next-level-cache = <&cctrllr>;
84 cpu2_intc: interrupt-controller {
85 #interrupt-cells = <1>;
86 compatible = "riscv,cpu-intc";
92 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
93 d-cache-block-size = <64>;
95 d-cache-size = <32768>;
99 i-cache-block-size = <64>;
101 i-cache-size = <32768>;
104 mmu-type = "riscv,sv39";
106 riscv,isa = "rv64imafdc";
107 clocks = <&clkcfg CLK_CPU>;
109 next-level-cache = <&cctrllr>;
112 cpu3_intc: interrupt-controller {
113 #interrupt-cells = <1>;
114 compatible = "riscv,cpu-intc";
115 interrupt-controller;
120 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
121 d-cache-block-size = <64>;
123 d-cache-size = <32768>;
127 i-cache-block-size = <64>;
129 i-cache-size = <32768>;
132 mmu-type = "riscv,sv39";
134 riscv,isa = "rv64imafdc";
135 clocks = <&clkcfg CLK_CPU>;
137 next-level-cache = <&cctrllr>;
139 cpu4_intc: interrupt-controller {
140 #interrupt-cells = <1>;
141 compatible = "riscv,cpu-intc";
142 interrupt-controller;
172 compatible = "fixed-clock";
176 syscontroller: syscontroller {
177 compatible = "microchip,mpfs-sys-controller";
182 #address-cells = <2>;
184 compatible = "simple-bus";
187 cctrllr: cache-controller@2010000 {
188 compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache";
189 reg = <0x0 0x2010000 0x0 0x1000>;
190 cache-block-size = <64>;
193 cache-size = <2097152>;
195 interrupt-parent = <&plic>;
196 interrupts = <1>, <3>, <4>, <2>;
199 clint: clint@2000000 {
200 compatible = "sifive,fu540-c000-clint", "sifive,clint0";
201 reg = <0x0 0x2000000 0x0 0xC000>;
202 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
203 <&cpu1_intc 3>, <&cpu1_intc 7>,
204 <&cpu2_intc 3>, <&cpu2_intc 7>,
205 <&cpu3_intc 3>, <&cpu3_intc 7>,
206 <&cpu4_intc 3>, <&cpu4_intc 7>;
209 plic: interrupt-controller@c000000 {
210 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
211 reg = <0x0 0xc000000 0x0 0x4000000>;
212 #address-cells = <0>;
213 #interrupt-cells = <1>;
214 interrupt-controller;
215 interrupts-extended = <&cpu0_intc 11>,
216 <&cpu1_intc 11>, <&cpu1_intc 9>,
217 <&cpu2_intc 11>, <&cpu2_intc 9>,
218 <&cpu3_intc 11>, <&cpu3_intc 9>,
219 <&cpu4_intc 11>, <&cpu4_intc 9>;
223 pdma: dma-controller@3000000 {
224 compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
225 reg = <0x0 0x3000000 0x0 0x8000>;
226 interrupt-parent = <&plic>;
227 interrupts = <5 6>, <7 8>, <9 10>, <11 12>;
232 clkcfg: clkcfg@20002000 {
233 compatible = "microchip,mpfs-clkcfg";
234 reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
239 mmuart0: serial@20000000 {
240 compatible = "ns16550a";
241 reg = <0x0 0x20000000 0x0 0x400>;
244 interrupt-parent = <&plic>;
246 current-speed = <115200>;
247 clocks = <&clkcfg CLK_MMUART0>;
248 status = "disabled"; /* Reserved for the HSS */
251 mmuart1: serial@20100000 {
252 compatible = "ns16550a";
253 reg = <0x0 0x20100000 0x0 0x400>;
256 interrupt-parent = <&plic>;
258 current-speed = <115200>;
259 clocks = <&clkcfg CLK_MMUART1>;
263 mmuart2: serial@20102000 {
264 compatible = "ns16550a";
265 reg = <0x0 0x20102000 0x0 0x400>;
268 interrupt-parent = <&plic>;
270 current-speed = <115200>;
271 clocks = <&clkcfg CLK_MMUART2>;
275 mmuart3: serial@20104000 {
276 compatible = "ns16550a";
277 reg = <0x0 0x20104000 0x0 0x400>;
280 interrupt-parent = <&plic>;
282 current-speed = <115200>;
283 clocks = <&clkcfg CLK_MMUART3>;
287 mmuart4: serial@20106000 {
288 compatible = "ns16550a";
289 reg = <0x0 0x20106000 0x0 0x400>;
292 interrupt-parent = <&plic>;
294 clocks = <&clkcfg CLK_MMUART4>;
295 current-speed = <115200>;
299 /* Common node entry for emmc/sd */
301 compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
302 reg = <0x0 0x20008000 0x0 0x1000>;
303 interrupt-parent = <&plic>;
305 clocks = <&clkcfg CLK_MMC>;
306 max-frequency = <200000000>;
311 compatible = "microchip,mpfs-spi";
312 #address-cells = <1>;
314 reg = <0x0 0x20108000 0x0 0x1000>;
315 interrupt-parent = <&plic>;
317 clocks = <&clkcfg CLK_SPI0>;
322 compatible = "microchip,mpfs-spi";
323 #address-cells = <1>;
325 reg = <0x0 0x20109000 0x0 0x1000>;
326 interrupt-parent = <&plic>;
328 clocks = <&clkcfg CLK_SPI1>;
333 compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2";
334 #address-cells = <1>;
336 reg = <0x0 0x21000000 0x0 0x1000>;
337 interrupt-parent = <&plic>;
339 clocks = <&clkcfg CLK_QSPI>;
344 compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
345 reg = <0x0 0x2010a000 0x0 0x1000>;
346 #address-cells = <1>;
348 interrupt-parent = <&plic>;
350 clocks = <&clkcfg CLK_I2C0>;
351 clock-frequency = <100000>;
356 compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
357 reg = <0x0 0x2010b000 0x0 0x1000>;
358 #address-cells = <1>;
360 interrupt-parent = <&plic>;
362 clocks = <&clkcfg CLK_I2C1>;
363 clock-frequency = <100000>;
368 compatible = "microchip,mpfs-can";
369 reg = <0x0 0x2010c000 0x0 0x1000>;
370 clocks = <&clkcfg CLK_CAN0>;
371 interrupt-parent = <&plic>;
377 compatible = "microchip,mpfs-can";
378 reg = <0x0 0x2010d000 0x0 0x1000>;
379 clocks = <&clkcfg CLK_CAN1>;
380 interrupt-parent = <&plic>;
385 mac0: ethernet@20110000 {
386 compatible = "cdns,macb";
387 reg = <0x0 0x20110000 0x0 0x2000>;
388 #address-cells = <1>;
390 interrupt-parent = <&plic>;
391 interrupts = <64>, <65>, <66>, <67>, <68>, <69>;
392 local-mac-address = [00 00 00 00 00 00];
393 clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
394 clock-names = "pclk", "hclk";
398 mac1: ethernet@20112000 {
399 compatible = "cdns,macb";
400 reg = <0x0 0x20112000 0x0 0x2000>;
401 #address-cells = <1>;
403 interrupt-parent = <&plic>;
404 interrupts = <70>, <71>, <72>, <73>, <74>, <75>;
405 local-mac-address = [00 00 00 00 00 00];
406 clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
407 clock-names = "pclk", "hclk";
411 gpio0: gpio@20120000 {
412 compatible = "microchip,mpfs-gpio";
413 reg = <0x0 0x20120000 0x0 0x1000>;
414 interrupt-parent = <&plic>;
415 interrupt-controller;
416 #interrupt-cells = <1>;
417 clocks = <&clkcfg CLK_GPIO0>;
423 gpio1: gpio@20121000 {
424 compatible = "microchip,mpfs-gpio";
425 reg = <0x0 0x20121000 0x0 0x1000>;
426 interrupt-parent = <&plic>;
427 interrupt-controller;
428 #interrupt-cells = <1>;
429 clocks = <&clkcfg CLK_GPIO1>;
435 gpio2: gpio@20122000 {
436 compatible = "microchip,mpfs-gpio";
437 reg = <0x0 0x20122000 0x0 0x1000>;
438 interrupt-parent = <&plic>;
439 interrupt-controller;
440 #interrupt-cells = <1>;
441 clocks = <&clkcfg CLK_GPIO2>;
448 compatible = "microchip,mpfs-rtc";
449 reg = <0x0 0x20124000 0x0 0x1000>;
450 interrupt-parent = <&plic>;
451 interrupts = <80>, <81>;
452 clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>;
453 clock-names = "rtc", "rtcref";
458 compatible = "microchip,mpfs-musb";
459 reg = <0x0 0x20201000 0x0 0x1000>;
460 interrupt-parent = <&plic>;
461 interrupts = <86>, <87>;
462 clocks = <&clkcfg CLK_USB>;
463 interrupt-names = "dma","mc";
467 mbox: mailbox@37020000 {
468 compatible = "microchip,mpfs-mailbox";
469 reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>;
470 interrupt-parent = <&plic>;