2 * Copyright 2011 IBM Corporation.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
10 #include <linux/types.h>
11 #include <linux/threads.h>
12 #include <linux/kernel.h>
13 #include <linux/irq.h>
14 #include <linux/debugfs.h>
15 #include <linux/smp.h>
16 #include <linux/interrupt.h>
17 #include <linux/seq_file.h>
18 #include <linux/init.h>
19 #include <linux/cpu.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
27 #include <asm/machdep.h>
29 #include <asm/errno.h>
32 #include <asm/firmware.h>
34 /* Globals common to all ICP/ICS implementations */
35 const struct icp_ops *icp_ops;
37 unsigned int xics_default_server = 0xff;
38 unsigned int xics_default_distrib_server = 0;
39 unsigned int xics_interrupt_server_size = 8;
41 DEFINE_PER_CPU(struct xics_cppr, xics_cppr);
43 struct irq_host *xics_host;
45 static LIST_HEAD(ics_list);
47 void xics_update_irq_servers(void)
50 struct device_node *np;
55 /* Find the server numbers for the boot cpu. */
56 np = of_get_cpu_node(boot_cpuid, NULL);
59 hcpuid = get_hard_smp_processor_id(boot_cpuid);
60 xics_default_server = hcpuid;
62 ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen);
68 i = ilen / sizeof(int);
70 /* Global interrupt distribution server is specified in the last
71 * entry of "ibm,ppc-interrupt-gserver#s" property. Get the last
72 * entry fom this property for current boot cpu id and use it as
73 * default distribution server
75 for (j = 0; j < i; j += 2) {
76 if (ireg[j] == hcpuid) {
77 xics_default_distrib_server = ireg[j+1];
84 /* GIQ stuff, currently only supported on RTAS setups, will have
85 * to be sorted properly for bare metal
87 void xics_set_cpu_giq(unsigned int gserver, unsigned int join)
89 #ifdef CONFIG_PPC_RTAS
93 if (!rtas_indicator_present(GLOBAL_INTERRUPT_QUEUE, NULL))
96 index = (1UL << xics_interrupt_server_size) - 1 - gserver;
98 status = rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE, index, join);
100 WARN(status < 0, "set-indicator(%d, %d, %u) returned %d\n",
101 GLOBAL_INTERRUPT_QUEUE, index, join, status);
105 void xics_setup_cpu(void)
107 icp_ops->set_priority(LOWEST_PRIORITY);
109 xics_set_cpu_giq(xics_default_distrib_server, 1);
112 void xics_mask_unknown_vec(unsigned int vec)
116 pr_err("Interrupt %u (real) is invalid, disabling it.\n", vec);
118 list_for_each_entry(ics, &ics_list, link)
119 ics->mask_unknown(ics, vec);
125 DEFINE_PER_CPU_SHARED_ALIGNED(unsigned long, xics_ipi_message);
127 irqreturn_t xics_ipi_dispatch(int cpu)
129 unsigned long *tgt = &per_cpu(xics_ipi_message, cpu);
131 mb(); /* order mmio clearing qirr */
133 if (test_and_clear_bit(PPC_MSG_CALL_FUNCTION, tgt)) {
134 smp_message_recv(PPC_MSG_CALL_FUNCTION);
136 if (test_and_clear_bit(PPC_MSG_RESCHEDULE, tgt)) {
137 smp_message_recv(PPC_MSG_RESCHEDULE);
139 if (test_and_clear_bit(PPC_MSG_CALL_FUNC_SINGLE, tgt)) {
140 smp_message_recv(PPC_MSG_CALL_FUNC_SINGLE);
142 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
143 if (test_and_clear_bit(PPC_MSG_DEBUGGER_BREAK, tgt)) {
144 smp_message_recv(PPC_MSG_DEBUGGER_BREAK);
151 static void xics_request_ipi(void)
155 ipi = irq_create_mapping(xics_host, XICS_IPI);
156 BUG_ON(ipi == NO_IRQ);
159 * IPIs are marked IRQF_DISABLED as they must run with irqs
162 irq_set_handler(ipi, handle_percpu_irq);
163 BUG_ON(request_irq(ipi, icp_ops->ipi_action,
164 IRQF_DISABLED|IRQF_PERCPU, "IPI", NULL));
167 int __init xics_smp_probe(void)
169 /* Setup message_pass callback based on which ICP is used */
170 smp_ops->message_pass = icp_ops->message_pass;
172 /* Register all the IPIs */
175 return cpumask_weight(cpu_possible_mask);
178 #endif /* CONFIG_SMP */
180 void xics_teardown_cpu(void)
182 struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
185 * we have to reset the cppr index to 0 because we're
186 * not going to return from the IPI
189 icp_ops->set_priority(0);
190 icp_ops->teardown_cpu();
193 void xics_kexec_teardown_cpu(int secondary)
197 icp_ops->flush_ipi();
200 * Some machines need to have at least one cpu in the GIQ,
201 * so leave the master cpu in the group.
204 xics_set_cpu_giq(xics_default_distrib_server, 0);
208 #ifdef CONFIG_HOTPLUG_CPU
210 /* Interrupts are disabled. */
211 void xics_migrate_irqs_away(void)
213 int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id();
214 unsigned int irq, virq;
216 /* If we used to be the default server, move to the new "boot_cpuid" */
217 if (hw_cpu == xics_default_server)
218 xics_update_irq_servers();
220 /* Reject any interrupt that was queued to us... */
221 icp_ops->set_priority(0);
223 /* Remove ourselves from the global interrupt queue */
224 xics_set_cpu_giq(xics_default_distrib_server, 0);
226 /* Allow IPIs again... */
227 icp_ops->set_priority(DEFAULT_PRIORITY);
230 struct irq_desc *desc;
231 struct irq_chip *chip;
236 /* We can't set affinity on ISA interrupts */
237 if (virq < NUM_ISA_INTERRUPTS)
239 if (irq_map[virq].host != xics_host)
241 irq = (unsigned int)irq_map[virq].hwirq;
242 /* We need to get IPIs still. */
243 if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
245 desc = irq_to_desc(virq);
246 /* We only need to migrate enabled IRQS */
247 if (!desc || !desc->action)
249 chip = irq_desc_get_chip(desc);
250 if (!chip || !chip->irq_set_affinity)
253 raw_spin_lock_irqsave(&desc->lock, flags);
255 /* Locate interrupt server */
257 ics = irq_get_chip_data(virq);
259 server = ics->get_server(ics, irq);
261 printk(KERN_ERR "%s: Can't find server for irq %d\n",
266 /* We only support delivery to all cpus or to one cpu.
267 * The irq has to be migrated only in the single cpu
270 if (server != hw_cpu)
273 /* This is expected during cpu offline. */
275 pr_warning("IRQ %u affinity broken off cpu %u\n",
278 /* Reset affinity to all cpus */
279 raw_spin_unlock_irqrestore(&desc->lock, flags);
280 irq_set_affinity(virq, cpu_all_mask);
283 raw_spin_unlock_irqrestore(&desc->lock, flags);
286 #endif /* CONFIG_HOTPLUG_CPU */
290 * For the moment we only implement delivery to all cpus or one cpu.
292 * If the requested affinity is cpu_all_mask, we set global affinity.
293 * If not we set it to the first cpu in the mask, even if multiple cpus
294 * are set. This is so things like irqbalance (which set core and package
295 * wide affinities) do the right thing.
297 int xics_get_irq_server(unsigned int virq, const struct cpumask *cpumask,
298 unsigned int strict_check)
301 if (!distribute_irqs)
302 return xics_default_server;
304 if (!cpumask_subset(cpu_possible_mask, cpumask)) {
305 int server = cpumask_first_and(cpu_online_mask, cpumask);
307 if (server < nr_cpu_ids)
308 return get_hard_smp_processor_id(server);
315 * Workaround issue with some versions of JS20 firmware that
316 * deliver interrupts to cpus which haven't been started. This
317 * happens when using the maxcpus= boot option.
319 if (cpumask_equal(cpu_online_mask, cpu_present_mask))
320 return xics_default_distrib_server;
322 return xics_default_server;
324 #endif /* CONFIG_SMP */
326 static int xics_host_match(struct irq_host *h, struct device_node *node)
328 /* IBM machines have interrupt parents of various funky types for things
329 * like vdevices, events, etc... The trick we use here is to match
330 * everything here except the legacy 8259 which is compatible "chrp,iic"
332 return !of_device_is_compatible(node, "chrp,iic");
336 static void xics_ipi_unmask(struct irq_data *d) { }
337 static void xics_ipi_mask(struct irq_data *d) { }
339 static struct irq_chip xics_ipi_chip = {
341 .irq_eoi = NULL, /* Patched at init time */
342 .irq_mask = xics_ipi_mask,
343 .irq_unmask = xics_ipi_unmask,
346 static int xics_host_map(struct irq_host *h, unsigned int virq,
351 pr_devel("xics: map virq %d, hwirq 0x%lx\n", virq, hw);
353 /* Insert the interrupt mapping into the radix tree for fast lookup */
354 irq_radix_revmap_insert(xics_host, virq, hw);
356 /* They aren't all level sensitive but we just don't really know */
357 irq_set_status_flags(virq, IRQ_LEVEL);
359 /* Don't call into ICS for IPIs */
360 if (hw == XICS_IPI) {
361 irq_set_chip_and_handler(virq, &xics_ipi_chip,
366 /* Let the ICS setup the chip data */
367 list_for_each_entry(ics, &ics_list, link)
368 if (ics->map(ics, virq) == 0)
373 static int xics_host_xlate(struct irq_host *h, struct device_node *ct,
374 const u32 *intspec, unsigned int intsize,
375 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
378 /* Current xics implementation translates everything
379 * to level. It is not technically right for MSIs but this
380 * is irrelevant at this point. We might get smarter in the future
382 *out_hwirq = intspec[0];
383 *out_flags = IRQ_TYPE_LEVEL_LOW;
388 static struct irq_host_ops xics_host_ops = {
389 .match = xics_host_match,
390 .map = xics_host_map,
391 .xlate = xics_host_xlate,
394 static void __init xics_init_host(void)
396 xics_host = irq_alloc_host(NULL, IRQ_HOST_MAP_TREE, 0, &xics_host_ops,
398 BUG_ON(xics_host == NULL);
399 irq_set_default_host(xics_host);
402 void __init xics_register_ics(struct ics *ics)
404 list_add(&ics->link, &ics_list);
407 static void __init xics_get_server_size(void)
409 struct device_node *np;
412 /* We fetch the interrupt server size from the first ICS node
415 np = of_find_compatible_node(NULL, NULL, "ibm,ppc-xics");
418 isize = of_get_property(np, "ibm,interrupt-server#-size", NULL);
421 xics_interrupt_server_size = *isize;
425 void __init xics_init(void)
429 /* Fist locate ICP */
430 #ifdef CONFIG_PPC_ICP_HV
431 if (firmware_has_feature(FW_FEATURE_LPAR))
434 #ifdef CONFIG_PPC_ICP_NATIVE
436 rc = icp_native_init();
439 pr_warning("XICS: Cannot find a Presentation Controller !\n");
443 /* Copy get_irq callback over to ppc_md */
444 ppc_md.get_irq = icp_ops->get_irq;
446 /* Patch up IPI chip EOI */
447 xics_ipi_chip.irq_eoi = icp_ops->eoi;
450 #ifdef CONFIG_PPC_ICS_RTAS
451 rc = ics_rtas_init();
454 pr_warning("XICS: Cannot find a Source Controller !\n");
456 /* Initialize common bits */
457 xics_get_server_size();
458 xics_update_irq_servers();