2 * arch/powerpc/sysdev/qe_lib/qe_ic.c
4 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
6 * Author: Li Yang <leoli@freescale.com>
7 * Based on code from Shlomi Gridish <gridish@freescale.com>
9 * QUICC ENGINE Interrupt Controller
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/errno.h>
20 #include <linux/reboot.h>
21 #include <linux/slab.h>
22 #include <linux/stddef.h>
23 #include <linux/sched.h>
24 #include <linux/signal.h>
25 #include <linux/sysdev.h>
26 #include <linux/device.h>
27 #include <linux/bootmem.h>
28 #include <linux/spinlock.h>
32 #include <asm/qe_ic.h>
36 static DEFINE_RAW_SPINLOCK(qe_ic_lock);
38 static struct qe_ic_info qe_ic_info[] = {
41 .mask_reg = QEIC_CIMR,
43 .pri_reg = QEIC_CIPWCC,
47 .mask_reg = QEIC_CIMR,
49 .pri_reg = QEIC_CIPWCC,
53 .mask_reg = QEIC_CIMR,
55 .pri_reg = QEIC_CIPWCC,
59 .mask_reg = QEIC_CIMR,
61 .pri_reg = QEIC_CIPZCC,
65 .mask_reg = QEIC_CIMR,
67 .pri_reg = QEIC_CIPZCC,
71 .mask_reg = QEIC_CIMR,
73 .pri_reg = QEIC_CIPZCC,
77 .mask_reg = QEIC_CIMR,
79 .pri_reg = QEIC_CIPZCC,
83 .mask_reg = QEIC_CIMR,
85 .pri_reg = QEIC_CIPZCC,
89 .mask_reg = QEIC_CIMR,
91 .pri_reg = QEIC_CIPZCC,
95 .mask_reg = QEIC_CRIMR,
97 .pri_reg = QEIC_CIPRTA,
101 .mask_reg = QEIC_CRIMR,
103 .pri_reg = QEIC_CIPRTB,
107 .mask_reg = QEIC_CRIMR,
109 .pri_reg = QEIC_CIPRTB,
113 .mask_reg = QEIC_CRIMR,
115 .pri_reg = QEIC_CIPRTB,
119 .mask_reg = QEIC_CRIMR,
121 .pri_reg = QEIC_CIPRTB,
125 .mask_reg = QEIC_CIMR,
127 .pri_reg = QEIC_CIPXCC,
131 .mask_reg = QEIC_CIMR,
133 .pri_reg = QEIC_CIPXCC,
137 .mask_reg = QEIC_CIMR,
139 .pri_reg = QEIC_CIPXCC,
143 .mask_reg = QEIC_CIMR,
145 .pri_reg = QEIC_CIPXCC,
149 .mask_reg = QEIC_CIMR,
151 .pri_reg = QEIC_CIPXCC,
155 .mask_reg = QEIC_CIMR,
157 .pri_reg = QEIC_CIPYCC,
161 .mask_reg = QEIC_CIMR,
163 .pri_reg = QEIC_CIPYCC,
167 .mask_reg = QEIC_CIMR,
169 .pri_reg = QEIC_CIPYCC,
173 .mask_reg = QEIC_CIMR,
175 .pri_reg = QEIC_CIPYCC,
179 static inline u32 qe_ic_read(volatile __be32 __iomem * base, unsigned int reg)
181 return in_be32(base + (reg >> 2));
184 static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg,
187 out_be32(base + (reg >> 2), value);
190 static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
192 return irq_get_chip_data(virq);
195 static inline struct qe_ic *qe_ic_from_irq_data(struct irq_data *d)
197 return irq_data_get_irq_chip_data(d);
200 static void qe_ic_unmask_irq(struct irq_data *d)
202 struct qe_ic *qe_ic = qe_ic_from_irq_data(d);
203 unsigned int src = irqd_to_hwirq(d);
207 raw_spin_lock_irqsave(&qe_ic_lock, flags);
209 temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
210 qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
211 temp | qe_ic_info[src].mask);
213 raw_spin_unlock_irqrestore(&qe_ic_lock, flags);
216 static void qe_ic_mask_irq(struct irq_data *d)
218 struct qe_ic *qe_ic = qe_ic_from_irq_data(d);
219 unsigned int src = irqd_to_hwirq(d);
223 raw_spin_lock_irqsave(&qe_ic_lock, flags);
225 temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
226 qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
227 temp & ~qe_ic_info[src].mask);
229 /* Flush the above write before enabling interrupts; otherwise,
230 * spurious interrupts will sometimes happen. To be 100% sure
231 * that the write has reached the device before interrupts are
232 * enabled, the mask register would have to be read back; however,
233 * this is not required for correctness, only to avoid wasting
234 * time on a large number of spurious interrupts. In testing,
235 * a sync reduced the observed spurious interrupts to zero.
239 raw_spin_unlock_irqrestore(&qe_ic_lock, flags);
242 static struct irq_chip qe_ic_irq_chip = {
244 .irq_unmask = qe_ic_unmask_irq,
245 .irq_mask = qe_ic_mask_irq,
246 .irq_mask_ack = qe_ic_mask_irq,
249 static int qe_ic_host_match(struct irq_host *h, struct device_node *node)
251 /* Exact match, unless qe_ic node is NULL */
252 return h->of_node == NULL || h->of_node == node;
255 static int qe_ic_host_map(struct irq_host *h, unsigned int virq,
258 struct qe_ic *qe_ic = h->host_data;
259 struct irq_chip *chip;
261 if (qe_ic_info[hw].mask == 0) {
262 printk(KERN_ERR "Can't map reserved IRQ\n");
266 chip = &qe_ic->hc_irq;
268 irq_set_chip_data(virq, qe_ic);
269 irq_set_status_flags(virq, IRQ_LEVEL);
271 irq_set_chip_and_handler(virq, chip, handle_level_irq);
276 static int qe_ic_host_xlate(struct irq_host *h, struct device_node *ct,
277 const u32 * intspec, unsigned int intsize,
278 irq_hw_number_t * out_hwirq,
279 unsigned int *out_flags)
281 *out_hwirq = intspec[0];
283 *out_flags = intspec[1];
285 *out_flags = IRQ_TYPE_NONE;
289 static struct irq_host_ops qe_ic_host_ops = {
290 .match = qe_ic_host_match,
291 .map = qe_ic_host_map,
292 .xlate = qe_ic_host_xlate,
295 /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
296 unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
300 BUG_ON(qe_ic == NULL);
302 /* get the interrupt source vector. */
303 irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26;
308 return irq_linear_revmap(qe_ic->irqhost, irq);
311 /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
312 unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
316 BUG_ON(qe_ic == NULL);
318 /* get the interrupt source vector. */
319 irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26;
324 return irq_linear_revmap(qe_ic->irqhost, irq);
327 void __init qe_ic_init(struct device_node *node, unsigned int flags,
328 void (*low_handler)(unsigned int irq, struct irq_desc *desc),
329 void (*high_handler)(unsigned int irq, struct irq_desc *desc))
333 u32 temp = 0, ret, high_active = 0;
335 ret = of_address_to_resource(node, 0, &res);
339 qe_ic = kzalloc(sizeof(*qe_ic), GFP_KERNEL);
343 qe_ic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
344 NR_QE_IC_INTS, &qe_ic_host_ops, 0);
345 if (qe_ic->irqhost == NULL) {
350 qe_ic->regs = ioremap(res.start, res.end - res.start + 1);
352 qe_ic->irqhost->host_data = qe_ic;
353 qe_ic->hc_irq = qe_ic_irq_chip;
355 qe_ic->virq_high = irq_of_parse_and_map(node, 0);
356 qe_ic->virq_low = irq_of_parse_and_map(node, 1);
358 if (qe_ic->virq_low == NO_IRQ) {
359 printk(KERN_ERR "Failed to map QE_IC low IRQ\n");
364 /* default priority scheme is grouped. If spread mode is */
365 /* required, configure cicr accordingly. */
366 if (flags & QE_IC_SPREADMODE_GRP_W)
368 if (flags & QE_IC_SPREADMODE_GRP_X)
370 if (flags & QE_IC_SPREADMODE_GRP_Y)
372 if (flags & QE_IC_SPREADMODE_GRP_Z)
374 if (flags & QE_IC_SPREADMODE_GRP_RISCA)
376 if (flags & QE_IC_SPREADMODE_GRP_RISCB)
379 /* choose destination signal for highest priority interrupt */
380 if (flags & QE_IC_HIGH_SIGNAL) {
381 temp |= (SIGNAL_HIGH << CICR_HPIT_SHIFT);
385 qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
387 irq_set_handler_data(qe_ic->virq_low, qe_ic);
388 irq_set_chained_handler(qe_ic->virq_low, low_handler);
390 if (qe_ic->virq_high != NO_IRQ &&
391 qe_ic->virq_high != qe_ic->virq_low) {
392 irq_set_handler_data(qe_ic->virq_high, qe_ic);
393 irq_set_chained_handler(qe_ic->virq_high, high_handler);
397 void qe_ic_set_highest_priority(unsigned int virq, int high)
399 struct qe_ic *qe_ic = qe_ic_from_irq(virq);
400 unsigned int src = virq_to_hw(virq);
403 temp = qe_ic_read(qe_ic->regs, QEIC_CICR);
405 temp &= ~CICR_HP_MASK;
406 temp |= src << CICR_HP_SHIFT;
408 temp &= ~CICR_HPIT_MASK;
409 temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << CICR_HPIT_SHIFT;
411 qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
414 /* Set Priority level within its group, from 1 to 8 */
415 int qe_ic_set_priority(unsigned int virq, unsigned int priority)
417 struct qe_ic *qe_ic = qe_ic_from_irq(virq);
418 unsigned int src = virq_to_hw(virq);
421 if (priority > 8 || priority == 0)
425 if (qe_ic_info[src].pri_reg == 0)
428 temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].pri_reg);
431 temp &= ~(0x7 << (32 - priority * 3));
432 temp |= qe_ic_info[src].pri_code << (32 - priority * 3);
434 temp &= ~(0x7 << (24 - priority * 3));
435 temp |= qe_ic_info[src].pri_code << (24 - priority * 3);
438 qe_ic_write(qe_ic->regs, qe_ic_info[src].pri_reg, temp);
443 /* Set a QE priority to use high irq, only priority 1~2 can use high irq */
444 int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high)
446 struct qe_ic *qe_ic = qe_ic_from_irq(virq);
447 unsigned int src = virq_to_hw(virq);
448 u32 temp, control_reg = QEIC_CICNR, shift = 0;
450 if (priority > 2 || priority == 0)
453 switch (qe_ic_info[src].pri_reg) {
455 shift = CICNR_ZCC1T_SHIFT;
458 shift = CICNR_WCC1T_SHIFT;
461 shift = CICNR_YCC1T_SHIFT;
464 shift = CICNR_XCC1T_SHIFT;
467 shift = CRICR_RTA1T_SHIFT;
468 control_reg = QEIC_CRICR;
471 shift = CRICR_RTB1T_SHIFT;
472 control_reg = QEIC_CRICR;
478 shift += (2 - priority) * 2;
479 temp = qe_ic_read(qe_ic->regs, control_reg);
480 temp &= ~(SIGNAL_MASK << shift);
481 temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << shift;
482 qe_ic_write(qe_ic->regs, control_reg, temp);
487 static struct sysdev_class qe_ic_sysclass = {
491 static struct sys_device device_qe_ic = {
493 .cls = &qe_ic_sysclass,
496 static int __init init_qe_ic_sysfs(void)
500 printk(KERN_DEBUG "Registering qe_ic with sysfs...\n");
502 rc = sysdev_class_register(&qe_ic_sysclass);
504 printk(KERN_ERR "Failed registering qe_ic sys class\n");
507 rc = sysdev_register(&device_qe_ic);
509 printk(KERN_ERR "Failed registering qe_ic sys device\n");
515 subsys_initcall(init_qe_ic_sysfs);