4 * Copyright (c) MontaVista Software, Inc. 2008.
6 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/spinlock.h>
17 #include <linux/err.h>
20 #include <linux/of_gpio.h>
21 #include <linux/gpio.h>
22 #include <linux/slab.h>
26 struct of_mm_gpio_chip mm_gc;
29 unsigned long pin_flags[QE_PIO_PINS];
30 #define QE_PIN_REQUESTED 0
32 /* shadowed data register to clear/set bits safely */
35 /* saved_regs used to restore dedicated functions */
36 struct qe_pio_regs saved_regs;
39 static inline struct qe_gpio_chip *
40 to_qe_gpio_chip(struct of_mm_gpio_chip *mm_gc)
42 return container_of(mm_gc, struct qe_gpio_chip, mm_gc);
45 static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
47 struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
48 struct qe_pio_regs __iomem *regs = mm_gc->regs;
50 qe_gc->cpdata = in_be32(®s->cpdata);
51 qe_gc->saved_regs.cpdata = qe_gc->cpdata;
52 qe_gc->saved_regs.cpdir1 = in_be32(®s->cpdir1);
53 qe_gc->saved_regs.cpdir2 = in_be32(®s->cpdir2);
54 qe_gc->saved_regs.cppar1 = in_be32(®s->cppar1);
55 qe_gc->saved_regs.cppar2 = in_be32(®s->cppar2);
56 qe_gc->saved_regs.cpodr = in_be32(®s->cpodr);
59 static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
61 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
62 struct qe_pio_regs __iomem *regs = mm_gc->regs;
63 u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
65 return in_be32(®s->cpdata) & pin_mask;
68 static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
70 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
71 struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
72 struct qe_pio_regs __iomem *regs = mm_gc->regs;
74 u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
76 spin_lock_irqsave(&qe_gc->lock, flags);
79 qe_gc->cpdata |= pin_mask;
81 qe_gc->cpdata &= ~pin_mask;
83 out_be32(®s->cpdata, qe_gc->cpdata);
85 spin_unlock_irqrestore(&qe_gc->lock, flags);
88 static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
90 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
91 struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
94 spin_lock_irqsave(&qe_gc->lock, flags);
96 __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0);
98 spin_unlock_irqrestore(&qe_gc->lock, flags);
103 static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
105 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
106 struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
109 qe_gpio_set(gc, gpio, val);
111 spin_lock_irqsave(&qe_gc->lock, flags);
113 __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);
115 spin_unlock_irqrestore(&qe_gc->lock, flags);
122 * The qe_gpio_chip name is unfortunate, we should change that to
123 * something like qe_pio_controller. Someday.
125 struct qe_gpio_chip *controller;
130 * qe_pin_request - Request a QE pin
131 * @np: device node to get a pin from
132 * @index: index of a pin in the device tree
133 * Context: non-atomic
135 * This function return qe_pin so that you could use it with the rest of
136 * the QE Pin Multiplexing API.
138 struct qe_pin *qe_pin_request(struct device_node *np, int index)
140 struct qe_pin *qe_pin;
141 struct device_node *gc;
142 struct of_gpio_chip *of_gc = NULL;
143 struct of_mm_gpio_chip *mm_gc;
144 struct qe_gpio_chip *qe_gc;
147 const void *gpio_spec;
148 const u32 *gpio_cells;
151 qe_pin = kzalloc(sizeof(*qe_pin), GFP_KERNEL);
153 pr_debug("%s: can't allocate memory\n", __func__);
154 return ERR_PTR(-ENOMEM);
157 err = of_parse_phandles_with_args(np, "gpios", "#gpio-cells", index,
160 pr_debug("%s: can't parse gpios property\n", __func__);
164 if (!of_device_is_compatible(gc, "fsl,mpc8323-qe-pario-bank")) {
165 pr_debug("%s: tried to get a non-qe pin\n", __func__);
172 pr_debug("%s: gpio controller %s isn't registered\n",
173 np->full_name, gc->full_name);
178 gpio_cells = of_get_property(gc, "#gpio-cells", &size);
179 if (!gpio_cells || size != sizeof(*gpio_cells) ||
180 *gpio_cells != of_gc->gpio_cells) {
181 pr_debug("%s: wrong #gpio-cells for %s\n",
182 np->full_name, gc->full_name);
187 err = of_gc->xlate(of_gc, np, gpio_spec, NULL);
191 mm_gc = to_of_mm_gpio_chip(&of_gc->gc);
192 qe_gc = to_qe_gpio_chip(mm_gc);
194 spin_lock_irqsave(&qe_gc->lock, flags);
196 if (test_and_set_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[err]) == 0) {
197 qe_pin->controller = qe_gc;
204 spin_unlock_irqrestore(&qe_gc->lock, flags);
212 pr_debug("%s failed with status %d\n", __func__, err);
215 EXPORT_SYMBOL(qe_pin_request);
218 * qe_pin_free - Free a pin
219 * @qe_pin: pointer to the qe_pin structure
222 * This function frees the qe_pin structure and makes a pin available
223 * for further qe_pin_request() calls.
225 void qe_pin_free(struct qe_pin *qe_pin)
227 struct qe_gpio_chip *qe_gc = qe_pin->controller;
229 const int pin = qe_pin->num;
231 spin_lock_irqsave(&qe_gc->lock, flags);
232 test_and_clear_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[pin]);
233 spin_unlock_irqrestore(&qe_gc->lock, flags);
237 EXPORT_SYMBOL(qe_pin_free);
240 * qe_pin_set_dedicated - Revert a pin to a dedicated peripheral function mode
241 * @qe_pin: pointer to the qe_pin structure
244 * This function resets a pin to a dedicated peripheral function that
245 * has been set up by the firmware.
247 void qe_pin_set_dedicated(struct qe_pin *qe_pin)
249 struct qe_gpio_chip *qe_gc = qe_pin->controller;
250 struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
251 struct qe_pio_regs *sregs = &qe_gc->saved_regs;
252 int pin = qe_pin->num;
253 u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1));
254 u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2);
255 bool second_reg = pin > (QE_PIO_PINS / 2) - 1;
258 spin_lock_irqsave(&qe_gc->lock, flags);
261 clrsetbits_be32(®s->cpdir2, mask2, sregs->cpdir2 & mask2);
262 clrsetbits_be32(®s->cppar2, mask2, sregs->cppar2 & mask2);
264 clrsetbits_be32(®s->cpdir1, mask2, sregs->cpdir1 & mask2);
265 clrsetbits_be32(®s->cppar1, mask2, sregs->cppar1 & mask2);
268 if (sregs->cpdata & mask1)
269 qe_gc->cpdata |= mask1;
271 qe_gc->cpdata &= ~mask1;
273 out_be32(®s->cpdata, qe_gc->cpdata);
274 clrsetbits_be32(®s->cpodr, mask1, sregs->cpodr & mask1);
276 spin_unlock_irqrestore(&qe_gc->lock, flags);
278 EXPORT_SYMBOL(qe_pin_set_dedicated);
281 * qe_pin_set_gpio - Set a pin to the GPIO mode
282 * @qe_pin: pointer to the qe_pin structure
285 * This function sets a pin to the GPIO mode.
287 void qe_pin_set_gpio(struct qe_pin *qe_pin)
289 struct qe_gpio_chip *qe_gc = qe_pin->controller;
290 struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
293 spin_lock_irqsave(&qe_gc->lock, flags);
295 /* Let's make it input by default, GPIO API is able to change that. */
296 __par_io_config_pin(regs, qe_pin->num, QE_PIO_DIR_IN, 0, 0, 0);
298 spin_unlock_irqrestore(&qe_gc->lock, flags);
300 EXPORT_SYMBOL(qe_pin_set_gpio);
302 static int __init qe_add_gpiochips(void)
304 struct device_node *np;
306 for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") {
308 struct qe_gpio_chip *qe_gc;
309 struct of_mm_gpio_chip *mm_gc;
310 struct of_gpio_chip *of_gc;
311 struct gpio_chip *gc;
313 qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);
319 spin_lock_init(&qe_gc->lock);
321 mm_gc = &qe_gc->mm_gc;
322 of_gc = &mm_gc->of_gc;
325 mm_gc->save_regs = qe_gpio_save_regs;
326 of_gc->gpio_cells = 2;
327 gc->ngpio = QE_PIO_PINS;
328 gc->direction_input = qe_gpio_dir_in;
329 gc->direction_output = qe_gpio_dir_out;
330 gc->get = qe_gpio_get;
331 gc->set = qe_gpio_set;
333 ret = of_mm_gpiochip_add(np, mm_gc);
338 pr_err("%s: registration failed with status %d\n",
341 /* try others anyway */
345 arch_initcall(qe_add_gpiochips);