2 * arch/powerpc/kernel/mpic.c
4 * Driver for interrupt controllers following the OpenPIC standard, the
5 * common implementation beeing IBM's MPIC. This driver also can deal
6 * with various broken implementations of this HW.
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive
20 #include <linux/types.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/irq.h>
24 #include <linux/smp.h>
25 #include <linux/interrupt.h>
26 #include <linux/bootmem.h>
27 #include <linux/spinlock.h>
28 #include <linux/pci.h>
30 #include <asm/ptrace.h>
31 #include <asm/signal.h>
33 #include <asm/pgtable.h>
35 #include <asm/machdep.h>
42 #define DBG(fmt...) printk(fmt)
47 static struct mpic *mpics;
48 static struct mpic *mpic_primary;
49 static DEFINE_SPINLOCK(mpic_lock);
51 #ifdef CONFIG_PPC32 /* XXX for now */
52 #ifdef CONFIG_IRQ_ALL_CPUS
53 #define distribute_irqs (1)
55 #define distribute_irqs (0)
59 #ifdef CONFIG_MPIC_WEIRD
60 static u32 mpic_infos[][MPIC_IDX_END] = {
61 [0] = { /* Original OpenPIC compatible MPIC */
64 MPIC_GREG_GLOBAL_CONF_0,
66 MPIC_GREG_IPI_VECTOR_PRI_0,
73 MPIC_TIMER_CURRENT_CNT,
75 MPIC_TIMER_VECTOR_PRI,
76 MPIC_TIMER_DESTINATION,
80 MPIC_CPU_IPI_DISPATCH_0,
81 MPIC_CPU_IPI_DISPATCH_STRIDE,
82 MPIC_CPU_CURRENT_TASK_PRI,
91 MPIC_VECPRI_VECTOR_MASK,
92 MPIC_VECPRI_POLARITY_POSITIVE,
93 MPIC_VECPRI_POLARITY_NEGATIVE,
94 MPIC_VECPRI_SENSE_LEVEL,
95 MPIC_VECPRI_SENSE_EDGE,
96 MPIC_VECPRI_POLARITY_MASK,
97 MPIC_VECPRI_SENSE_MASK,
100 [1] = { /* Tsi108/109 PIC */
102 TSI108_GREG_FEATURE_0,
103 TSI108_GREG_GLOBAL_CONF_0,
104 TSI108_GREG_VENDOR_ID,
105 TSI108_GREG_IPI_VECTOR_PRI_0,
106 TSI108_GREG_IPI_STRIDE,
107 TSI108_GREG_SPURIOUS,
108 TSI108_GREG_TIMER_FREQ,
112 TSI108_TIMER_CURRENT_CNT,
113 TSI108_TIMER_BASE_CNT,
114 TSI108_TIMER_VECTOR_PRI,
115 TSI108_TIMER_DESTINATION,
119 TSI108_CPU_IPI_DISPATCH_0,
120 TSI108_CPU_IPI_DISPATCH_STRIDE,
121 TSI108_CPU_CURRENT_TASK_PRI,
129 TSI108_IRQ_VECTOR_PRI,
130 TSI108_VECPRI_VECTOR_MASK,
131 TSI108_VECPRI_POLARITY_POSITIVE,
132 TSI108_VECPRI_POLARITY_NEGATIVE,
133 TSI108_VECPRI_SENSE_LEVEL,
134 TSI108_VECPRI_SENSE_EDGE,
135 TSI108_VECPRI_POLARITY_MASK,
136 TSI108_VECPRI_SENSE_MASK,
137 TSI108_IRQ_DESTINATION
141 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
143 #else /* CONFIG_MPIC_WEIRD */
145 #define MPIC_INFO(name) MPIC_##name
147 #endif /* CONFIG_MPIC_WEIRD */
150 * Register accessor functions
154 static inline u32 _mpic_read(enum mpic_reg_type type,
155 struct mpic_reg_bank *rb,
159 #ifdef CONFIG_PPC_DCR
160 case mpic_access_dcr:
161 return dcr_read(rb->dhost, reg);
163 case mpic_access_mmio_be:
164 return in_be32(rb->base + (reg >> 2));
165 case mpic_access_mmio_le:
167 return in_le32(rb->base + (reg >> 2));
171 static inline void _mpic_write(enum mpic_reg_type type,
172 struct mpic_reg_bank *rb,
173 unsigned int reg, u32 value)
176 #ifdef CONFIG_PPC_DCR
177 case mpic_access_dcr:
178 dcr_write(rb->dhost, reg, value);
181 case mpic_access_mmio_be:
182 out_be32(rb->base + (reg >> 2), value);
184 case mpic_access_mmio_le:
186 out_le32(rb->base + (reg >> 2), value);
191 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
193 enum mpic_reg_type type = mpic->reg_type;
194 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
195 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
197 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
198 type = mpic_access_mmio_be;
199 return _mpic_read(type, &mpic->gregs, offset);
202 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
204 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
205 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
207 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
210 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
212 unsigned int cpu = 0;
214 if (mpic->flags & MPIC_PRIMARY)
215 cpu = hard_smp_processor_id();
216 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
219 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
221 unsigned int cpu = 0;
223 if (mpic->flags & MPIC_PRIMARY)
224 cpu = hard_smp_processor_id();
226 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
229 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
231 unsigned int isu = src_no >> mpic->isu_shift;
232 unsigned int idx = src_no & mpic->isu_mask;
235 val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
236 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
237 #ifdef CONFIG_MPIC_BROKEN_REGREAD
239 val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |
240 mpic->isu_reg0_shadow[src_no];
245 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
246 unsigned int reg, u32 value)
248 unsigned int isu = src_no >> mpic->isu_shift;
249 unsigned int idx = src_no & mpic->isu_mask;
251 _mpic_write(mpic->reg_type, &mpic->isus[isu],
252 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
254 #ifdef CONFIG_MPIC_BROKEN_REGREAD
256 mpic->isu_reg0_shadow[src_no] =
257 value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);
261 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
262 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
263 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
264 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
265 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
266 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
267 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
268 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
272 * Low level utility functions
276 static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
277 struct mpic_reg_bank *rb, unsigned int offset,
280 rb->base = ioremap(phys_addr + offset, size);
281 BUG_ON(rb->base == NULL);
284 #ifdef CONFIG_PPC_DCR
285 static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node,
286 struct mpic_reg_bank *rb,
287 unsigned int offset, unsigned int size)
291 dbasep = of_get_property(node, "dcr-reg", NULL);
293 rb->dhost = dcr_map(node, *dbasep + offset, size);
294 BUG_ON(!DCR_MAP_OK(rb->dhost));
297 static inline void mpic_map(struct mpic *mpic, struct device_node *node,
298 phys_addr_t phys_addr, struct mpic_reg_bank *rb,
299 unsigned int offset, unsigned int size)
301 if (mpic->flags & MPIC_USES_DCR)
302 _mpic_map_dcr(mpic, node, rb, offset, size);
304 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
306 #else /* CONFIG_PPC_DCR */
307 #define mpic_map(m,n,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)
308 #endif /* !CONFIG_PPC_DCR */
312 /* Check if we have one of those nice broken MPICs with a flipped endian on
313 * reads from IPI registers
315 static void __init mpic_test_broken_ipi(struct mpic *mpic)
319 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
320 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
322 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
323 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
324 mpic->flags |= MPIC_BROKEN_IPI;
328 #ifdef CONFIG_MPIC_U3_HT_IRQS
330 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
331 * to force the edge setting on the MPIC and do the ack workaround.
333 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
335 if (source >= 128 || !mpic->fixups)
337 return mpic->fixups[source].base != NULL;
341 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
343 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
345 if (fixup->applebase) {
346 unsigned int soff = (fixup->index >> 3) & ~3;
347 unsigned int mask = 1U << (fixup->index & 0x1f);
348 writel(mask, fixup->applebase + soff);
350 spin_lock(&mpic->fixup_lock);
351 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
352 writel(fixup->data, fixup->base + 4);
353 spin_unlock(&mpic->fixup_lock);
357 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
358 unsigned int irqflags)
360 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
364 if (fixup->base == NULL)
367 DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n",
368 source, irqflags, fixup->index);
369 spin_lock_irqsave(&mpic->fixup_lock, flags);
370 /* Enable and configure */
371 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
372 tmp = readl(fixup->base + 4);
374 if (irqflags & IRQ_LEVEL)
376 writel(tmp, fixup->base + 4);
377 spin_unlock_irqrestore(&mpic->fixup_lock, flags);
380 /* use the lowest bit inverted to the actual HW,
381 * set if this fixup was enabled, clear otherwise */
382 mpic->save_data[source].fixup_data = tmp | 1;
386 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source,
387 unsigned int irqflags)
389 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
393 if (fixup->base == NULL)
396 DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags);
399 spin_lock_irqsave(&mpic->fixup_lock, flags);
400 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
401 tmp = readl(fixup->base + 4);
403 writel(tmp, fixup->base + 4);
404 spin_unlock_irqrestore(&mpic->fixup_lock, flags);
407 /* use the lowest bit inverted to the actual HW,
408 * set if this fixup was enabled, clear otherwise */
409 mpic->save_data[source].fixup_data = tmp & ~1;
413 #ifdef CONFIG_PCI_MSI
414 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
421 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
422 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
423 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
424 if (id == PCI_CAP_ID_HT) {
425 id = readb(devbase + pos + 3);
426 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
434 base = devbase + pos;
436 flags = readb(base + HT_MSI_FLAGS);
437 if (!(flags & HT_MSI_FLAGS_FIXED)) {
438 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
439 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
442 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
443 PCI_SLOT(devfn), PCI_FUNC(devfn),
444 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
446 if (!(flags & HT_MSI_FLAGS_ENABLE))
447 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
450 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
457 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
458 unsigned int devfn, u32 vdid)
465 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
466 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
467 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
468 if (id == PCI_CAP_ID_HT) {
469 id = readb(devbase + pos + 3);
470 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
477 base = devbase + pos;
478 writeb(0x01, base + 2);
479 n = (readl(base + 4) >> 16) & 0xff;
481 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
483 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
485 for (i = 0; i <= n; i++) {
486 writeb(0x10 + 2 * i, base + 2);
487 tmp = readl(base + 4);
488 irq = (tmp >> 16) & 0xff;
489 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
490 /* mask it , will be unmasked later */
492 writel(tmp, base + 4);
493 mpic->fixups[irq].index = i;
494 mpic->fixups[irq].base = base;
495 /* Apple HT PIC has a non-standard way of doing EOIs */
496 if ((vdid & 0xffff) == 0x106b)
497 mpic->fixups[irq].applebase = devbase + 0x60;
499 mpic->fixups[irq].applebase = NULL;
500 writeb(0x11 + 2 * i, base + 2);
501 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
506 static void __init mpic_scan_ht_pics(struct mpic *mpic)
509 u8 __iomem *cfgspace;
511 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
513 /* Allocate fixups array */
514 mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL);
515 BUG_ON(mpic->fixups == NULL);
518 spin_lock_init(&mpic->fixup_lock);
520 /* Map U3 config space. We assume all IO-APICs are on the primary bus
521 * so we only need to map 64kB.
523 cfgspace = ioremap(0xf2000000, 0x10000);
524 BUG_ON(cfgspace == NULL);
526 /* Now we scan all slots. We do a very quick scan, we read the header
527 * type, vendor ID and device ID only, that's plenty enough
529 for (devfn = 0; devfn < 0x100; devfn++) {
530 u8 __iomem *devbase = cfgspace + (devfn << 8);
531 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
532 u32 l = readl(devbase + PCI_VENDOR_ID);
535 DBG("devfn %x, l: %x\n", devfn, l);
537 /* If no device, skip */
538 if (l == 0xffffffff || l == 0x00000000 ||
539 l == 0x0000ffff || l == 0xffff0000)
541 /* Check if is supports capability lists */
542 s = readw(devbase + PCI_STATUS);
543 if (!(s & PCI_STATUS_CAP_LIST))
546 mpic_scan_ht_pic(mpic, devbase, devfn, l);
547 mpic_scan_ht_msi(mpic, devbase, devfn);
550 /* next device, if function 0 */
551 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
556 #else /* CONFIG_MPIC_U3_HT_IRQS */
558 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
563 static void __init mpic_scan_ht_pics(struct mpic *mpic)
567 #endif /* CONFIG_MPIC_U3_HT_IRQS */
570 static int irq_choose_cpu(const cpumask_t *mask)
574 if (cpumask_equal(mask, cpu_all_mask)) {
575 static int irq_rover;
576 static DEFINE_SPINLOCK(irq_rover_lock);
579 /* Round-robin distribution... */
581 spin_lock_irqsave(&irq_rover_lock, flags);
583 while (!cpu_online(irq_rover)) {
584 if (++irq_rover >= NR_CPUS)
589 if (++irq_rover >= NR_CPUS)
591 } while (!cpu_online(irq_rover));
593 spin_unlock_irqrestore(&irq_rover_lock, flags);
595 cpuid = cpumask_first_and(mask, cpu_online_mask);
596 if (cpuid >= nr_cpu_ids)
600 return get_hard_smp_processor_id(cpuid);
603 static int irq_choose_cpu(const cpumask_t *mask)
605 return hard_smp_processor_id();
609 #define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
611 /* Find an mpic associated with a given linux interrupt */
612 static struct mpic *mpic_find(unsigned int irq)
614 if (irq < NUM_ISA_INTERRUPTS)
617 return irq_to_desc(irq)->chip_data;
620 /* Determine if the linux irq is an IPI */
621 static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)
623 unsigned int src = mpic_irq_to_hw(irq);
625 return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
629 /* Convert a cpu mask from logical to physical cpu numbers. */
630 static inline u32 mpic_physmask(u32 cpumask)
635 for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)
636 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
641 /* Get the mpic structure from the IPI number */
642 static inline struct mpic * mpic_from_ipi(unsigned int ipi)
644 return irq_to_desc(ipi)->chip_data;
648 /* Get the mpic structure from the irq number */
649 static inline struct mpic * mpic_from_irq(unsigned int irq)
651 return irq_to_desc(irq)->chip_data;
655 static inline void mpic_eoi(struct mpic *mpic)
657 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
658 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
662 * Linux descriptor level callbacks
666 void mpic_unmask_irq(unsigned int irq)
668 unsigned int loops = 100000;
669 struct mpic *mpic = mpic_from_irq(irq);
670 unsigned int src = mpic_irq_to_hw(irq);
672 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);
674 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
675 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
677 /* make sure mask gets to controller before we return to user */
680 printk(KERN_ERR "mpic_enable_irq timeout\n");
683 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
686 void mpic_mask_irq(unsigned int irq)
688 unsigned int loops = 100000;
689 struct mpic *mpic = mpic_from_irq(irq);
690 unsigned int src = mpic_irq_to_hw(irq);
692 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
694 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
695 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
698 /* make sure mask gets to controller before we return to user */
701 printk(KERN_ERR "mpic_enable_irq timeout\n");
704 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
707 void mpic_end_irq(unsigned int irq)
709 struct mpic *mpic = mpic_from_irq(irq);
712 DBG("%s: end_irq: %d\n", mpic->name, irq);
714 /* We always EOI on end_irq() even for edge interrupts since that
715 * should only lower the priority, the MPIC should have properly
716 * latched another edge interrupt coming in anyway
722 #ifdef CONFIG_MPIC_U3_HT_IRQS
724 static void mpic_unmask_ht_irq(unsigned int irq)
726 struct mpic *mpic = mpic_from_irq(irq);
727 unsigned int src = mpic_irq_to_hw(irq);
729 mpic_unmask_irq(irq);
731 if (irq_to_desc(irq)->status & IRQ_LEVEL)
732 mpic_ht_end_irq(mpic, src);
735 static unsigned int mpic_startup_ht_irq(unsigned int irq)
737 struct mpic *mpic = mpic_from_irq(irq);
738 unsigned int src = mpic_irq_to_hw(irq);
740 mpic_unmask_irq(irq);
741 mpic_startup_ht_interrupt(mpic, src, irq_to_desc(irq)->status);
746 static void mpic_shutdown_ht_irq(unsigned int irq)
748 struct mpic *mpic = mpic_from_irq(irq);
749 unsigned int src = mpic_irq_to_hw(irq);
751 mpic_shutdown_ht_interrupt(mpic, src, irq_to_desc(irq)->status);
755 static void mpic_end_ht_irq(unsigned int irq)
757 struct mpic *mpic = mpic_from_irq(irq);
758 unsigned int src = mpic_irq_to_hw(irq);
761 DBG("%s: end_irq: %d\n", mpic->name, irq);
763 /* We always EOI on end_irq() even for edge interrupts since that
764 * should only lower the priority, the MPIC should have properly
765 * latched another edge interrupt coming in anyway
768 if (irq_to_desc(irq)->status & IRQ_LEVEL)
769 mpic_ht_end_irq(mpic, src);
772 #endif /* !CONFIG_MPIC_U3_HT_IRQS */
776 static void mpic_unmask_ipi(unsigned int irq)
778 struct mpic *mpic = mpic_from_ipi(irq);
779 unsigned int src = mpic_irq_to_hw(irq) - mpic->ipi_vecs[0];
781 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src);
782 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
785 static void mpic_mask_ipi(unsigned int irq)
787 /* NEVER disable an IPI... that's just plain wrong! */
790 static void mpic_end_ipi(unsigned int irq)
792 struct mpic *mpic = mpic_from_ipi(irq);
795 * IPIs are marked IRQ_PER_CPU. This has the side effect of
796 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
797 * applying to them. We EOI them late to avoid re-entering.
798 * We mark IPI's with IRQF_DISABLED as they must run with
804 #endif /* CONFIG_SMP */
806 int mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask)
808 struct mpic *mpic = mpic_from_irq(irq);
809 unsigned int src = mpic_irq_to_hw(irq);
811 if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
812 int cpuid = irq_choose_cpu(cpumask);
814 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
818 cpumask_and(&tmp, cpumask, cpu_online_mask);
820 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
821 mpic_physmask(cpus_addr(tmp)[0]));
827 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
829 /* Now convert sense value */
830 switch(type & IRQ_TYPE_SENSE_MASK) {
831 case IRQ_TYPE_EDGE_RISING:
832 return MPIC_INFO(VECPRI_SENSE_EDGE) |
833 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
834 case IRQ_TYPE_EDGE_FALLING:
835 case IRQ_TYPE_EDGE_BOTH:
836 return MPIC_INFO(VECPRI_SENSE_EDGE) |
837 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
838 case IRQ_TYPE_LEVEL_HIGH:
839 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
840 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
841 case IRQ_TYPE_LEVEL_LOW:
843 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
844 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
848 int mpic_set_irq_type(unsigned int virq, unsigned int flow_type)
850 struct mpic *mpic = mpic_from_irq(virq);
851 unsigned int src = mpic_irq_to_hw(virq);
852 struct irq_desc *desc = irq_to_desc(virq);
853 unsigned int vecpri, vold, vnew;
855 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
856 mpic, virq, src, flow_type);
858 if (src >= mpic->irq_count)
861 if (flow_type == IRQ_TYPE_NONE)
862 if (mpic->senses && src < mpic->senses_count)
863 flow_type = mpic->senses[src];
864 if (flow_type == IRQ_TYPE_NONE)
865 flow_type = IRQ_TYPE_LEVEL_LOW;
867 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
868 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
869 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
870 desc->status |= IRQ_LEVEL;
872 if (mpic_is_ht_interrupt(mpic, src))
873 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
874 MPIC_VECPRI_SENSE_EDGE;
876 vecpri = mpic_type_to_vecpri(mpic, flow_type);
878 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
879 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
880 MPIC_INFO(VECPRI_SENSE_MASK));
883 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
888 void mpic_set_vector(unsigned int virq, unsigned int vector)
890 struct mpic *mpic = mpic_from_irq(virq);
891 unsigned int src = mpic_irq_to_hw(virq);
894 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
895 mpic, virq, src, vector);
897 if (src >= mpic->irq_count)
900 vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
901 vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
903 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
906 static struct irq_chip mpic_irq_chip = {
907 .mask = mpic_mask_irq,
908 .unmask = mpic_unmask_irq,
910 .set_type = mpic_set_irq_type,
914 static struct irq_chip mpic_ipi_chip = {
915 .mask = mpic_mask_ipi,
916 .unmask = mpic_unmask_ipi,
919 #endif /* CONFIG_SMP */
921 #ifdef CONFIG_MPIC_U3_HT_IRQS
922 static struct irq_chip mpic_irq_ht_chip = {
923 .startup = mpic_startup_ht_irq,
924 .shutdown = mpic_shutdown_ht_irq,
925 .mask = mpic_mask_irq,
926 .unmask = mpic_unmask_ht_irq,
927 .eoi = mpic_end_ht_irq,
928 .set_type = mpic_set_irq_type,
930 #endif /* CONFIG_MPIC_U3_HT_IRQS */
933 static int mpic_host_match(struct irq_host *h, struct device_node *node)
935 /* Exact match, unless mpic node is NULL */
936 return h->of_node == NULL || h->of_node == node;
939 static int mpic_host_map(struct irq_host *h, unsigned int virq,
942 struct mpic *mpic = h->host_data;
943 struct irq_chip *chip;
945 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
947 if (hw == mpic->spurious_vec)
949 if (mpic->protected && test_bit(hw, mpic->protected))
953 else if (hw >= mpic->ipi_vecs[0]) {
954 WARN_ON(!(mpic->flags & MPIC_PRIMARY));
956 DBG("mpic: mapping as IPI\n");
957 set_irq_chip_data(virq, mpic);
958 set_irq_chip_and_handler(virq, &mpic->hc_ipi,
962 #endif /* CONFIG_SMP */
964 if (hw >= mpic->irq_count)
967 mpic_msi_reserve_hwirq(mpic, hw);
970 chip = &mpic->hc_irq;
972 #ifdef CONFIG_MPIC_U3_HT_IRQS
973 /* Check for HT interrupts, override vecpri */
974 if (mpic_is_ht_interrupt(mpic, hw))
975 chip = &mpic->hc_ht_irq;
976 #endif /* CONFIG_MPIC_U3_HT_IRQS */
978 DBG("mpic: mapping to irq chip @%p\n", chip);
980 set_irq_chip_data(virq, mpic);
981 set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq);
983 /* Set default irq type */
984 set_irq_type(virq, IRQ_TYPE_NONE);
989 static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
990 const u32 *intspec, unsigned int intsize,
991 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
994 static unsigned char map_mpic_senses[4] = {
995 IRQ_TYPE_EDGE_RISING,
998 IRQ_TYPE_EDGE_FALLING,
1001 *out_hwirq = intspec[0];
1005 /* Apple invented a new race of encoding on machines with
1006 * an HT APIC. They encode, among others, the index within
1007 * the HT APIC. We don't care about it here since thankfully,
1008 * it appears that they have the APIC already properly
1009 * configured, and thus our current fixup code that reads the
1010 * APIC config works fine. However, we still need to mask out
1011 * bits in the specifier to make sure we only get bit 0 which
1012 * is the level/edge bit (the only sense bit exposed by Apple),
1013 * as their bit 1 means something else.
1015 if (machine_is(powermac))
1017 *out_flags = map_mpic_senses[intspec[1] & mask];
1019 *out_flags = IRQ_TYPE_NONE;
1021 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1022 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
1027 static struct irq_host_ops mpic_host_ops = {
1028 .match = mpic_host_match,
1029 .map = mpic_host_map,
1030 .xlate = mpic_host_xlate,
1034 * Exported functions
1037 struct mpic * __init mpic_alloc(struct device_node *node,
1038 phys_addr_t phys_addr,
1040 unsigned int isu_size,
1041 unsigned int irq_count,
1049 u64 paddr = phys_addr;
1051 mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
1057 mpic->hc_irq = mpic_irq_chip;
1058 mpic->hc_irq.name = name;
1059 if (flags & MPIC_PRIMARY)
1060 mpic->hc_irq.set_affinity = mpic_set_affinity;
1061 #ifdef CONFIG_MPIC_U3_HT_IRQS
1062 mpic->hc_ht_irq = mpic_irq_ht_chip;
1063 mpic->hc_ht_irq.name = name;
1064 if (flags & MPIC_PRIMARY)
1065 mpic->hc_ht_irq.set_affinity = mpic_set_affinity;
1066 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1069 mpic->hc_ipi = mpic_ipi_chip;
1070 mpic->hc_ipi.name = name;
1071 #endif /* CONFIG_SMP */
1073 mpic->flags = flags;
1074 mpic->isu_size = isu_size;
1075 mpic->irq_count = irq_count;
1076 mpic->num_sources = 0; /* so far */
1078 if (flags & MPIC_LARGE_VECTORS)
1083 mpic->timer_vecs[0] = intvec_top - 8;
1084 mpic->timer_vecs[1] = intvec_top - 7;
1085 mpic->timer_vecs[2] = intvec_top - 6;
1086 mpic->timer_vecs[3] = intvec_top - 5;
1087 mpic->ipi_vecs[0] = intvec_top - 4;
1088 mpic->ipi_vecs[1] = intvec_top - 3;
1089 mpic->ipi_vecs[2] = intvec_top - 2;
1090 mpic->ipi_vecs[3] = intvec_top - 1;
1091 mpic->spurious_vec = intvec_top;
1093 /* Check for "big-endian" in device-tree */
1094 if (node && of_get_property(node, "big-endian", NULL) != NULL)
1095 mpic->flags |= MPIC_BIG_ENDIAN;
1097 /* Look for protected sources */
1100 unsigned int bits, mapsize;
1102 of_get_property(node, "protected-sources", &psize);
1105 bits = intvec_top + 1;
1106 mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long);
1107 mpic->protected = kzalloc(mapsize, GFP_KERNEL);
1108 BUG_ON(mpic->protected == NULL);
1109 for (i = 0; i < psize; i++) {
1110 if (psrc[i] > intvec_top)
1112 __set_bit(psrc[i], mpic->protected);
1117 #ifdef CONFIG_MPIC_WEIRD
1118 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
1121 /* default register type */
1122 mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ?
1123 mpic_access_mmio_be : mpic_access_mmio_le;
1125 /* If no physical address is passed in, a device-node is mandatory */
1126 BUG_ON(paddr == 0 && node == NULL);
1128 /* If no physical address passed in, check if it's dcr based */
1129 if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) {
1130 #ifdef CONFIG_PPC_DCR
1131 mpic->flags |= MPIC_USES_DCR;
1132 mpic->reg_type = mpic_access_dcr;
1135 #endif /* CONFIG_PPC_DCR */
1138 /* If the MPIC is not DCR based, and no physical address was passed
1139 * in, try to obtain one
1141 if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {
1142 const u32 *reg = of_get_property(node, "reg", NULL);
1143 BUG_ON(reg == NULL);
1144 paddr = of_translate_address(node, reg);
1145 BUG_ON(paddr == OF_BAD_ADDR);
1148 /* Map the global registers */
1149 mpic_map(mpic, node, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1150 mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1153 if (flags & MPIC_WANTS_RESET) {
1154 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1155 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1156 | MPIC_GREG_GCONF_RESET);
1157 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1158 & MPIC_GREG_GCONF_RESET)
1163 if (flags & MPIC_ENABLE_COREINT)
1164 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1165 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1166 | MPIC_GREG_GCONF_COREINT);
1168 if (flags & MPIC_ENABLE_MCK)
1169 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1170 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1171 | MPIC_GREG_GCONF_MCK);
1173 /* Read feature register, calculate num CPUs and, for non-ISU
1174 * MPICs, num sources as well. On ISU MPICs, sources are counted
1177 greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1178 mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK)
1179 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
1180 if (isu_size == 0) {
1181 if (flags & MPIC_BROKEN_FRR_NIRQS)
1182 mpic->num_sources = mpic->irq_count;
1185 ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1186 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
1189 /* Map the per-CPU registers */
1190 for (i = 0; i < mpic->num_cpus; i++) {
1191 mpic_map(mpic, node, paddr, &mpic->cpuregs[i],
1192 MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE),
1196 /* Initialize main ISU if none provided */
1197 if (mpic->isu_size == 0) {
1198 mpic->isu_size = mpic->num_sources;
1199 mpic_map(mpic, node, paddr, &mpic->isus[0],
1200 MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1202 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1203 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1205 mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
1206 isu_size ? isu_size : mpic->num_sources,
1208 flags & MPIC_LARGE_VECTORS ? 2048 : 256);
1209 if (mpic->irqhost == NULL)
1212 mpic->irqhost->host_data = mpic;
1214 /* Display version */
1215 switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1229 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1231 name, vers, (unsigned long long)paddr, mpic->num_cpus);
1232 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1233 mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1238 if (flags & MPIC_PRIMARY) {
1239 mpic_primary = mpic;
1240 irq_set_default_host(mpic->irqhost);
1246 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1249 unsigned int isu_first = isu_num * mpic->isu_size;
1251 BUG_ON(isu_num >= MPIC_MAX_ISU);
1253 mpic_map(mpic, mpic->irqhost->of_node,
1254 paddr, &mpic->isus[isu_num], 0,
1255 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1257 if ((isu_first + mpic->isu_size) > mpic->num_sources)
1258 mpic->num_sources = isu_first + mpic->isu_size;
1261 void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
1263 mpic->senses = senses;
1264 mpic->senses_count = count;
1267 void __init mpic_init(struct mpic *mpic)
1272 BUG_ON(mpic->num_sources == 0);
1274 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1276 /* Set current processor priority to max */
1277 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1279 /* Initialize timers: just disable them all */
1280 for (i = 0; i < 4; i++) {
1281 mpic_write(mpic->tmregs,
1282 i * MPIC_INFO(TIMER_STRIDE) +
1283 MPIC_INFO(TIMER_DESTINATION), 0);
1284 mpic_write(mpic->tmregs,
1285 i * MPIC_INFO(TIMER_STRIDE) +
1286 MPIC_INFO(TIMER_VECTOR_PRI),
1288 (mpic->timer_vecs[0] + i));
1291 /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1292 mpic_test_broken_ipi(mpic);
1293 for (i = 0; i < 4; i++) {
1296 (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1297 (mpic->ipi_vecs[0] + i));
1300 /* Initialize interrupt sources */
1301 if (mpic->irq_count == 0)
1302 mpic->irq_count = mpic->num_sources;
1304 /* Do the HT PIC fixups on U3 broken mpic */
1305 DBG("MPIC flags: %x\n", mpic->flags);
1306 if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) {
1307 mpic_scan_ht_pics(mpic);
1308 mpic_u3msi_init(mpic);
1311 mpic_pasemi_msi_init(mpic);
1313 if (mpic->flags & MPIC_PRIMARY)
1314 cpu = hard_smp_processor_id();
1318 for (i = 0; i < mpic->num_sources; i++) {
1319 /* start with vector = source number, and masked */
1320 u32 vecpri = MPIC_VECPRI_MASK | i |
1321 (8 << MPIC_VECPRI_PRIORITY_SHIFT);
1323 /* check if protected */
1324 if (mpic->protected && test_bit(i, mpic->protected))
1327 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1328 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1331 /* Init spurious vector */
1332 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1334 /* Disable 8259 passthrough, if supported */
1335 if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1336 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1337 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1338 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1340 if (mpic->flags & MPIC_NO_BIAS)
1341 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1342 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1343 | MPIC_GREG_GCONF_NO_BIAS);
1345 /* Set current processor priority to 0 */
1346 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1349 /* allocate memory to save mpic state */
1350 mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data),
1352 BUG_ON(mpic->save_data == NULL);
1356 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
1360 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1361 v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
1362 v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
1363 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1366 void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1368 unsigned long flags;
1371 spin_lock_irqsave(&mpic_lock, flags);
1372 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1374 v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
1376 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
1377 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1378 spin_unlock_irqrestore(&mpic_lock, flags);
1381 void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1383 struct mpic *mpic = mpic_find(irq);
1384 unsigned int src = mpic_irq_to_hw(irq);
1385 unsigned long flags;
1391 spin_lock_irqsave(&mpic_lock, flags);
1392 if (mpic_is_ipi(mpic, irq)) {
1393 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1394 ~MPIC_VECPRI_PRIORITY_MASK;
1395 mpic_ipi_write(src - mpic->ipi_vecs[0],
1396 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1398 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1399 & ~MPIC_VECPRI_PRIORITY_MASK;
1400 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1401 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1403 spin_unlock_irqrestore(&mpic_lock, flags);
1406 void mpic_setup_this_cpu(void)
1409 struct mpic *mpic = mpic_primary;
1410 unsigned long flags;
1411 u32 msk = 1 << hard_smp_processor_id();
1414 BUG_ON(mpic == NULL);
1416 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1418 spin_lock_irqsave(&mpic_lock, flags);
1420 /* let the mpic know we want intrs. default affinity is 0xffffffff
1421 * until changed via /proc. That's how it's done on x86. If we want
1422 * it differently, then we should make sure we also change the default
1423 * values of irq_desc[].affinity in irq.c.
1425 if (distribute_irqs) {
1426 for (i = 0; i < mpic->num_sources ; i++)
1427 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1428 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1431 /* Set current processor priority to 0 */
1432 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1434 spin_unlock_irqrestore(&mpic_lock, flags);
1435 #endif /* CONFIG_SMP */
1438 int mpic_cpu_get_priority(void)
1440 struct mpic *mpic = mpic_primary;
1442 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1445 void mpic_cpu_set_priority(int prio)
1447 struct mpic *mpic = mpic_primary;
1449 prio &= MPIC_CPU_TASKPRI_MASK;
1450 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1453 void mpic_teardown_this_cpu(int secondary)
1455 struct mpic *mpic = mpic_primary;
1456 unsigned long flags;
1457 u32 msk = 1 << hard_smp_processor_id();
1460 BUG_ON(mpic == NULL);
1462 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1463 spin_lock_irqsave(&mpic_lock, flags);
1465 /* let the mpic know we don't want intrs. */
1466 for (i = 0; i < mpic->num_sources ; i++)
1467 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1468 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1470 /* Set current processor priority to max */
1471 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1472 /* We need to EOI the IPI since not all platforms reset the MPIC
1473 * on boot and new interrupts wouldn't get delivered otherwise.
1477 spin_unlock_irqrestore(&mpic_lock, flags);
1481 void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask)
1483 struct mpic *mpic = mpic_primary;
1485 BUG_ON(mpic == NULL);
1488 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
1491 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1492 ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),
1493 mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0]));
1496 static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1500 src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
1502 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1504 if (unlikely(src == mpic->spurious_vec)) {
1505 if (mpic->flags & MPIC_SPV_EOI)
1509 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1510 if (printk_ratelimit())
1511 printk(KERN_WARNING "%s: Got protected source %d !\n",
1512 mpic->name, (int)src);
1517 return irq_linear_revmap(mpic->irqhost, src);
1520 unsigned int mpic_get_one_irq(struct mpic *mpic)
1522 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
1525 unsigned int mpic_get_irq(void)
1527 struct mpic *mpic = mpic_primary;
1529 BUG_ON(mpic == NULL);
1531 return mpic_get_one_irq(mpic);
1534 unsigned int mpic_get_coreint_irq(void)
1537 struct mpic *mpic = mpic_primary;
1540 BUG_ON(mpic == NULL);
1542 src = mfspr(SPRN_EPR);
1544 if (unlikely(src == mpic->spurious_vec)) {
1545 if (mpic->flags & MPIC_SPV_EOI)
1549 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1550 if (printk_ratelimit())
1551 printk(KERN_WARNING "%s: Got protected source %d !\n",
1552 mpic->name, (int)src);
1556 return irq_linear_revmap(mpic->irqhost, src);
1562 unsigned int mpic_get_mcirq(void)
1564 struct mpic *mpic = mpic_primary;
1566 BUG_ON(mpic == NULL);
1568 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
1572 void mpic_request_ipis(void)
1574 struct mpic *mpic = mpic_primary;
1576 BUG_ON(mpic == NULL);
1578 printk(KERN_INFO "mpic: requesting IPIs ... \n");
1580 for (i = 0; i < 4; i++) {
1581 unsigned int vipi = irq_create_mapping(mpic->irqhost,
1582 mpic->ipi_vecs[0] + i);
1583 if (vipi == NO_IRQ) {
1584 printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
1587 smp_request_message_ipi(vipi, i);
1591 void smp_mpic_message_pass(int target, int msg)
1593 /* make sure we're sending something that translates to an IPI */
1594 if ((unsigned int)msg > 3) {
1595 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1596 smp_processor_id(), msg);
1601 mpic_send_ipi(msg, 0xffffffff);
1603 case MSG_ALL_BUT_SELF:
1604 mpic_send_ipi(msg, 0xffffffff & ~(1 << smp_processor_id()));
1607 mpic_send_ipi(msg, 1 << target);
1612 int __init smp_mpic_probe(void)
1616 DBG("smp_mpic_probe()...\n");
1618 nr_cpus = cpus_weight(cpu_possible_map);
1620 DBG("nr_cpus: %d\n", nr_cpus);
1623 mpic_request_ipis();
1628 void __devinit smp_mpic_setup_cpu(int cpu)
1630 mpic_setup_this_cpu();
1632 #endif /* CONFIG_SMP */
1635 static int mpic_suspend(struct sys_device *dev, pm_message_t state)
1637 struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1640 for (i = 0; i < mpic->num_sources; i++) {
1641 mpic->save_data[i].vecprio =
1642 mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1643 mpic->save_data[i].dest =
1644 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1650 static int mpic_resume(struct sys_device *dev)
1652 struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1655 for (i = 0; i < mpic->num_sources; i++) {
1656 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
1657 mpic->save_data[i].vecprio);
1658 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1659 mpic->save_data[i].dest);
1661 #ifdef CONFIG_MPIC_U3_HT_IRQS
1663 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1666 /* we use the lowest bit in an inverted meaning */
1667 if ((mpic->save_data[i].fixup_data & 1) == 0)
1670 /* Enable and configure */
1671 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
1673 writel(mpic->save_data[i].fixup_data & ~1,
1678 } /* end for loop */
1684 static struct sysdev_class mpic_sysclass = {
1686 .resume = mpic_resume,
1687 .suspend = mpic_suspend,
1692 static int mpic_init_sys(void)
1694 struct mpic *mpic = mpics;
1697 error = sysdev_class_register(&mpic_sysclass);
1699 while (mpic && !error) {
1700 mpic->sysdev.cls = &mpic_sysclass;
1701 mpic->sysdev.id = id++;
1702 error = sysdev_register(&mpic->sysdev);
1708 device_initcall(mpic_init_sys);