2 * GPIOs on MPC8349/8572/8610 and compatible
4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/spinlock.h>
16 #include <linux/of_gpio.h>
17 #include <linux/gpio.h>
19 #define MPC8XXX_GPIO_PINS 32
28 struct mpc8xxx_gpio_chip {
29 struct of_mm_gpio_chip mm_gc;
33 * shadowed data register to be able to clear/set output pins in
34 * open drain mode safely
39 static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
41 return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
44 static inline struct mpc8xxx_gpio_chip *
45 to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm)
47 return container_of(mm, struct mpc8xxx_gpio_chip, mm_gc);
50 static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
52 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
54 mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
57 /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
58 * defined as output cannot be determined by reading GPDAT register,
59 * so we use shadow data register instead. The status of input pins
60 * is determined by reading GPDAT register.
62 static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
65 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
66 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
68 val = in_be32(mm->regs + GPIO_DAT) & ~in_be32(mm->regs + GPIO_DIR);
70 return (val | mpc8xxx_gc->data) & mpc8xxx_gpio2mask(gpio);
73 static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
75 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
77 return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
80 static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
82 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
83 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
86 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
89 mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio);
91 mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);
93 out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
95 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
98 static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
100 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
101 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
104 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
106 clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
108 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
113 static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
115 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
116 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
119 mpc8xxx_gpio_set(gc, gpio, val);
121 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
123 setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
125 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
130 static void __init mpc8xxx_add_controller(struct device_node *np)
132 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
133 struct of_mm_gpio_chip *mm_gc;
134 struct of_gpio_chip *of_gc;
135 struct gpio_chip *gc;
138 mpc8xxx_gc = kzalloc(sizeof(*mpc8xxx_gc), GFP_KERNEL);
144 spin_lock_init(&mpc8xxx_gc->lock);
146 mm_gc = &mpc8xxx_gc->mm_gc;
147 of_gc = &mm_gc->of_gc;
150 mm_gc->save_regs = mpc8xxx_gpio_save_regs;
151 of_gc->gpio_cells = 2;
152 gc->ngpio = MPC8XXX_GPIO_PINS;
153 gc->direction_input = mpc8xxx_gpio_dir_in;
154 gc->direction_output = mpc8xxx_gpio_dir_out;
155 if (of_device_is_compatible(np, "fsl,mpc8572-gpio"))
156 gc->get = mpc8572_gpio_get;
158 gc->get = mpc8xxx_gpio_get;
159 gc->set = mpc8xxx_gpio_set;
161 ret = of_mm_gpiochip_add(np, mm_gc);
168 pr_err("%s: registration failed with status %d\n",
175 static int __init mpc8xxx_add_gpiochips(void)
177 struct device_node *np;
179 for_each_compatible_node(np, NULL, "fsl,mpc8349-gpio")
180 mpc8xxx_add_controller(np);
182 for_each_compatible_node(np, NULL, "fsl,mpc8572-gpio")
183 mpc8xxx_add_controller(np);
185 for_each_compatible_node(np, NULL, "fsl,mpc8610-gpio")
186 mpc8xxx_add_controller(np);
190 arch_initcall(mpc8xxx_add_gpiochips);