1 #include <linux/kernel.h>
2 #include <linux/stddef.h>
3 #include <linux/init.h>
4 #include <linux/sched.h>
5 #include <linux/signal.h>
7 #include <linux/dma-mapping.h>
11 #include <asm/8xx_immap.h>
13 #include "mpc8xx_pic.h"
16 #define PIC_VEC_SPURRIOUS 15
18 extern int cpm_get_irq(struct pt_regs *regs);
20 static struct irq_domain *mpc8xx_pic_host;
21 #define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
22 static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
23 static sysconf8xx_t __iomem *siu_reg;
25 int cpm_get_irq(struct pt_regs *regs);
27 static void mpc8xx_unmask_irq(struct irq_data *d)
30 unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
35 ppc_cached_irq_mask[word] |= (1 << (31-bit));
36 out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
39 static void mpc8xx_mask_irq(struct irq_data *d)
42 unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
47 ppc_cached_irq_mask[word] &= ~(1 << (31-bit));
48 out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
51 static void mpc8xx_ack(struct irq_data *d)
54 unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
57 out_be32(&siu_reg->sc_sipend, 1 << (31-bit));
60 static void mpc8xx_end_irq(struct irq_data *d)
63 unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
68 ppc_cached_irq_mask[word] |= (1 << (31-bit));
69 out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
72 static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type)
74 if (flow_type & IRQ_TYPE_EDGE_FALLING) {
75 irq_hw_number_t hw = (unsigned int)irqd_to_hwirq(d);
76 unsigned int siel = in_be32(&siu_reg->sc_siel);
78 /* only external IRQ senses are programmable */
80 siel |= (0x80000000 >> hw);
81 out_be32(&siu_reg->sc_siel, siel);
82 __irq_set_handler_locked(d->irq, handle_edge_irq);
88 static struct irq_chip mpc8xx_pic = {
90 .irq_unmask = mpc8xx_unmask_irq,
91 .irq_mask = mpc8xx_mask_irq,
92 .irq_ack = mpc8xx_ack,
93 .irq_eoi = mpc8xx_end_irq,
94 .irq_set_type = mpc8xx_set_irq_type,
97 unsigned int mpc8xx_get_irq(void)
101 /* For MPC8xx, read the SIVEC register and shift the bits down
102 * to get the irq number.
104 irq = in_be32(&siu_reg->sc_sivec) >> 26;
106 if (irq == PIC_VEC_SPURRIOUS)
109 return irq_linear_revmap(mpc8xx_pic_host, irq);
113 static int mpc8xx_pic_host_map(struct irq_domain *h, unsigned int virq,
116 pr_debug("mpc8xx_pic_host_map(%d, 0x%lx)\n", virq, hw);
118 /* Set default irq handle */
119 irq_set_chip_and_handler(virq, &mpc8xx_pic, handle_level_irq);
124 static int mpc8xx_pic_host_xlate(struct irq_domain *h, struct device_node *ct,
125 const u32 *intspec, unsigned int intsize,
126 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
128 static unsigned char map_pic_senses[4] = {
129 IRQ_TYPE_EDGE_RISING,
132 IRQ_TYPE_EDGE_FALLING,
135 *out_hwirq = intspec[0];
136 if (intsize > 1 && intspec[1] < 4)
137 *out_flags = map_pic_senses[intspec[1]];
139 *out_flags = IRQ_TYPE_NONE;
145 static struct irq_domain_ops mpc8xx_pic_host_ops = {
146 .map = mpc8xx_pic_host_map,
147 .xlate = mpc8xx_pic_host_xlate,
150 int mpc8xx_pic_init(void)
153 struct device_node *np;
156 np = of_find_compatible_node(NULL, NULL, "fsl,pq1-pic");
158 np = of_find_node_by_type(NULL, "mpc8xx-pic");
160 printk(KERN_ERR "Could not find fsl,pq1-pic node\n");
164 ret = of_address_to_resource(np, 0, &res);
168 siu_reg = ioremap(res.start, resource_size(&res));
169 if (siu_reg == NULL) {
174 mpc8xx_pic_host = irq_domain_add_linear(np, 64, &mpc8xx_pic_host_ops, NULL);
175 if (mpc8xx_pic_host == NULL) {
176 printk(KERN_ERR "MPC8xx PIC: failed to allocate irq host!\n");