2 * MPC83xx/85xx/86xx PCI/PCIE support routing.
4 * Copyright 2007-2012 Freescale Semiconductor, Inc.
5 * Copyright 2008-2009 MontaVista Software, Inc.
7 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
8 * Recode: ZHANG WEI <wei.zhang@freescale.com>
9 * Rewrite the routing for Frescale PCI and PCI Express
10 * Roy Zang <tie-fei.zang@freescale.com>
11 * MPC83xx PCI-Express support:
12 * Tony Li <tony.li@freescale.com>
13 * Anton Vorontsov <avorontsov@ru.mvista.com>
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 #include <linux/kernel.h>
21 #include <linux/pci.h>
22 #include <linux/delay.h>
23 #include <linux/string.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/memblock.h>
27 #include <linux/log2.h>
28 #include <linux/slab.h>
29 #include <linux/suspend.h>
30 #include <linux/syscore_ops.h>
31 #include <linux/uaccess.h>
35 #include <asm/pci-bridge.h>
36 #include <asm/ppc-pci.h>
37 #include <asm/machdep.h>
38 #include <asm/disassemble.h>
39 #include <asm/ppc-opcode.h>
40 #include <sysdev/fsl_soc.h>
41 #include <sysdev/fsl_pci.h>
43 static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
45 static void quirk_fsl_pcie_early(struct pci_dev *dev)
49 /* if we aren't a PCIe don't bother */
50 if (!pci_is_pcie(dev))
53 /* if we aren't in host mode don't bother */
54 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
55 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
58 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
59 fsl_pcie_bus_fixup = 1;
63 static int fsl_indirect_read_config(struct pci_bus *, unsigned int,
66 static int fsl_pcie_check_link(struct pci_controller *hose)
70 if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
71 if (hose->ops->read == fsl_indirect_read_config) {
73 bus.number = hose->first_busno;
76 indirect_read_config(&bus, 0, PCIE_LTSSM, 4, &val);
78 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
79 if (val < PCIE_LTSSM_L0)
82 struct ccsr_pci __iomem *pci = hose->private_data;
83 /* for PCIe IP rev 3.0 or greater use CSR0 for link state */
84 val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK)
85 >> PEX_CSR0_LTSSM_SHIFT;
86 if (val != PEX_CSR0_LTSSM_L0)
93 static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn,
94 int offset, int len, u32 *val)
96 struct pci_controller *hose = pci_bus_to_host(bus);
98 if (fsl_pcie_check_link(hose))
99 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
101 hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
103 return indirect_read_config(bus, devfn, offset, len, val);
106 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
108 static struct pci_ops fsl_indirect_pcie_ops =
110 .read = fsl_indirect_read_config,
111 .write = indirect_write_config,
114 #define MAX_PHYS_ADDR_BITS 40
115 static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS;
117 static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
119 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
123 * Fixup PCI devices that are able to DMA to above the physical
124 * address width of the SoC such that we can address any internal
125 * SoC address from across PCI if needed
127 if ((dev_is_pci(dev)) &&
128 dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) {
129 set_dma_ops(dev, &dma_direct_ops);
130 set_dma_offset(dev, pci64_dma_offset);
133 *dev->dma_mask = dma_mask;
137 static int setup_one_atmu(struct ccsr_pci __iomem *pci,
138 unsigned int index, const struct resource *res,
139 resource_size_t offset)
141 resource_size_t pci_addr = res->start - offset;
142 resource_size_t phys_addr = res->start;
143 resource_size_t size = resource_size(res);
144 u32 flags = 0x80044000; /* enable & mem R/W */
147 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
148 (u64)res->start, (u64)size);
150 if (res->flags & IORESOURCE_PREFETCH)
151 flags |= 0x10000000; /* enable relaxed ordering */
153 for (i = 0; size > 0; i++) {
154 unsigned int bits = min_t(u32, ilog2(size),
155 __ffs(pci_addr | phys_addr));
160 out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
161 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
162 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
163 out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
165 pci_addr += (resource_size_t)1U << bits;
166 phys_addr += (resource_size_t)1U << bits;
167 size -= (resource_size_t)1U << bits;
173 /* atmu setup for fsl pci/pcie controller */
174 static void setup_pci_atmu(struct pci_controller *hose)
176 struct ccsr_pci __iomem *pci = hose->private_data;
177 int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
178 u64 mem, sz, paddr_hi = 0;
179 u64 offset = 0, paddr_lo = ULLONG_MAX;
180 u32 pcicsrbar = 0, pcicsrbar_sz;
181 u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
182 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
183 const char *name = hose->dn->full_name;
187 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
188 if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) {
195 /* Disable all windows (except powar0 since it's ignored) */
196 for(i = 1; i < 5; i++)
197 out_be32(&pci->pow[i].powar, 0);
198 for (i = start_idx; i < end_idx; i++)
199 out_be32(&pci->piw[i].piwar, 0);
201 /* Setup outbound MEM window */
202 for(i = 0, j = 1; i < 3; i++) {
203 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
206 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
207 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
209 /* We assume all memory resources have the same offset */
210 offset = hose->mem_offset[i];
211 n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset);
213 if (n < 0 || j >= 5) {
214 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
215 hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
220 /* Setup outbound IO window */
221 if (hose->io_resource.flags & IORESOURCE_IO) {
223 pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
225 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
226 "phy base 0x%016llx.\n",
227 (u64)hose->io_resource.start,
228 (u64)resource_size(&hose->io_resource),
229 (u64)hose->io_base_phys);
230 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
231 out_be32(&pci->pow[j].potear, 0);
232 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
234 out_be32(&pci->pow[j].powar, 0x80088000
235 | (ilog2(hose->io_resource.end
236 - hose->io_resource.start + 1) - 1));
240 /* convert to pci address space */
244 if (paddr_hi == paddr_lo) {
245 pr_err("%s: No outbound window space\n", name);
250 pr_err("%s: No space for inbound window\n", name);
254 /* setup PCSRBAR/PEXCSRBAR */
255 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
256 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
257 pcicsrbar_sz = ~pcicsrbar_sz + 1;
259 if (paddr_hi < (0x100000000ull - pcicsrbar_sz) ||
260 (paddr_lo > 0x100000000ull))
261 pcicsrbar = 0x100000000ull - pcicsrbar_sz;
263 pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz;
264 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
266 paddr_lo = min(paddr_lo, (u64)pcicsrbar);
268 pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar);
270 /* Setup inbound mem window */
271 mem = memblock_end_of_DRAM();
274 * The msi-address-64 property, if it exists, indicates the physical
275 * address of the MSIIR register. Normally, this register is located
276 * inside CCSR, so the ATMU that covers all of CCSR is used. But if
277 * this property exists, then we normally need to create a new ATMU
278 * for it. For now, however, we cheat. The only entity that creates
279 * this property is the Freescale hypervisor, and the address is
280 * specified in the partition configuration. Typically, the address
281 * is located in the page immediately after the end of DDR. If so, we
282 * can avoid allocating a new ATMU by extending the DDR ATMU by one
285 reg = of_get_property(hose->dn, "msi-address-64", &len);
286 if (reg && (len == sizeof(u64))) {
287 u64 address = be64_to_cpup(reg);
289 if ((address >= mem) && (address < (mem + PAGE_SIZE))) {
290 pr_info("%s: extending DDR ATMU to cover MSIIR", name);
293 /* TODO: Create a new ATMU for MSIIR */
294 pr_warn("%s: msi-address-64 address of %llx is "
295 "unsupported\n", name, address);
299 sz = min(mem, paddr_lo);
302 /* PCIe can overmap inbound & outbound since RX & TX are separated */
303 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
304 /* Size window to exact size if power-of-two or one size up */
305 if ((1ull << mem_log) != mem) {
307 if ((1ull << mem_log) > mem)
308 pr_info("%s: Setting PCI inbound window "
309 "greater than memory size\n", name);
312 piwar |= ((mem_log - 1) & PIWAR_SZ_MASK);
314 /* Setup inbound memory window */
315 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
316 out_be32(&pci->piw[win_idx].piwbar, 0x00000000);
317 out_be32(&pci->piw[win_idx].piwar, piwar);
320 hose->dma_window_base_cur = 0x00000000;
321 hose->dma_window_size = (resource_size_t)sz;
324 * if we have >4G of memory setup second PCI inbound window to
325 * let devices that are 64-bit address capable to work w/o
326 * SWIOTLB and access the full range of memory
329 mem_log = ilog2(mem);
331 /* Size window up if we dont fit in exact power-of-2 */
332 if ((1ull << mem_log) != mem)
335 piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1);
337 /* Setup inbound memory window */
338 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
339 out_be32(&pci->piw[win_idx].piwbear,
340 pci64_dma_offset >> 44);
341 out_be32(&pci->piw[win_idx].piwbar,
342 pci64_dma_offset >> 12);
343 out_be32(&pci->piw[win_idx].piwar, piwar);
346 * install our own dma_set_mask handler to fixup dma_ops
349 ppc_md.dma_set_mask = fsl_pci_dma_set_mask;
351 pr_info("%s: Setup 64-bit PCI DMA window\n", name);
356 /* Setup inbound memory window */
357 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
358 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
359 out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1)));
362 paddr += 1ull << mem_log;
363 sz -= 1ull << mem_log;
367 piwar |= (mem_log - 1);
369 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
370 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
371 out_be32(&pci->piw[win_idx].piwar, piwar);
374 paddr += 1ull << mem_log;
377 hose->dma_window_base_cur = 0x00000000;
378 hose->dma_window_size = (resource_size_t)paddr;
381 if (hose->dma_window_size < mem) {
382 #ifdef CONFIG_SWIOTLB
383 ppc_swiotlb_enable = 1;
385 pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to "
386 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
389 /* adjusting outbound windows could reclaim space in mem map */
390 if (paddr_hi < 0xffffffffull)
391 pr_warning("%s: WARNING: Outbound window cfg leaves "
392 "gaps in memory map. Adjusting the memory map "
393 "could reduce unnecessary bounce buffering.\n",
396 pr_info("%s: DMA window size is 0x%llx\n", name,
397 (u64)hose->dma_window_size);
401 static void __init setup_pci_cmd(struct pci_controller *hose)
406 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
407 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
409 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
411 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
413 int pci_x_cmd = cap_x + PCI_X_CMD;
414 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
415 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
416 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
418 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
422 void fsl_pcibios_fixup_bus(struct pci_bus *bus)
424 struct pci_controller *hose = pci_bus_to_host(bus);
425 int i, is_pcie = 0, no_link;
427 /* The root complex bridge comes up with bogus resources,
428 * we copy the PHB ones in.
430 * With the current generic PCI code, the PHB bus no longer
431 * has bus->resource[0..4] set, so things are a bit more
435 if (fsl_pcie_bus_fixup)
436 is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
437 no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK);
439 if (bus->parent == hose->bus && (is_pcie || no_link)) {
440 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) {
441 struct resource *res = bus->resource[i];
442 struct resource *par;
447 par = &hose->io_resource;
449 par = &hose->mem_resources[i-1];
452 res->start = par ? par->start : 0;
453 res->end = par ? par->end : 0;
454 res->flags = par ? par->flags : 0;
459 int fsl_add_bridge(struct platform_device *pdev, int is_primary)
462 struct pci_controller *hose;
463 struct resource rsrc;
464 const int *bus_range;
466 struct device_node *dev;
467 struct ccsr_pci __iomem *pci;
469 dev = pdev->dev.of_node;
471 if (!of_device_is_available(dev)) {
472 pr_warning("%s: disabled\n", dev->full_name);
476 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
478 /* Fetch host bridge registers address */
479 if (of_address_to_resource(dev, 0, &rsrc)) {
480 printk(KERN_WARNING "Can't get pci register base!");
484 /* Get bus range if any */
485 bus_range = of_get_property(dev, "bus-range", &len);
486 if (bus_range == NULL || len < 2 * sizeof(int))
487 printk(KERN_WARNING "Can't get bus-range for %s, assume"
488 " bus 0\n", dev->full_name);
490 pci_add_flags(PCI_REASSIGN_ALL_BUS);
491 hose = pcibios_alloc_controller(dev);
495 /* set platform device as the parent */
496 hose->parent = &pdev->dev;
497 hose->first_busno = bus_range ? bus_range[0] : 0x0;
498 hose->last_busno = bus_range ? bus_range[1] : 0xff;
500 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
501 (u64)rsrc.start, (u64)resource_size(&rsrc));
503 pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc));
504 if (!hose->private_data)
507 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
508 PPC_INDIRECT_TYPE_BIG_ENDIAN);
510 if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0)
511 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
513 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
514 /* use fsl_indirect_read_config for PCIe */
515 hose->ops = &fsl_indirect_pcie_ops;
516 /* For PCIE read HEADER_TYPE to identify controler mode */
517 early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type);
518 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
522 /* For PCI read PROG to identify controller mode */
523 early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
525 !of_property_read_bool(dev, "fsl,pci-agent-force-enum"))
531 /* check PCI express link status */
532 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
533 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
534 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
535 if (fsl_pcie_check_link(hose))
536 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
539 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
540 "Firmware bus number: %d->%d\n",
541 (unsigned long long)rsrc.start, hose->first_busno,
544 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
545 hose, hose->cfg_addr, hose->cfg_data);
547 /* Interpret the "ranges" property */
548 /* This also maps the I/O region and sets isa_io/mem_base */
549 pci_process_bridge_OF_ranges(hose, dev, is_primary);
551 /* Setup PEX window registers */
552 setup_pci_atmu(hose);
557 iounmap(hose->private_data);
558 /* unmap cfg_data & cfg_addr separately if not on same page */
559 if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
560 ((unsigned long)hose->cfg_addr & PAGE_MASK))
561 iounmap(hose->cfg_data);
562 iounmap(hose->cfg_addr);
563 pcibios_free_controller(hose);
566 #endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
568 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
569 quirk_fsl_pcie_early);
571 #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
572 struct mpc83xx_pcie_priv {
573 void __iomem *cfg_type0;
574 void __iomem *cfg_type1;
578 struct pex_inbound_window {
586 * With the convention of u-boot, the PCIE outbound window 0 serves
587 * as configuration transactions outbound.
589 #define PEX_OUTWIN0_BAR 0xCA4
590 #define PEX_OUTWIN0_TAL 0xCA8
591 #define PEX_OUTWIN0_TAH 0xCAC
592 #define PEX_RC_INWIN_BASE 0xE60
593 #define PEX_RCIWARn_EN 0x1
595 static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
597 struct pci_controller *hose = pci_bus_to_host(bus);
599 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
600 return PCIBIOS_DEVICE_NOT_FOUND;
602 * Workaround for the HW bug: for Type 0 configure transactions the
603 * PCI-E controller does not check the device number bits and just
604 * assumes that the device number bits are 0.
606 if (bus->number == hose->first_busno ||
607 bus->primary == hose->first_busno) {
609 return PCIBIOS_DEVICE_NOT_FOUND;
612 if (ppc_md.pci_exclude_device) {
613 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
614 return PCIBIOS_DEVICE_NOT_FOUND;
617 return PCIBIOS_SUCCESSFUL;
620 static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
621 unsigned int devfn, int offset)
623 struct pci_controller *hose = pci_bus_to_host(bus);
624 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
625 u32 dev_base = bus->number << 24 | devfn << 16;
628 ret = mpc83xx_pcie_exclude_device(bus, devfn);
635 if (bus->number == hose->first_busno)
636 return pcie->cfg_type0 + offset;
638 if (pcie->dev_base == dev_base)
641 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base);
643 pcie->dev_base = dev_base;
645 return pcie->cfg_type1 + offset;
648 static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
649 int offset, int len, u32 val)
651 struct pci_controller *hose = pci_bus_to_host(bus);
653 /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */
654 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
657 return pci_generic_config_write(bus, devfn, offset, len, val);
660 static struct pci_ops mpc83xx_pcie_ops = {
661 .map_bus = mpc83xx_pcie_remap_cfg,
662 .read = pci_generic_config_read,
663 .write = mpc83xx_pcie_write_config,
666 static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
667 struct resource *reg)
669 struct mpc83xx_pcie_priv *pcie;
673 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL);
677 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg));
678 if (!pcie->cfg_type0)
681 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR);
683 /* PCI-E isn't configured. */
688 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000);
689 if (!pcie->cfg_type1)
692 WARN_ON(hose->dn->data);
693 hose->dn->data = pcie;
694 hose->ops = &mpc83xx_pcie_ops;
695 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
697 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
698 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
700 if (fsl_pcie_check_link(hose))
701 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
705 iounmap(pcie->cfg_type0);
712 int __init mpc83xx_add_bridge(struct device_node *dev)
716 struct pci_controller *hose;
717 struct resource rsrc_reg;
718 struct resource rsrc_cfg;
719 const int *bus_range;
724 if (!of_device_is_available(dev)) {
725 pr_warning("%s: disabled by the firmware.\n",
729 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
731 /* Fetch host bridge registers address */
732 if (of_address_to_resource(dev, 0, &rsrc_reg)) {
733 printk(KERN_WARNING "Can't get pci register base!\n");
737 memset(&rsrc_cfg, 0, sizeof(rsrc_cfg));
739 if (of_address_to_resource(dev, 1, &rsrc_cfg)) {
741 "No pci config register base in dev tree, "
744 * MPC83xx supports up to two host controllers
745 * one at 0x8500 has config space registers at 0x8300
746 * one at 0x8600 has config space registers at 0x8380
748 if ((rsrc_reg.start & 0xfffff) == 0x8500)
749 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;
750 else if ((rsrc_reg.start & 0xfffff) == 0x8600)
751 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;
754 * Controller at offset 0x8500 is primary
756 if ((rsrc_reg.start & 0xfffff) == 0x8500)
761 /* Get bus range if any */
762 bus_range = of_get_property(dev, "bus-range", &len);
763 if (bus_range == NULL || len < 2 * sizeof(int)) {
764 printk(KERN_WARNING "Can't get bus-range for %s, assume"
765 " bus 0\n", dev->full_name);
768 pci_add_flags(PCI_REASSIGN_ALL_BUS);
769 hose = pcibios_alloc_controller(dev);
773 hose->first_busno = bus_range ? bus_range[0] : 0;
774 hose->last_busno = bus_range ? bus_range[1] : 0xff;
776 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) {
777 ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
781 setup_indirect_pci(hose, rsrc_cfg.start,
782 rsrc_cfg.start + 4, 0);
785 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
786 "Firmware bus number: %d->%d\n",
787 (unsigned long long)rsrc_reg.start, hose->first_busno,
790 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
791 hose, hose->cfg_addr, hose->cfg_data);
793 /* Interpret the "ranges" property */
794 /* This also maps the I/O region and sets isa_io/mem_base */
795 pci_process_bridge_OF_ranges(hose, dev, primary);
799 pcibios_free_controller(hose);
802 #endif /* CONFIG_PPC_83xx */
804 u64 fsl_pci_immrbar_base(struct pci_controller *hose)
806 #ifdef CONFIG_PPC_83xx
807 if (is_mpc83xx_pci) {
808 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
809 struct pex_inbound_window *in;
812 /* Walk the Root Complex Inbound windows to match IMMR base */
813 in = pcie->cfg_type0 + PEX_RC_INWIN_BASE;
814 for (i = 0; i < 4; i++) {
815 /* not enabled, skip */
816 if (!(in_le32(&in[i].ar) & PEX_RCIWARn_EN))
819 if (get_immrbase() == in_le32(&in[i].tar))
820 return (u64)in_le32(&in[i].barh) << 32 |
821 in_le32(&in[i].barl);
824 printk(KERN_WARNING "could not find PCI BAR matching IMMR\n");
828 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
829 if (!is_mpc83xx_pci) {
832 pci_bus_read_config_dword(hose->bus,
833 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
836 * For PEXCSRBAR, bit 3-0 indicate prefetchable and
837 * address type. So when getting base address, these
838 * bits should be masked
840 base &= PCI_BASE_ADDRESS_MEM_MASK;
850 static int mcheck_handle_load(struct pt_regs *regs, u32 inst)
852 unsigned int rd, ra, rb, d;
859 switch (get_op(inst)) {
861 switch (get_xop(inst)) {
863 case OP_31_XOP_LWBRX:
864 regs->gpr[rd] = 0xffffffff;
867 case OP_31_XOP_LWZUX:
868 regs->gpr[rd] = 0xffffffff;
869 regs->gpr[ra] += regs->gpr[rb];
873 regs->gpr[rd] = 0xff;
876 case OP_31_XOP_LBZUX:
877 regs->gpr[rd] = 0xff;
878 regs->gpr[ra] += regs->gpr[rb];
882 case OP_31_XOP_LHBRX:
883 regs->gpr[rd] = 0xffff;
886 case OP_31_XOP_LHZUX:
887 regs->gpr[rd] = 0xffff;
888 regs->gpr[ra] += regs->gpr[rb];
892 regs->gpr[rd] = ~0UL;
895 case OP_31_XOP_LHAUX:
896 regs->gpr[rd] = ~0UL;
897 regs->gpr[ra] += regs->gpr[rb];
906 regs->gpr[rd] = 0xffffffff;
910 regs->gpr[rd] = 0xffffffff;
911 regs->gpr[ra] += (s16)d;
915 regs->gpr[rd] = 0xff;
919 regs->gpr[rd] = 0xff;
920 regs->gpr[ra] += (s16)d;
924 regs->gpr[rd] = 0xffff;
928 regs->gpr[rd] = 0xffff;
929 regs->gpr[ra] += (s16)d;
933 regs->gpr[rd] = ~0UL;
937 regs->gpr[rd] = ~0UL;
938 regs->gpr[ra] += (s16)d;
948 static int is_in_pci_mem_space(phys_addr_t addr)
950 struct pci_controller *hose;
951 struct resource *res;
954 list_for_each_entry(hose, &hose_list, list_node) {
955 if (!(hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG))
958 for (i = 0; i < 3; i++) {
959 res = &hose->mem_resources[i];
960 if ((res->flags & IORESOURCE_MEM) &&
961 addr >= res->start && addr <= res->end)
968 int fsl_pci_mcheck_exception(struct pt_regs *regs)
972 phys_addr_t addr = 0;
974 /* Let KVM/QEMU deal with the exception */
975 if (regs->msr & MSR_GS)
978 #ifdef CONFIG_PHYS_64BIT
979 addr = mfspr(SPRN_MCARU);
982 addr += mfspr(SPRN_MCAR);
984 if (is_in_pci_mem_space(addr)) {
985 if (user_mode(regs)) {
987 ret = get_user(regs->nip, &inst);
990 ret = probe_kernel_address(regs->nip, inst);
993 if (mcheck_handle_load(regs, inst)) {
1003 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
1004 static const struct of_device_id pci_ids[] = {
1005 { .compatible = "fsl,mpc8540-pci", },
1006 { .compatible = "fsl,mpc8548-pcie", },
1007 { .compatible = "fsl,mpc8610-pci", },
1008 { .compatible = "fsl,mpc8641-pcie", },
1009 { .compatible = "fsl,qoriq-pcie", },
1010 { .compatible = "fsl,qoriq-pcie-v2.1", },
1011 { .compatible = "fsl,qoriq-pcie-v2.2", },
1012 { .compatible = "fsl,qoriq-pcie-v2.3", },
1013 { .compatible = "fsl,qoriq-pcie-v2.4", },
1014 { .compatible = "fsl,qoriq-pcie-v3.0", },
1017 * The following entries are for compatibility with older device
1020 { .compatible = "fsl,p1022-pcie", },
1021 { .compatible = "fsl,p4080-pcie", },
1026 struct device_node *fsl_pci_primary;
1028 void fsl_pci_assign_primary(void)
1030 struct device_node *np;
1032 /* Callers can specify the primary bus using other means. */
1033 if (fsl_pci_primary)
1036 /* If a PCI host bridge contains an ISA node, it's primary. */
1037 np = of_find_node_by_type(NULL, "isa");
1038 while ((fsl_pci_primary = of_get_parent(np))) {
1040 np = fsl_pci_primary;
1042 if (of_match_node(pci_ids, np) && of_device_is_available(np))
1047 * If there's no PCI host bridge with ISA, arbitrarily
1048 * designate one as primary. This can go away once
1049 * various bugs with primary-less systems are fixed.
1051 for_each_matching_node(np, pci_ids) {
1052 if (of_device_is_available(np)) {
1053 fsl_pci_primary = np;
1060 #ifdef CONFIG_PM_SLEEP
1061 static irqreturn_t fsl_pci_pme_handle(int irq, void *dev_id)
1063 struct pci_controller *hose = dev_id;
1064 struct ccsr_pci __iomem *pci = hose->private_data;
1067 dr = in_be32(&pci->pex_pme_mes_dr);
1071 out_be32(&pci->pex_pme_mes_dr, dr);
1076 static int fsl_pci_pme_probe(struct pci_controller *hose)
1078 struct ccsr_pci __iomem *pci;
1079 struct pci_dev *dev;
1084 /* Get hose's pci_dev */
1085 dev = list_first_entry(&hose->bus->devices, typeof(*dev), bus_list);
1088 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms);
1089 pms &= ~PCI_PM_CTRL_PME_ENABLE;
1090 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms);
1092 pme_irq = irq_of_parse_and_map(hose->dn, 0);
1094 dev_err(&dev->dev, "Failed to map PME interrupt.\n");
1099 res = devm_request_irq(hose->parent, pme_irq,
1104 dev_err(&dev->dev, "Unable to requiest irq %d for PME\n", pme_irq);
1105 irq_dispose_mapping(pme_irq);
1110 pci = hose->private_data;
1112 /* Enable PTOD, ENL23D & EXL23D */
1113 clrbits32(&pci->pex_pme_mes_disr,
1114 PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
1116 out_be32(&pci->pex_pme_mes_ier, 0);
1117 setbits32(&pci->pex_pme_mes_ier,
1118 PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
1121 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms);
1122 pms |= PCI_PM_CTRL_PME_ENABLE;
1123 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms);
1128 static void send_pme_turnoff_message(struct pci_controller *hose)
1130 struct ccsr_pci __iomem *pci = hose->private_data;
1134 /* Send PME_Turn_Off Message Request */
1135 setbits32(&pci->pex_pmcr, PEX_PMCR_PTOMR);
1137 /* Wait trun off done */
1138 for (i = 0; i < 150; i++) {
1139 dr = in_be32(&pci->pex_pme_mes_dr);
1141 out_be32(&pci->pex_pme_mes_dr, dr);
1149 static void fsl_pci_syscore_do_suspend(struct pci_controller *hose)
1151 send_pme_turnoff_message(hose);
1154 static int fsl_pci_syscore_suspend(void)
1156 struct pci_controller *hose, *tmp;
1158 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1159 fsl_pci_syscore_do_suspend(hose);
1164 static void fsl_pci_syscore_do_resume(struct pci_controller *hose)
1166 struct ccsr_pci __iomem *pci = hose->private_data;
1170 /* Send Exit L2 State Message */
1171 setbits32(&pci->pex_pmcr, PEX_PMCR_EXL2S);
1173 /* Wait exit done */
1174 for (i = 0; i < 150; i++) {
1175 dr = in_be32(&pci->pex_pme_mes_dr);
1177 out_be32(&pci->pex_pme_mes_dr, dr);
1184 setup_pci_atmu(hose);
1187 static void fsl_pci_syscore_resume(void)
1189 struct pci_controller *hose, *tmp;
1191 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1192 fsl_pci_syscore_do_resume(hose);
1195 static struct syscore_ops pci_syscore_pm_ops = {
1196 .suspend = fsl_pci_syscore_suspend,
1197 .resume = fsl_pci_syscore_resume,
1201 void fsl_pcibios_fixup_phb(struct pci_controller *phb)
1203 #ifdef CONFIG_PM_SLEEP
1204 fsl_pci_pme_probe(phb);
1208 static int fsl_pci_probe(struct platform_device *pdev)
1210 struct device_node *node;
1213 node = pdev->dev.of_node;
1214 ret = fsl_add_bridge(pdev, fsl_pci_primary == node);
1216 mpc85xx_pci_err_probe(pdev);
1221 static struct platform_driver fsl_pci_driver = {
1224 .of_match_table = pci_ids,
1226 .probe = fsl_pci_probe,
1229 static int __init fsl_pci_init(void)
1231 #ifdef CONFIG_PM_SLEEP
1232 register_syscore_ops(&pci_syscore_pm_ops);
1234 return platform_driver_register(&fsl_pci_driver);
1236 arch_initcall(fsl_pci_init);