2 * Support PCI/PCIe on PowerNV platforms
4 * Currently supports only P5IOC2
6 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/delay.h>
17 #include <linux/string.h>
18 #include <linux/init.h>
19 #include <linux/bootmem.h>
20 #include <linux/irq.h>
22 #include <linux/msi.h>
23 #include <linux/iommu.h>
25 #include <asm/sections.h>
28 #include <asm/pci-bridge.h>
29 #include <asm/machdep.h>
30 #include <asm/msi_bitmap.h>
31 #include <asm/ppc-pci.h>
33 #include <asm/iommu.h>
35 #include <asm/firmware.h>
36 #include <asm/eeh_event.h>
43 #define PCI_RESET_DELAY_US 3000000
45 #define cfg_dbg(fmt...) do { } while(0)
46 //#define cfg_dbg(fmt...) printk(fmt)
49 static int pnv_msi_check_device(struct pci_dev* pdev, int nvec, int type)
51 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
52 struct pnv_phb *phb = hose->private_data;
53 struct pci_dn *pdn = pci_get_pdn(pdev);
55 if (pdn && pdn->force_32bit_msi && !phb->msi32_support)
58 return (phb && phb->msi_bmp.bitmap) ? 0 : -ENODEV;
61 static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
63 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
64 struct pnv_phb *phb = hose->private_data;
65 struct msi_desc *entry;
74 list_for_each_entry(entry, &pdev->msi_list, list) {
75 if (!entry->msi_attrib.is_64 && !phb->msi32_support) {
76 pr_warn("%s: Supports only 64-bit MSIs\n",
80 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, 1);
82 pr_warn("%s: Failed to find a free MSI\n",
86 virq = irq_create_mapping(NULL, phb->msi_base + hwirq);
88 pr_warn("%s: Failed to map MSI to linux irq\n",
90 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
93 rc = phb->msi_setup(phb, pdev, phb->msi_base + hwirq,
94 virq, entry->msi_attrib.is_64, &msg);
96 pr_warn("%s: Failed to setup MSI\n", pci_name(pdev));
97 irq_dispose_mapping(virq);
98 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
101 irq_set_msi_desc(virq, entry);
102 write_msi_msg(virq, &msg);
107 static void pnv_teardown_msi_irqs(struct pci_dev *pdev)
109 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
110 struct pnv_phb *phb = hose->private_data;
111 struct msi_desc *entry;
116 list_for_each_entry(entry, &pdev->msi_list, list) {
117 if (entry->irq == NO_IRQ)
119 irq_set_msi_desc(entry->irq, NULL);
120 msi_bitmap_free_hwirqs(&phb->msi_bmp,
121 virq_to_hw(entry->irq) - phb->msi_base, 1);
122 irq_dispose_mapping(entry->irq);
125 #endif /* CONFIG_PCI_MSI */
127 static void pnv_pci_dump_p7ioc_diag_data(struct pci_controller *hose,
128 struct OpalIoPhbErrorCommon *common)
130 struct OpalIoP7IOCPhbErrorData *data;
133 data = (struct OpalIoP7IOCPhbErrorData *)common;
134 pr_info("P7IOC PHB#%d Diag-data (Version: %d)\n\n",
135 hose->global_number, common->version);
137 pr_info(" brdgCtl: %08x\n", data->brdgCtl);
139 pr_info(" portStatusReg: %08x\n", data->portStatusReg);
140 pr_info(" rootCmplxStatus: %08x\n", data->rootCmplxStatus);
141 pr_info(" busAgentStatus: %08x\n", data->busAgentStatus);
143 pr_info(" deviceStatus: %08x\n", data->deviceStatus);
144 pr_info(" slotStatus: %08x\n", data->slotStatus);
145 pr_info(" linkStatus: %08x\n", data->linkStatus);
146 pr_info(" devCmdStatus: %08x\n", data->devCmdStatus);
147 pr_info(" devSecStatus: %08x\n", data->devSecStatus);
149 pr_info(" rootErrorStatus: %08x\n", data->rootErrorStatus);
150 pr_info(" uncorrErrorStatus: %08x\n", data->uncorrErrorStatus);
151 pr_info(" corrErrorStatus: %08x\n", data->corrErrorStatus);
152 pr_info(" tlpHdr1: %08x\n", data->tlpHdr1);
153 pr_info(" tlpHdr2: %08x\n", data->tlpHdr2);
154 pr_info(" tlpHdr3: %08x\n", data->tlpHdr3);
155 pr_info(" tlpHdr4: %08x\n", data->tlpHdr4);
156 pr_info(" sourceId: %08x\n", data->sourceId);
157 pr_info(" errorClass: %016llx\n", data->errorClass);
158 pr_info(" correlator: %016llx\n", data->correlator);
159 pr_info(" p7iocPlssr: %016llx\n", data->p7iocPlssr);
160 pr_info(" p7iocCsr: %016llx\n", data->p7iocCsr);
161 pr_info(" lemFir: %016llx\n", data->lemFir);
162 pr_info(" lemErrorMask: %016llx\n", data->lemErrorMask);
163 pr_info(" lemWOF: %016llx\n", data->lemWOF);
164 pr_info(" phbErrorStatus: %016llx\n", data->phbErrorStatus);
165 pr_info(" phbFirstErrorStatus: %016llx\n", data->phbFirstErrorStatus);
166 pr_info(" phbErrorLog0: %016llx\n", data->phbErrorLog0);
167 pr_info(" phbErrorLog1: %016llx\n", data->phbErrorLog1);
168 pr_info(" mmioErrorStatus: %016llx\n", data->mmioErrorStatus);
169 pr_info(" mmioFirstErrorStatus: %016llx\n", data->mmioFirstErrorStatus);
170 pr_info(" mmioErrorLog0: %016llx\n", data->mmioErrorLog0);
171 pr_info(" mmioErrorLog1: %016llx\n", data->mmioErrorLog1);
172 pr_info(" dma0ErrorStatus: %016llx\n", data->dma0ErrorStatus);
173 pr_info(" dma0FirstErrorStatus: %016llx\n", data->dma0FirstErrorStatus);
174 pr_info(" dma0ErrorLog0: %016llx\n", data->dma0ErrorLog0);
175 pr_info(" dma0ErrorLog1: %016llx\n", data->dma0ErrorLog1);
176 pr_info(" dma1ErrorStatus: %016llx\n", data->dma1ErrorStatus);
177 pr_info(" dma1FirstErrorStatus: %016llx\n", data->dma1FirstErrorStatus);
178 pr_info(" dma1ErrorLog0: %016llx\n", data->dma1ErrorLog0);
179 pr_info(" dma1ErrorLog1: %016llx\n", data->dma1ErrorLog1);
181 for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) {
182 if ((data->pestA[i] >> 63) == 0 &&
183 (data->pestB[i] >> 63) == 0)
186 pr_info(" PE[%3d] PESTA: %016llx\n", i, data->pestA[i]);
187 pr_info(" PESTB: %016llx\n", data->pestB[i]);
191 static void pnv_pci_dump_phb3_diag_data(struct pci_controller *hose,
192 struct OpalIoPhbErrorCommon *common)
194 struct OpalIoPhb3ErrorData *data;
197 data = (struct OpalIoPhb3ErrorData*)common;
198 pr_info("PHB3 PHB#%d Diag-data (Version: %d)\n\n",
199 hose->global_number, common->version);
201 pr_info(" brdgCtl: %08x\n", data->brdgCtl);
203 pr_info(" portStatusReg: %08x\n", data->portStatusReg);
204 pr_info(" rootCmplxStatus: %08x\n", data->rootCmplxStatus);
205 pr_info(" busAgentStatus: %08x\n", data->busAgentStatus);
207 pr_info(" deviceStatus: %08x\n", data->deviceStatus);
208 pr_info(" slotStatus: %08x\n", data->slotStatus);
209 pr_info(" linkStatus: %08x\n", data->linkStatus);
210 pr_info(" devCmdStatus: %08x\n", data->devCmdStatus);
211 pr_info(" devSecStatus: %08x\n", data->devSecStatus);
213 pr_info(" rootErrorStatus: %08x\n", data->rootErrorStatus);
214 pr_info(" uncorrErrorStatus: %08x\n", data->uncorrErrorStatus);
215 pr_info(" corrErrorStatus: %08x\n", data->corrErrorStatus);
216 pr_info(" tlpHdr1: %08x\n", data->tlpHdr1);
217 pr_info(" tlpHdr2: %08x\n", data->tlpHdr2);
218 pr_info(" tlpHdr3: %08x\n", data->tlpHdr3);
219 pr_info(" tlpHdr4: %08x\n", data->tlpHdr4);
220 pr_info(" sourceId: %08x\n", data->sourceId);
221 pr_info(" errorClass: %016llx\n", data->errorClass);
222 pr_info(" correlator: %016llx\n", data->correlator);
224 pr_info(" nFir: %016llx\n", data->nFir);
225 pr_info(" nFirMask: %016llx\n", data->nFirMask);
226 pr_info(" nFirWOF: %016llx\n", data->nFirWOF);
227 pr_info(" PhbPlssr: %016llx\n", data->phbPlssr);
228 pr_info(" PhbCsr: %016llx\n", data->phbCsr);
229 pr_info(" lemFir: %016llx\n", data->lemFir);
230 pr_info(" lemErrorMask: %016llx\n", data->lemErrorMask);
231 pr_info(" lemWOF: %016llx\n", data->lemWOF);
232 pr_info(" phbErrorStatus: %016llx\n", data->phbErrorStatus);
233 pr_info(" phbFirstErrorStatus: %016llx\n", data->phbFirstErrorStatus);
234 pr_info(" phbErrorLog0: %016llx\n", data->phbErrorLog0);
235 pr_info(" phbErrorLog1: %016llx\n", data->phbErrorLog1);
236 pr_info(" mmioErrorStatus: %016llx\n", data->mmioErrorStatus);
237 pr_info(" mmioFirstErrorStatus: %016llx\n", data->mmioFirstErrorStatus);
238 pr_info(" mmioErrorLog0: %016llx\n", data->mmioErrorLog0);
239 pr_info(" mmioErrorLog1: %016llx\n", data->mmioErrorLog1);
240 pr_info(" dma0ErrorStatus: %016llx\n", data->dma0ErrorStatus);
241 pr_info(" dma0FirstErrorStatus: %016llx\n", data->dma0FirstErrorStatus);
242 pr_info(" dma0ErrorLog0: %016llx\n", data->dma0ErrorLog0);
243 pr_info(" dma0ErrorLog1: %016llx\n", data->dma0ErrorLog1);
244 pr_info(" dma1ErrorStatus: %016llx\n", data->dma1ErrorStatus);
245 pr_info(" dma1FirstErrorStatus: %016llx\n", data->dma1FirstErrorStatus);
246 pr_info(" dma1ErrorLog0: %016llx\n", data->dma1ErrorLog0);
247 pr_info(" dma1ErrorLog1: %016llx\n", data->dma1ErrorLog1);
249 for (i = 0; i < OPAL_PHB3_NUM_PEST_REGS; i++) {
250 if ((data->pestA[i] >> 63) == 0 &&
251 (data->pestB[i] >> 63) == 0)
254 pr_info(" PE[%3d] PESTA: %016llx\n", i, data->pestA[i]);
255 pr_info(" PESTB: %016llx\n", data->pestB[i]);
259 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
260 unsigned char *log_buff)
262 struct OpalIoPhbErrorCommon *common;
264 if (!hose || !log_buff)
267 common = (struct OpalIoPhbErrorCommon *)log_buff;
268 switch (common->ioType) {
269 case OPAL_PHB_ERROR_DATA_TYPE_P7IOC:
270 pnv_pci_dump_p7ioc_diag_data(hose, common);
272 case OPAL_PHB_ERROR_DATA_TYPE_PHB3:
273 pnv_pci_dump_phb3_diag_data(hose, common);
276 pr_warn("%s: Unrecognized ioType %d\n",
277 __func__, common->ioType);
281 static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no)
283 unsigned long flags, rc;
286 spin_lock_irqsave(&phb->lock, flags);
288 rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob,
289 PNV_PCI_DIAG_BUF_SIZE);
290 has_diag = (rc == OPAL_SUCCESS);
292 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
293 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
295 pr_warning("PCI %d: Failed to clear EEH freeze state"
296 " for PE#%d, err %ld\n",
297 phb->hose->global_number, pe_no, rc);
299 /* For now, let's only display the diag buffer when we fail to clear
300 * the EEH status. We'll do more sensible things later when we have
301 * proper EEH support. We need to make sure we don't pollute ourselves
302 * with the normal errors generated when probing empty slots
305 pnv_pci_dump_phb_diag_data(phb->hose, phb->diag.blob);
307 pr_warning("PCI %d: No diag data available\n",
308 phb->hose->global_number);
311 spin_unlock_irqrestore(&phb->lock, flags);
314 static void pnv_pci_config_check_eeh(struct pnv_phb *phb,
315 struct device_node *dn)
323 * Get the PE#. During the PCI probe stage, we might not
324 * setup that yet. So all ER errors should be mapped to
327 pe_no = PCI_DN(dn)->pe_number;
328 if (pe_no == IODA_INVALID_PE) {
329 if (phb->type == PNV_PHB_P5IOC2)
332 pe_no = phb->ioda.reserved_pe;
335 /* Read freeze status */
336 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, &fstate, &pcierr,
339 pr_warning("%s: Can't read EEH status (PE#%d) for "
341 __func__, pe_no, dn->full_name, rc);
344 cfg_dbg(" -> EEH check, bdfn=%04x PE#%d fstate=%x\n",
345 (PCI_DN(dn)->busno << 8) | (PCI_DN(dn)->devfn),
348 pnv_pci_handle_eeh_config(phb, pe_no);
351 int pnv_pci_cfg_read(struct device_node *dn,
352 int where, int size, u32 *val)
354 struct pci_dn *pdn = PCI_DN(dn);
355 struct pnv_phb *phb = pdn->phb->private_data;
356 u32 bdfn = (pdn->busno << 8) | pdn->devfn;
358 struct eeh_pe *phb_pe = NULL;
365 rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8);
366 *val = (rc == OPAL_SUCCESS) ? v8 : 0xff;
371 rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where,
373 *val = (rc == OPAL_SUCCESS) ? be16_to_cpu(v16) : 0xffff;
378 rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32);
379 *val = (rc == OPAL_SUCCESS) ? be32_to_cpu(v32) : 0xffffffff;
383 return PCIBIOS_FUNC_NOT_SUPPORTED;
385 cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n",
386 __func__, pdn->busno, pdn->devfn, where, size, *val);
389 * Check if the specified PE has been put into frozen
390 * state. On the other hand, we needn't do that while
391 * the PHB has been put into frozen state because of
395 phb_pe = eeh_phb_pe_get(pdn->phb);
396 if (phb_pe && (phb_pe->state & EEH_PE_ISOLATED))
397 return PCIBIOS_SUCCESSFUL;
399 if (phb->eeh_state & PNV_EEH_STATE_ENABLED) {
400 if (*val == EEH_IO_ERROR_VALUE(size) &&
401 eeh_dev_check_failure(of_node_to_eeh_dev(dn)))
402 return PCIBIOS_DEVICE_NOT_FOUND;
404 pnv_pci_config_check_eeh(phb, dn);
407 pnv_pci_config_check_eeh(phb, dn);
410 return PCIBIOS_SUCCESSFUL;
413 int pnv_pci_cfg_write(struct device_node *dn,
414 int where, int size, u32 val)
416 struct pci_dn *pdn = PCI_DN(dn);
417 struct pnv_phb *phb = pdn->phb->private_data;
418 u32 bdfn = (pdn->busno << 8) | pdn->devfn;
420 cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n",
421 pdn->busno, pdn->devfn, where, size, val);
424 opal_pci_config_write_byte(phb->opal_id, bdfn, where, val);
427 opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val);
430 opal_pci_config_write_word(phb->opal_id, bdfn, where, val);
433 return PCIBIOS_FUNC_NOT_SUPPORTED;
436 /* Check if the PHB got frozen due to an error (no response) */
438 if (!(phb->eeh_state & PNV_EEH_STATE_ENABLED))
439 pnv_pci_config_check_eeh(phb, dn);
441 pnv_pci_config_check_eeh(phb, dn);
444 return PCIBIOS_SUCCESSFUL;
447 static int pnv_pci_read_config(struct pci_bus *bus,
449 int where, int size, u32 *val)
451 struct device_node *dn, *busdn = pci_bus_to_OF_node(bus);
454 for (dn = busdn->child; dn; dn = dn->sibling) {
456 if (pdn && pdn->devfn == devfn)
457 return pnv_pci_cfg_read(dn, where, size, val);
461 return PCIBIOS_DEVICE_NOT_FOUND;
465 static int pnv_pci_write_config(struct pci_bus *bus,
467 int where, int size, u32 val)
469 struct device_node *dn, *busdn = pci_bus_to_OF_node(bus);
472 for (dn = busdn->child; dn; dn = dn->sibling) {
474 if (pdn && pdn->devfn == devfn)
475 return pnv_pci_cfg_write(dn, where, size, val);
478 return PCIBIOS_DEVICE_NOT_FOUND;
481 struct pci_ops pnv_pci_ops = {
482 .read = pnv_pci_read_config,
483 .write = pnv_pci_write_config,
486 static int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
487 unsigned long uaddr, enum dma_data_direction direction,
488 struct dma_attrs *attrs, bool rm)
494 proto_tce = TCE_PCI_READ; // Read allowed
496 if (direction != DMA_TO_DEVICE)
497 proto_tce |= TCE_PCI_WRITE;
499 tces = tcep = ((__be64 *)tbl->it_base) + index - tbl->it_offset;
500 rpn = __pa(uaddr) >> TCE_SHIFT;
503 *(tcep++) = cpu_to_be64(proto_tce | (rpn++ << TCE_RPN_SHIFT));
505 /* Some implementations won't cache invalid TCEs and thus may not
506 * need that flush. We'll probably turn it_type into a bit mask
507 * of flags if that becomes the case
509 if (tbl->it_type & TCE_PCI_SWINV_CREATE)
510 pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1, rm);
515 static int pnv_tce_build_vm(struct iommu_table *tbl, long index, long npages,
517 enum dma_data_direction direction,
518 struct dma_attrs *attrs)
520 return pnv_tce_build(tbl, index, npages, uaddr, direction, attrs,
524 static void pnv_tce_free(struct iommu_table *tbl, long index, long npages,
529 tces = tcep = ((__be64 *)tbl->it_base) + index - tbl->it_offset;
532 *(tcep++) = cpu_to_be64(0);
534 if (tbl->it_type & TCE_PCI_SWINV_FREE)
535 pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1, rm);
538 static void pnv_tce_free_vm(struct iommu_table *tbl, long index, long npages)
540 pnv_tce_free(tbl, index, npages, false);
543 static unsigned long pnv_tce_get(struct iommu_table *tbl, long index)
545 return ((u64 *)tbl->it_base)[index - tbl->it_offset];
548 static int pnv_tce_build_rm(struct iommu_table *tbl, long index, long npages,
550 enum dma_data_direction direction,
551 struct dma_attrs *attrs)
553 return pnv_tce_build(tbl, index, npages, uaddr, direction, attrs, true);
556 static void pnv_tce_free_rm(struct iommu_table *tbl, long index, long npages)
558 pnv_tce_free(tbl, index, npages, true);
561 void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
562 void *tce_mem, u64 tce_size,
565 tbl->it_blocksize = 16;
566 tbl->it_base = (unsigned long)tce_mem;
567 tbl->it_page_shift = IOMMU_PAGE_SHIFT_4K;
568 tbl->it_offset = dma_offset >> tbl->it_page_shift;
570 tbl->it_size = tce_size >> 3;
572 tbl->it_type = TCE_PCI;
575 static struct iommu_table *pnv_pci_setup_bml_iommu(struct pci_controller *hose)
577 struct iommu_table *tbl;
578 const __be64 *basep, *swinvp;
581 basep = of_get_property(hose->dn, "linux,tce-base", NULL);
582 sizep = of_get_property(hose->dn, "linux,tce-size", NULL);
583 if (basep == NULL || sizep == NULL) {
584 pr_err("PCI: %s has missing tce entries !\n",
585 hose->dn->full_name);
588 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, hose->node);
591 pnv_pci_setup_iommu_table(tbl, __va(be64_to_cpup(basep)),
592 be32_to_cpup(sizep), 0);
593 iommu_init_table(tbl, hose->node);
594 iommu_register_group(tbl, pci_domain_nr(hose->bus), 0);
596 /* Deal with SW invalidated TCEs when needed (BML way) */
597 swinvp = of_get_property(hose->dn, "linux,tce-sw-invalidate-info",
600 tbl->it_busno = be64_to_cpu(swinvp[1]);
601 tbl->it_index = (unsigned long)ioremap(be64_to_cpup(swinvp), 8);
602 tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE;
607 static void pnv_pci_dma_fallback_setup(struct pci_controller *hose,
608 struct pci_dev *pdev)
610 struct device_node *np = pci_bus_to_OF_node(hose->bus);
616 if (!pdn->iommu_table)
617 pdn->iommu_table = pnv_pci_setup_bml_iommu(hose);
618 if (!pdn->iommu_table)
620 set_iommu_table_base_and_group(&pdev->dev, pdn->iommu_table);
623 static void pnv_pci_dma_dev_setup(struct pci_dev *pdev)
625 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
626 struct pnv_phb *phb = hose->private_data;
628 /* If we have no phb structure, try to setup a fallback based on
629 * the device-tree (RTAS PCI for example)
631 if (phb && phb->dma_dev_setup)
632 phb->dma_dev_setup(phb, pdev);
634 pnv_pci_dma_fallback_setup(hose, pdev);
637 int pnv_pci_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
639 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
640 struct pnv_phb *phb = hose->private_data;
642 if (phb && phb->dma_set_mask)
643 return phb->dma_set_mask(phb, pdev, dma_mask);
644 return __dma_set_mask(&pdev->dev, dma_mask);
647 void pnv_pci_shutdown(void)
649 struct pci_controller *hose;
651 list_for_each_entry(hose, &hose_list, list_node) {
652 struct pnv_phb *phb = hose->private_data;
654 if (phb && phb->shutdown)
659 /* Fixup wrong class code in p7ioc and p8 root complex */
660 static void pnv_p7ioc_rc_quirk(struct pci_dev *dev)
662 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
664 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk);
666 static int pnv_pci_probe_mode(struct pci_bus *bus)
668 struct pci_controller *hose = pci_bus_to_host(bus);
669 const __be64 *tstamp;
673 /* We hijack this as a way to ensure we have waited long
674 * enough since the reset was lifted on the PCI bus
676 if (bus != hose->bus)
677 return PCI_PROBE_NORMAL;
678 tstamp = of_get_property(hose->dn, "reset-clear-timestamp", NULL);
679 if (!tstamp || !*tstamp)
680 return PCI_PROBE_NORMAL;
682 now = mftb() / tb_ticks_per_usec;
683 target = (be64_to_cpup(tstamp) / tb_ticks_per_usec)
684 + PCI_RESET_DELAY_US;
686 pr_devel("pci %04d: Reset target: 0x%llx now: 0x%llx\n",
687 hose->global_number, target, now);
690 msleep((target - now + 999) / 1000);
692 return PCI_PROBE_NORMAL;
695 void __init pnv_pci_init(void)
697 struct device_node *np;
699 pci_add_flags(PCI_CAN_SKIP_ISA_ALIGN);
701 /* OPAL absent, try POPAL first then RTAS detection of PHBs */
702 if (!firmware_has_feature(FW_FEATURE_OPAL)) {
703 #ifdef CONFIG_PPC_POWERNV_RTAS
704 init_pci_config_tokens();
705 find_and_init_phbs();
706 #endif /* CONFIG_PPC_POWERNV_RTAS */
708 /* OPAL is here, do our normal stuff */
712 /* Look for IODA IO-Hubs. We don't support mixing IODA
713 * and p5ioc2 due to the need to change some global
716 for_each_compatible_node(np, NULL, "ibm,ioda-hub") {
717 pnv_pci_init_ioda_hub(np);
721 /* Look for p5ioc2 IO-Hubs */
723 for_each_compatible_node(np, NULL, "ibm,p5ioc2")
724 pnv_pci_init_p5ioc2_hub(np);
726 /* Look for ioda2 built-in PHB3's */
727 for_each_compatible_node(np, NULL, "ibm,ioda2-phb")
728 pnv_pci_init_ioda2_phb(np);
731 /* Setup the linkage between OF nodes and PHBs */
734 /* Configure IOMMU DMA hooks */
735 ppc_md.pci_dma_dev_setup = pnv_pci_dma_dev_setup;
736 ppc_md.tce_build = pnv_tce_build_vm;
737 ppc_md.tce_free = pnv_tce_free_vm;
738 ppc_md.tce_build_rm = pnv_tce_build_rm;
739 ppc_md.tce_free_rm = pnv_tce_free_rm;
740 ppc_md.tce_get = pnv_tce_get;
741 ppc_md.pci_probe_mode = pnv_pci_probe_mode;
742 set_pci_dma_ops(&dma_iommu_ops);
745 #ifdef CONFIG_PCI_MSI
746 ppc_md.msi_check_device = pnv_msi_check_device;
747 ppc_md.setup_msi_irqs = pnv_setup_msi_irqs;
748 ppc_md.teardown_msi_irqs = pnv_teardown_msi_irqs;
752 static int tce_iommu_bus_notifier(struct notifier_block *nb,
753 unsigned long action, void *data)
755 struct device *dev = data;
758 case BUS_NOTIFY_ADD_DEVICE:
759 return iommu_add_device(dev);
760 case BUS_NOTIFY_DEL_DEVICE:
761 if (dev->iommu_group)
762 iommu_del_device(dev);
769 static struct notifier_block tce_iommu_bus_nb = {
770 .notifier_call = tce_iommu_bus_notifier,
773 static int __init tce_iommu_bus_notifier_init(void)
775 bus_register_notifier(&pci_bus_type, &tce_iommu_bus_nb);
779 subsys_initcall_sync(tce_iommu_bus_notifier_init);