2 * Support PCI/PCIe on PowerNV platforms
4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/crash_dump.h>
17 #include <linux/debugfs.h>
18 #include <linux/delay.h>
19 #include <linux/string.h>
20 #include <linux/init.h>
21 #include <linux/bootmem.h>
22 #include <linux/irq.h>
24 #include <linux/msi.h>
25 #include <linux/memblock.h>
26 #include <linux/iommu.h>
27 #include <linux/rculist.h>
28 #include <linux/sizes.h>
30 #include <asm/sections.h>
33 #include <asm/pci-bridge.h>
34 #include <asm/machdep.h>
35 #include <asm/msi_bitmap.h>
36 #include <asm/ppc-pci.h>
38 #include <asm/iommu.h>
41 #include <asm/debug.h>
42 #include <asm/firmware.h>
43 #include <asm/pnv-pci.h>
44 #include <asm/mmzone.h>
46 #include <misc/cxl-base.h>
51 #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */
52 #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */
53 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000
55 #define POWERNV_IOMMU_DEFAULT_LEVELS 1
56 #define POWERNV_IOMMU_MAX_LEVELS 5
58 static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU" };
59 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
61 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
73 if (pe->flags & PNV_IODA_PE_DEV)
74 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
75 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
76 sprintf(pfix, "%04x:%02x ",
77 pci_domain_nr(pe->pbus), pe->pbus->number);
79 else if (pe->flags & PNV_IODA_PE_VF)
80 sprintf(pfix, "%04x:%02x:%2x.%d",
81 pci_domain_nr(pe->parent_dev->bus),
82 (pe->rid & 0xff00) >> 8,
83 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
84 #endif /* CONFIG_PCI_IOV*/
86 printk("%spci %s: [PE# %.3d] %pV",
87 level, pfix, pe->pe_number, &vaf);
92 static bool pnv_iommu_bypass_disabled __read_mostly;
94 static int __init iommu_setup(char *str)
100 if (!strncmp(str, "nobypass", 8)) {
101 pnv_iommu_bypass_disabled = true;
102 pr_info("PowerNV: IOMMU bypass window disabled.\n");
105 str += strcspn(str, ",");
112 early_param("iommu", iommu_setup);
114 static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r)
117 * WARNING: We cannot rely on the resource flags. The Linux PCI
118 * allocation code sometimes decides to put a 64-bit prefetchable
119 * BAR in the 32-bit window, so we have to compare the addresses.
121 * For simplicity we only test resource start.
123 return (r->start >= phb->ioda.m64_base &&
124 r->start < (phb->ioda.m64_base + phb->ioda.m64_size));
127 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
129 phb->ioda.pe_array[pe_no].phb = phb;
130 phb->ioda.pe_array[pe_no].pe_number = pe_no;
132 return &phb->ioda.pe_array[pe_no];
135 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
137 if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) {
138 pr_warn("%s: Invalid PE %d on PHB#%x\n",
139 __func__, pe_no, phb->hose->global_number);
143 if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
144 pr_debug("%s: PE %d was reserved on PHB#%x\n",
145 __func__, pe_no, phb->hose->global_number);
147 pnv_ioda_init_pe(phb, pe_no);
150 static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb)
152 unsigned long pe = phb->ioda.total_pe_num - 1;
154 for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) {
155 if (!test_and_set_bit(pe, phb->ioda.pe_alloc))
156 return pnv_ioda_init_pe(phb, pe);
162 static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
164 struct pnv_phb *phb = pe->phb;
168 memset(pe, 0, sizeof(struct pnv_ioda_pe));
169 clear_bit(pe->pe_number, phb->ioda.pe_alloc);
172 /* The default M64 BAR is shared by all PEs */
173 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
179 /* Configure the default M64 BAR */
180 rc = opal_pci_set_phb_mem_window(phb->opal_id,
181 OPAL_M64_WINDOW_TYPE,
182 phb->ioda.m64_bar_idx,
186 if (rc != OPAL_SUCCESS) {
187 desc = "configuring";
191 /* Enable the default M64 BAR */
192 rc = opal_pci_phb_mmio_enable(phb->opal_id,
193 OPAL_M64_WINDOW_TYPE,
194 phb->ioda.m64_bar_idx,
195 OPAL_ENABLE_M64_SPLIT);
196 if (rc != OPAL_SUCCESS) {
202 * Exclude the segments for reserved and root bus PE, which
203 * are first or last two PEs.
205 r = &phb->hose->mem_resources[1];
206 if (phb->ioda.reserved_pe_idx == 0)
207 r->start += (2 * phb->ioda.m64_segsize);
208 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
209 r->end -= (2 * phb->ioda.m64_segsize);
211 pr_warn(" Cannot strip M64 segment for reserved PE#%d\n",
212 phb->ioda.reserved_pe_idx);
217 pr_warn(" Failure %lld %s M64 BAR#%d\n",
218 rc, desc, phb->ioda.m64_bar_idx);
219 opal_pci_phb_mmio_enable(phb->opal_id,
220 OPAL_M64_WINDOW_TYPE,
221 phb->ioda.m64_bar_idx,
226 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev,
227 unsigned long *pe_bitmap)
229 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
230 struct pnv_phb *phb = hose->private_data;
232 resource_size_t base, sgsz, start, end;
235 base = phb->ioda.m64_base;
236 sgsz = phb->ioda.m64_segsize;
237 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
238 r = &pdev->resource[i];
239 if (!r->parent || !pnv_pci_is_m64(phb, r))
242 start = _ALIGN_DOWN(r->start - base, sgsz);
243 end = _ALIGN_UP(r->end - base, sgsz);
244 for (segno = start / sgsz; segno < end / sgsz; segno++) {
246 set_bit(segno, pe_bitmap);
248 pnv_ioda_reserve_pe(phb, segno);
253 static int pnv_ioda1_init_m64(struct pnv_phb *phb)
259 * There are 16 M64 BARs, each of which has 8 segments. So
260 * there are as many M64 segments as the maximum number of
263 for (index = 0; index < PNV_IODA1_M64_NUM; index++) {
264 unsigned long base, segsz = phb->ioda.m64_segsize;
267 base = phb->ioda.m64_base +
268 index * PNV_IODA1_M64_SEGS * segsz;
269 rc = opal_pci_set_phb_mem_window(phb->opal_id,
270 OPAL_M64_WINDOW_TYPE, index, base, 0,
271 PNV_IODA1_M64_SEGS * segsz);
272 if (rc != OPAL_SUCCESS) {
273 pr_warn(" Error %lld setting M64 PHB#%d-BAR#%d\n",
274 rc, phb->hose->global_number, index);
278 rc = opal_pci_phb_mmio_enable(phb->opal_id,
279 OPAL_M64_WINDOW_TYPE, index,
280 OPAL_ENABLE_M64_SPLIT);
281 if (rc != OPAL_SUCCESS) {
282 pr_warn(" Error %lld enabling M64 PHB#%d-BAR#%d\n",
283 rc, phb->hose->global_number, index);
289 * Exclude the segments for reserved and root bus PE, which
290 * are first or last two PEs.
292 r = &phb->hose->mem_resources[1];
293 if (phb->ioda.reserved_pe_idx == 0)
294 r->start += (2 * phb->ioda.m64_segsize);
295 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
296 r->end -= (2 * phb->ioda.m64_segsize);
298 WARN(1, "Wrong reserved PE#%d on PHB#%d\n",
299 phb->ioda.reserved_pe_idx, phb->hose->global_number);
304 for ( ; index >= 0; index--)
305 opal_pci_phb_mmio_enable(phb->opal_id,
306 OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64);
311 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus,
312 unsigned long *pe_bitmap,
315 struct pci_dev *pdev;
317 list_for_each_entry(pdev, &bus->devices, bus_list) {
318 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap);
320 if (all && pdev->subordinate)
321 pnv_ioda_reserve_m64_pe(pdev->subordinate,
326 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all)
328 struct pci_controller *hose = pci_bus_to_host(bus);
329 struct pnv_phb *phb = hose->private_data;
330 struct pnv_ioda_pe *master_pe, *pe;
331 unsigned long size, *pe_alloc;
334 /* Root bus shouldn't use M64 */
335 if (pci_is_root_bus(bus))
338 /* Allocate bitmap */
339 size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
340 pe_alloc = kzalloc(size, GFP_KERNEL);
342 pr_warn("%s: Out of memory !\n",
347 /* Figure out reserved PE numbers by the PE */
348 pnv_ioda_reserve_m64_pe(bus, pe_alloc, all);
351 * the current bus might not own M64 window and that's all
352 * contributed by its child buses. For the case, we needn't
353 * pick M64 dependent PE#.
355 if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) {
361 * Figure out the master PE and put all slave PEs to master
362 * PE's list to form compound PE.
366 while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) <
367 phb->ioda.total_pe_num) {
368 pe = &phb->ioda.pe_array[i];
370 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
372 pe->flags |= PNV_IODA_PE_MASTER;
373 INIT_LIST_HEAD(&pe->slaves);
376 pe->flags |= PNV_IODA_PE_SLAVE;
377 pe->master = master_pe;
378 list_add_tail(&pe->list, &master_pe->slaves);
382 * P7IOC supports M64DT, which helps mapping M64 segment
383 * to one particular PE#. However, PHB3 has fixed mapping
384 * between M64 segment and PE#. In order to have same logic
385 * for P7IOC and PHB3, we enforce fixed mapping between M64
386 * segment and PE# on P7IOC.
388 if (phb->type == PNV_PHB_IODA1) {
391 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
392 pe->pe_number, OPAL_M64_WINDOW_TYPE,
393 pe->pe_number / PNV_IODA1_M64_SEGS,
394 pe->pe_number % PNV_IODA1_M64_SEGS);
395 if (rc != OPAL_SUCCESS)
396 pr_warn("%s: Error %lld mapping M64 for PHB#%d-PE#%d\n",
397 __func__, rc, phb->hose->global_number,
406 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
408 struct pci_controller *hose = phb->hose;
409 struct device_node *dn = hose->dn;
410 struct resource *res;
415 if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) {
416 pr_info(" Not support M64 window\n");
420 if (!firmware_has_feature(FW_FEATURE_OPAL)) {
421 pr_info(" Firmware too old to support M64 window\n");
425 r = of_get_property(dn, "ibm,opal-m64-window", NULL);
427 pr_info(" No <ibm,opal-m64-window> on %s\n",
433 * Find the available M64 BAR range and pickup the last one for
434 * covering the whole 64-bits space. We support only one range.
436 if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges",
438 /* In absence of the property, assume 0..15 */
442 /* We only support 64 bits in our allocator */
443 if (m64_range[1] > 63) {
444 pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n",
445 __func__, m64_range[1], phb->hose->global_number);
448 /* Empty range, no m64 */
449 if (m64_range[1] <= m64_range[0]) {
450 pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n",
451 __func__, phb->hose->global_number);
455 /* Configure M64 informations */
456 res = &hose->mem_resources[1];
457 res->name = dn->full_name;
458 res->start = of_translate_address(dn, r + 2);
459 res->end = res->start + of_read_number(r + 4, 2) - 1;
460 res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
461 pci_addr = of_read_number(r, 2);
462 hose->mem_offset[1] = res->start - pci_addr;
464 phb->ioda.m64_size = resource_size(res);
465 phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num;
466 phb->ioda.m64_base = pci_addr;
468 /* This lines up nicely with the display from processing OF ranges */
469 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n",
470 res->start, res->end, pci_addr, m64_range[0],
471 m64_range[0] + m64_range[1] - 1);
473 /* Mark all M64 used up by default */
474 phb->ioda.m64_bar_alloc = (unsigned long)-1;
476 /* Use last M64 BAR to cover M64 window */
478 phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1];
480 pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx);
482 /* Mark remaining ones free */
483 for (i = m64_range[0]; i < m64_range[1]; i++)
484 clear_bit(i, &phb->ioda.m64_bar_alloc);
487 * Setup init functions for M64 based on IODA version, IODA3 uses
490 if (phb->type == PNV_PHB_IODA1)
491 phb->init_m64 = pnv_ioda1_init_m64;
493 phb->init_m64 = pnv_ioda2_init_m64;
494 phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe;
495 phb->pick_m64_pe = pnv_ioda_pick_m64_pe;
498 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
500 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
501 struct pnv_ioda_pe *slave;
504 /* Fetch master PE */
505 if (pe->flags & PNV_IODA_PE_SLAVE) {
507 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
510 pe_no = pe->pe_number;
513 /* Freeze master PE */
514 rc = opal_pci_eeh_freeze_set(phb->opal_id,
516 OPAL_EEH_ACTION_SET_FREEZE_ALL);
517 if (rc != OPAL_SUCCESS) {
518 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
519 __func__, rc, phb->hose->global_number, pe_no);
523 /* Freeze slave PEs */
524 if (!(pe->flags & PNV_IODA_PE_MASTER))
527 list_for_each_entry(slave, &pe->slaves, list) {
528 rc = opal_pci_eeh_freeze_set(phb->opal_id,
530 OPAL_EEH_ACTION_SET_FREEZE_ALL);
531 if (rc != OPAL_SUCCESS)
532 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
533 __func__, rc, phb->hose->global_number,
538 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
540 struct pnv_ioda_pe *pe, *slave;
544 pe = &phb->ioda.pe_array[pe_no];
545 if (pe->flags & PNV_IODA_PE_SLAVE) {
547 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
548 pe_no = pe->pe_number;
551 /* Clear frozen state for master PE */
552 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
553 if (rc != OPAL_SUCCESS) {
554 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
555 __func__, rc, opt, phb->hose->global_number, pe_no);
559 if (!(pe->flags & PNV_IODA_PE_MASTER))
562 /* Clear frozen state for slave PEs */
563 list_for_each_entry(slave, &pe->slaves, list) {
564 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
567 if (rc != OPAL_SUCCESS) {
568 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
569 __func__, rc, opt, phb->hose->global_number,
578 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
580 struct pnv_ioda_pe *slave, *pe;
585 /* Sanity check on PE number */
586 if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num)
587 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
590 * Fetch the master PE and the PE instance might be
591 * not initialized yet.
593 pe = &phb->ioda.pe_array[pe_no];
594 if (pe->flags & PNV_IODA_PE_SLAVE) {
596 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
597 pe_no = pe->pe_number;
600 /* Check the master PE */
601 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
602 &state, &pcierr, NULL);
603 if (rc != OPAL_SUCCESS) {
604 pr_warn("%s: Failure %lld getting "
605 "PHB#%x-PE#%x state\n",
607 phb->hose->global_number, pe_no);
608 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
611 /* Check the slave PE */
612 if (!(pe->flags & PNV_IODA_PE_MASTER))
615 list_for_each_entry(slave, &pe->slaves, list) {
616 rc = opal_pci_eeh_freeze_status(phb->opal_id,
621 if (rc != OPAL_SUCCESS) {
622 pr_warn("%s: Failure %lld getting "
623 "PHB#%x-PE#%x state\n",
625 phb->hose->global_number, slave->pe_number);
626 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
630 * Override the result based on the ascending
640 /* Currently those 2 are only used when MSIs are enabled, this will change
641 * but in the meantime, we need to protect them to avoid warnings
643 #ifdef CONFIG_PCI_MSI
644 struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
646 struct pci_controller *hose = pci_bus_to_host(dev->bus);
647 struct pnv_phb *phb = hose->private_data;
648 struct pci_dn *pdn = pci_get_pdn(dev);
652 if (pdn->pe_number == IODA_INVALID_PE)
654 return &phb->ioda.pe_array[pdn->pe_number];
656 #endif /* CONFIG_PCI_MSI */
658 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
659 struct pnv_ioda_pe *parent,
660 struct pnv_ioda_pe *child,
663 const char *desc = is_add ? "adding" : "removing";
664 uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
665 OPAL_REMOVE_PE_FROM_DOMAIN;
666 struct pnv_ioda_pe *slave;
669 /* Parent PE affects child PE */
670 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
671 child->pe_number, op);
672 if (rc != OPAL_SUCCESS) {
673 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
678 if (!(child->flags & PNV_IODA_PE_MASTER))
681 /* Compound case: parent PE affects slave PEs */
682 list_for_each_entry(slave, &child->slaves, list) {
683 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
684 slave->pe_number, op);
685 if (rc != OPAL_SUCCESS) {
686 pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
695 static int pnv_ioda_set_peltv(struct pnv_phb *phb,
696 struct pnv_ioda_pe *pe,
699 struct pnv_ioda_pe *slave;
700 struct pci_dev *pdev = NULL;
704 * Clear PE frozen state. If it's master PE, we need
705 * clear slave PE frozen state as well.
708 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
709 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
710 if (pe->flags & PNV_IODA_PE_MASTER) {
711 list_for_each_entry(slave, &pe->slaves, list)
712 opal_pci_eeh_freeze_clear(phb->opal_id,
714 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
719 * Associate PE in PELT. We need add the PE into the
720 * corresponding PELT-V as well. Otherwise, the error
721 * originated from the PE might contribute to other
724 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
728 /* For compound PEs, any one affects all of them */
729 if (pe->flags & PNV_IODA_PE_MASTER) {
730 list_for_each_entry(slave, &pe->slaves, list) {
731 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
737 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
738 pdev = pe->pbus->self;
739 else if (pe->flags & PNV_IODA_PE_DEV)
740 pdev = pe->pdev->bus->self;
741 #ifdef CONFIG_PCI_IOV
742 else if (pe->flags & PNV_IODA_PE_VF)
743 pdev = pe->parent_dev;
744 #endif /* CONFIG_PCI_IOV */
746 struct pci_dn *pdn = pci_get_pdn(pdev);
747 struct pnv_ioda_pe *parent;
749 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
750 parent = &phb->ioda.pe_array[pdn->pe_number];
751 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
756 pdev = pdev->bus->self;
762 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
764 struct pci_dev *parent;
765 uint8_t bcomp, dcomp, fcomp;
769 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
773 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
774 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
775 parent = pe->pbus->self;
776 if (pe->flags & PNV_IODA_PE_BUS_ALL)
777 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
782 case 1: bcomp = OpalPciBusAll; break;
783 case 2: bcomp = OpalPciBus7Bits; break;
784 case 4: bcomp = OpalPciBus6Bits; break;
785 case 8: bcomp = OpalPciBus5Bits; break;
786 case 16: bcomp = OpalPciBus4Bits; break;
787 case 32: bcomp = OpalPciBus3Bits; break;
789 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
791 /* Do an exact match only */
792 bcomp = OpalPciBusAll;
794 rid_end = pe->rid + (count << 8);
796 #ifdef CONFIG_PCI_IOV
797 if (pe->flags & PNV_IODA_PE_VF)
798 parent = pe->parent_dev;
801 parent = pe->pdev->bus->self;
802 bcomp = OpalPciBusAll;
803 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
804 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
805 rid_end = pe->rid + 1;
808 /* Clear the reverse map */
809 for (rid = pe->rid; rid < rid_end; rid++)
810 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE;
812 /* Release from all parents PELT-V */
814 struct pci_dn *pdn = pci_get_pdn(parent);
815 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
816 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
817 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
818 /* XXX What to do in case of error ? */
820 parent = parent->bus->self;
823 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
824 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
826 /* Disassociate PE in PELT */
827 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
828 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
830 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
831 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
832 bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
834 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
838 #ifdef CONFIG_PCI_IOV
839 pe->parent_dev = NULL;
845 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
847 struct pci_dev *parent;
848 uint8_t bcomp, dcomp, fcomp;
849 long rc, rid_end, rid;
851 /* Bus validation ? */
855 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
856 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
857 parent = pe->pbus->self;
858 if (pe->flags & PNV_IODA_PE_BUS_ALL)
859 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
864 case 1: bcomp = OpalPciBusAll; break;
865 case 2: bcomp = OpalPciBus7Bits; break;
866 case 4: bcomp = OpalPciBus6Bits; break;
867 case 8: bcomp = OpalPciBus5Bits; break;
868 case 16: bcomp = OpalPciBus4Bits; break;
869 case 32: bcomp = OpalPciBus3Bits; break;
871 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
873 /* Do an exact match only */
874 bcomp = OpalPciBusAll;
876 rid_end = pe->rid + (count << 8);
878 #ifdef CONFIG_PCI_IOV
879 if (pe->flags & PNV_IODA_PE_VF)
880 parent = pe->parent_dev;
882 #endif /* CONFIG_PCI_IOV */
883 parent = pe->pdev->bus->self;
884 bcomp = OpalPciBusAll;
885 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
886 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
887 rid_end = pe->rid + 1;
891 * Associate PE in PELT. We need add the PE into the
892 * corresponding PELT-V as well. Otherwise, the error
893 * originated from the PE might contribute to other
896 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
897 bcomp, dcomp, fcomp, OPAL_MAP_PE);
899 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
904 * Configure PELTV. NPUs don't have a PELTV table so skip
905 * configuration on them.
907 if (phb->type != PNV_PHB_NPU)
908 pnv_ioda_set_peltv(phb, pe, true);
910 /* Setup reverse map */
911 for (rid = pe->rid; rid < rid_end; rid++)
912 phb->ioda.pe_rmap[rid] = pe->pe_number;
914 /* Setup one MVTs on IODA1 */
915 if (phb->type != PNV_PHB_IODA1) {
920 pe->mve_number = pe->pe_number;
921 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
922 if (rc != OPAL_SUCCESS) {
923 pe_err(pe, "OPAL error %ld setting up MVE %d\n",
927 rc = opal_pci_set_mve_enable(phb->opal_id,
928 pe->mve_number, OPAL_ENABLE_MVE);
930 pe_err(pe, "OPAL error %ld enabling MVE %d\n",
940 #ifdef CONFIG_PCI_IOV
941 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
943 struct pci_dn *pdn = pci_get_pdn(dev);
945 struct resource *res, res2;
946 resource_size_t size;
953 * "offset" is in VFs. The M64 windows are sized so that when they
954 * are segmented, each segment is the same size as the IOV BAR.
955 * Each segment is in a separate PE, and the high order bits of the
956 * address are the PE number. Therefore, each VF's BAR is in a
957 * separate PE, and changing the IOV BAR start address changes the
958 * range of PEs the VFs are in.
960 num_vfs = pdn->num_vfs;
961 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
962 res = &dev->resource[i + PCI_IOV_RESOURCES];
963 if (!res->flags || !res->parent)
967 * The actual IOV BAR range is determined by the start address
968 * and the actual size for num_vfs VFs BAR. This check is to
969 * make sure that after shifting, the range will not overlap
970 * with another device.
972 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
973 res2.flags = res->flags;
974 res2.start = res->start + (size * offset);
975 res2.end = res2.start + (size * num_vfs) - 1;
977 if (res2.end > res->end) {
978 dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
979 i, &res2, res, num_vfs, offset);
985 * After doing so, there would be a "hole" in the /proc/iomem when
986 * offset is a positive value. It looks like the device return some
987 * mmio back to the system, which actually no one could use it.
989 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
990 res = &dev->resource[i + PCI_IOV_RESOURCES];
991 if (!res->flags || !res->parent)
994 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
996 res->start += size * offset;
998 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
999 i, &res2, res, (offset > 0) ? "En" : "Dis",
1001 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
1005 #endif /* CONFIG_PCI_IOV */
1007 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
1009 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1010 struct pnv_phb *phb = hose->private_data;
1011 struct pci_dn *pdn = pci_get_pdn(dev);
1012 struct pnv_ioda_pe *pe;
1015 pr_err("%s: Device tree node not associated properly\n",
1019 if (pdn->pe_number != IODA_INVALID_PE)
1022 pe = pnv_ioda_alloc_pe(phb);
1024 pr_warning("%s: Not enough PE# available, disabling device\n",
1029 /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
1030 * pointer in the PE data structure, both should be destroyed at the
1031 * same time. However, this needs to be looked at more closely again
1032 * once we actually start removing things (Hotplug, SR-IOV, ...)
1034 * At some point we want to remove the PDN completely anyways
1038 pdn->pe_number = pe->pe_number;
1039 pe->flags = PNV_IODA_PE_DEV;
1042 pe->mve_number = -1;
1043 pe->rid = dev->bus->number << 8 | pdn->devfn;
1045 pe_info(pe, "Associated device to PE\n");
1047 if (pnv_ioda_configure_pe(phb, pe)) {
1048 /* XXX What do we do here ? */
1049 pnv_ioda_free_pe(pe);
1050 pdn->pe_number = IODA_INVALID_PE;
1056 /* Put PE to the list */
1057 list_add_tail(&pe->list, &phb->ioda.pe_list);
1062 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
1064 struct pci_dev *dev;
1066 list_for_each_entry(dev, &bus->devices, bus_list) {
1067 struct pci_dn *pdn = pci_get_pdn(dev);
1070 pr_warn("%s: No device node associated with device !\n",
1076 * In partial hotplug case, the PCI device might be still
1077 * associated with the PE and needn't attach it to the PE
1080 if (pdn->pe_number != IODA_INVALID_PE)
1085 pdn->pe_number = pe->pe_number;
1086 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1087 pnv_ioda_setup_same_PE(dev->subordinate, pe);
1092 * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1093 * single PCI bus. Another one that contains the primary PCI bus and its
1094 * subordinate PCI devices and buses. The second type of PE is normally
1095 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1097 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
1099 struct pci_controller *hose = pci_bus_to_host(bus);
1100 struct pnv_phb *phb = hose->private_data;
1101 struct pnv_ioda_pe *pe = NULL;
1102 unsigned int pe_num;
1105 * In partial hotplug case, the PE instance might be still alive.
1106 * We should reuse it instead of allocating a new one.
1108 pe_num = phb->ioda.pe_rmap[bus->number << 8];
1109 if (pe_num != IODA_INVALID_PE) {
1110 pe = &phb->ioda.pe_array[pe_num];
1111 pnv_ioda_setup_same_PE(bus, pe);
1115 /* PE number for root bus should have been reserved */
1116 if (pci_is_root_bus(bus) &&
1117 phb->ioda.root_pe_idx != IODA_INVALID_PE)
1118 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx];
1120 /* Check if PE is determined by M64 */
1121 if (!pe && phb->pick_m64_pe)
1122 pe = phb->pick_m64_pe(bus, all);
1124 /* The PE number isn't pinned by M64 */
1126 pe = pnv_ioda_alloc_pe(phb);
1129 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1130 __func__, pci_domain_nr(bus), bus->number);
1134 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1137 pe->mve_number = -1;
1138 pe->rid = bus->busn_res.start << 8;
1141 pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n",
1142 bus->busn_res.start, bus->busn_res.end, pe->pe_number);
1144 pe_info(pe, "Secondary bus %d associated with PE#%d\n",
1145 bus->busn_res.start, pe->pe_number);
1147 if (pnv_ioda_configure_pe(phb, pe)) {
1148 /* XXX What do we do here ? */
1149 pnv_ioda_free_pe(pe);
1154 /* Associate it with all child devices */
1155 pnv_ioda_setup_same_PE(bus, pe);
1157 /* Put PE to the list */
1158 list_add_tail(&pe->list, &phb->ioda.pe_list);
1163 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
1165 int pe_num, found_pe = false, rc;
1167 struct pnv_ioda_pe *pe;
1168 struct pci_dev *gpu_pdev;
1169 struct pci_dn *npu_pdn;
1170 struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
1171 struct pnv_phb *phb = hose->private_data;
1174 * Due to a hardware errata PE#0 on the NPU is reserved for
1175 * error handling. This means we only have three PEs remaining
1176 * which need to be assigned to four links, implying some
1177 * links must share PEs.
1179 * To achieve this we assign PEs such that NPUs linking the
1180 * same GPU get assigned the same PE.
1182 gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
1183 for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
1184 pe = &phb->ioda.pe_array[pe_num];
1188 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
1190 * This device has the same peer GPU so should
1191 * be assigned the same PE as the existing
1194 dev_info(&npu_pdev->dev,
1195 "Associating to existing PE %d\n", pe_num);
1196 pci_dev_get(npu_pdev);
1197 npu_pdn = pci_get_pdn(npu_pdev);
1198 rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
1199 npu_pdn->pcidev = npu_pdev;
1200 npu_pdn->pe_number = pe_num;
1201 phb->ioda.pe_rmap[rid] = pe->pe_number;
1203 /* Map the PE to this link */
1204 rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
1206 OPAL_COMPARE_RID_DEVICE_NUMBER,
1207 OPAL_COMPARE_RID_FUNCTION_NUMBER,
1209 WARN_ON(rc != OPAL_SUCCESS);
1217 * Could not find an existing PE so allocate a new
1220 return pnv_ioda_setup_dev_PE(npu_pdev);
1225 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
1227 struct pci_dev *pdev;
1229 list_for_each_entry(pdev, &bus->devices, bus_list)
1230 pnv_ioda_setup_npu_PE(pdev);
1233 static void pnv_pci_ioda_setup_PEs(void)
1235 struct pci_controller *hose, *tmp;
1236 struct pnv_phb *phb;
1238 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1239 phb = hose->private_data;
1240 if (phb->type == PNV_PHB_NPU) {
1241 /* PE#0 is needed for error reporting */
1242 pnv_ioda_reserve_pe(phb, 0);
1243 pnv_ioda_setup_npu_PEs(hose->bus);
1248 #ifdef CONFIG_PCI_IOV
1249 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
1251 struct pci_bus *bus;
1252 struct pci_controller *hose;
1253 struct pnv_phb *phb;
1259 hose = pci_bus_to_host(bus);
1260 phb = hose->private_data;
1261 pdn = pci_get_pdn(pdev);
1263 if (pdn->m64_single_mode)
1268 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1269 for (j = 0; j < m64_bars; j++) {
1270 if (pdn->m64_map[j][i] == IODA_INVALID_M64)
1272 opal_pci_phb_mmio_enable(phb->opal_id,
1273 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0);
1274 clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc);
1275 pdn->m64_map[j][i] = IODA_INVALID_M64;
1278 kfree(pdn->m64_map);
1282 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
1284 struct pci_bus *bus;
1285 struct pci_controller *hose;
1286 struct pnv_phb *phb;
1289 struct resource *res;
1293 resource_size_t size, start;
1298 hose = pci_bus_to_host(bus);
1299 phb = hose->private_data;
1300 pdn = pci_get_pdn(pdev);
1301 total_vfs = pci_sriov_get_totalvfs(pdev);
1303 if (pdn->m64_single_mode)
1308 pdn->m64_map = kmalloc(sizeof(*pdn->m64_map) * m64_bars, GFP_KERNEL);
1311 /* Initialize the m64_map to IODA_INVALID_M64 */
1312 for (i = 0; i < m64_bars ; i++)
1313 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++)
1314 pdn->m64_map[i][j] = IODA_INVALID_M64;
1317 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1318 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1319 if (!res->flags || !res->parent)
1322 for (j = 0; j < m64_bars; j++) {
1324 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1325 phb->ioda.m64_bar_idx + 1, 0);
1327 if (win >= phb->ioda.m64_bar_idx + 1)
1329 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1331 pdn->m64_map[j][i] = win;
1333 if (pdn->m64_single_mode) {
1334 size = pci_iov_resource_size(pdev,
1335 PCI_IOV_RESOURCES + i);
1336 start = res->start + size * j;
1338 size = resource_size(res);
1342 /* Map the M64 here */
1343 if (pdn->m64_single_mode) {
1344 pe_num = pdn->pe_num_map[j];
1345 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1346 pe_num, OPAL_M64_WINDOW_TYPE,
1347 pdn->m64_map[j][i], 0);
1350 rc = opal_pci_set_phb_mem_window(phb->opal_id,
1351 OPAL_M64_WINDOW_TYPE,
1358 if (rc != OPAL_SUCCESS) {
1359 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1364 if (pdn->m64_single_mode)
1365 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1366 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2);
1368 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1369 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1);
1371 if (rc != OPAL_SUCCESS) {
1372 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1381 pnv_pci_vf_release_m64(pdev, num_vfs);
1385 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1387 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
1389 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1391 struct iommu_table *tbl;
1394 tbl = pe->table_group.tables[0];
1395 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1397 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
1399 pnv_pci_ioda2_set_bypass(pe, false);
1400 if (pe->table_group.group) {
1401 iommu_group_put(pe->table_group.group);
1402 BUG_ON(pe->table_group.group);
1404 pnv_pci_ioda2_table_free_pages(tbl);
1405 iommu_free_table(tbl, of_node_full_name(dev->dev.of_node));
1408 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
1410 struct pci_bus *bus;
1411 struct pci_controller *hose;
1412 struct pnv_phb *phb;
1413 struct pnv_ioda_pe *pe, *pe_n;
1417 hose = pci_bus_to_host(bus);
1418 phb = hose->private_data;
1419 pdn = pci_get_pdn(pdev);
1421 if (!pdev->is_physfn)
1424 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1425 if (pe->parent_dev != pdev)
1428 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1430 /* Remove from list */
1431 mutex_lock(&phb->ioda.pe_list_mutex);
1432 list_del(&pe->list);
1433 mutex_unlock(&phb->ioda.pe_list_mutex);
1435 pnv_ioda_deconfigure_pe(phb, pe);
1437 pnv_ioda_free_pe(pe);
1441 void pnv_pci_sriov_disable(struct pci_dev *pdev)
1443 struct pci_bus *bus;
1444 struct pci_controller *hose;
1445 struct pnv_phb *phb;
1446 struct pnv_ioda_pe *pe;
1448 struct pci_sriov *iov;
1452 hose = pci_bus_to_host(bus);
1453 phb = hose->private_data;
1454 pdn = pci_get_pdn(pdev);
1456 num_vfs = pdn->num_vfs;
1458 /* Release VF PEs */
1459 pnv_ioda_release_vf_PE(pdev);
1461 if (phb->type == PNV_PHB_IODA2) {
1462 if (!pdn->m64_single_mode)
1463 pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map);
1465 /* Release M64 windows */
1466 pnv_pci_vf_release_m64(pdev, num_vfs);
1468 /* Release PE numbers */
1469 if (pdn->m64_single_mode) {
1470 for (i = 0; i < num_vfs; i++) {
1471 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1474 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1475 pnv_ioda_free_pe(pe);
1478 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1479 /* Releasing pe_num_map */
1480 kfree(pdn->pe_num_map);
1484 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1485 struct pnv_ioda_pe *pe);
1486 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1488 struct pci_bus *bus;
1489 struct pci_controller *hose;
1490 struct pnv_phb *phb;
1491 struct pnv_ioda_pe *pe;
1497 hose = pci_bus_to_host(bus);
1498 phb = hose->private_data;
1499 pdn = pci_get_pdn(pdev);
1501 if (!pdev->is_physfn)
1504 /* Reserve PE for each VF */
1505 for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1506 if (pdn->m64_single_mode)
1507 pe_num = pdn->pe_num_map[vf_index];
1509 pe_num = *pdn->pe_num_map + vf_index;
1511 pe = &phb->ioda.pe_array[pe_num];
1512 pe->pe_number = pe_num;
1514 pe->flags = PNV_IODA_PE_VF;
1516 pe->parent_dev = pdev;
1517 pe->mve_number = -1;
1518 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) |
1519 pci_iov_virtfn_devfn(pdev, vf_index);
1521 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n",
1522 hose->global_number, pdev->bus->number,
1523 PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
1524 PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num);
1526 if (pnv_ioda_configure_pe(phb, pe)) {
1527 /* XXX What do we do here ? */
1528 pnv_ioda_free_pe(pe);
1533 /* Put PE to the list */
1534 mutex_lock(&phb->ioda.pe_list_mutex);
1535 list_add_tail(&pe->list, &phb->ioda.pe_list);
1536 mutex_unlock(&phb->ioda.pe_list_mutex);
1538 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1542 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1544 struct pci_bus *bus;
1545 struct pci_controller *hose;
1546 struct pnv_phb *phb;
1547 struct pnv_ioda_pe *pe;
1553 hose = pci_bus_to_host(bus);
1554 phb = hose->private_data;
1555 pdn = pci_get_pdn(pdev);
1557 if (phb->type == PNV_PHB_IODA2) {
1558 if (!pdn->vfs_expanded) {
1559 dev_info(&pdev->dev, "don't support this SRIOV device"
1560 " with non 64bit-prefetchable IOV BAR\n");
1565 * When M64 BARs functions in Single PE mode, the number of VFs
1566 * could be enabled must be less than the number of M64 BARs.
1568 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) {
1569 dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n");
1573 /* Allocating pe_num_map */
1574 if (pdn->m64_single_mode)
1575 pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map) * num_vfs,
1578 pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL);
1580 if (!pdn->pe_num_map)
1583 if (pdn->m64_single_mode)
1584 for (i = 0; i < num_vfs; i++)
1585 pdn->pe_num_map[i] = IODA_INVALID_PE;
1587 /* Calculate available PE for required VFs */
1588 if (pdn->m64_single_mode) {
1589 for (i = 0; i < num_vfs; i++) {
1590 pe = pnv_ioda_alloc_pe(phb);
1596 pdn->pe_num_map[i] = pe->pe_number;
1599 mutex_lock(&phb->ioda.pe_alloc_mutex);
1600 *pdn->pe_num_map = bitmap_find_next_zero_area(
1601 phb->ioda.pe_alloc, phb->ioda.total_pe_num,
1603 if (*pdn->pe_num_map >= phb->ioda.total_pe_num) {
1604 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1605 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1606 kfree(pdn->pe_num_map);
1609 bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1610 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1612 pdn->num_vfs = num_vfs;
1614 /* Assign M64 window accordingly */
1615 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
1617 dev_info(&pdev->dev, "Not enough M64 window resources\n");
1622 * When using one M64 BAR to map one IOV BAR, we need to shift
1623 * the IOV BAR according to the PE# allocated to the VFs.
1624 * Otherwise, the PE# for the VF will conflict with others.
1626 if (!pdn->m64_single_mode) {
1627 ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map);
1634 pnv_ioda_setup_vf_PE(pdev, num_vfs);
1639 if (pdn->m64_single_mode) {
1640 for (i = 0; i < num_vfs; i++) {
1641 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1644 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1645 pnv_ioda_free_pe(pe);
1648 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1650 /* Releasing pe_num_map */
1651 kfree(pdn->pe_num_map);
1656 int pcibios_sriov_disable(struct pci_dev *pdev)
1658 pnv_pci_sriov_disable(pdev);
1660 /* Release PCI data */
1661 remove_dev_pci_data(pdev);
1665 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1667 /* Allocate PCI data */
1668 add_dev_pci_data(pdev);
1670 return pnv_pci_sriov_enable(pdev, num_vfs);
1672 #endif /* CONFIG_PCI_IOV */
1674 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
1676 struct pci_dn *pdn = pci_get_pdn(pdev);
1677 struct pnv_ioda_pe *pe;
1680 * The function can be called while the PE#
1681 * hasn't been assigned. Do nothing for the
1684 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1687 pe = &phb->ioda.pe_array[pdn->pe_number];
1688 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1689 set_dma_offset(&pdev->dev, pe->tce_bypass_base);
1690 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1692 * Note: iommu_add_device() will fail here as
1693 * for physical PE: the device is already added by now;
1694 * for virtual PE: sysfs entries are not ready yet and
1695 * tce_iommu_bus_notifier will add the device to a group later.
1699 static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
1701 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1702 struct pnv_phb *phb = hose->private_data;
1703 struct pci_dn *pdn = pci_get_pdn(pdev);
1704 struct pnv_ioda_pe *pe;
1706 bool bypass = false;
1708 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1711 pe = &phb->ioda.pe_array[pdn->pe_number];
1712 if (pe->tce_bypass_enabled) {
1713 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1714 bypass = (dma_mask >= top);
1718 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
1719 set_dma_ops(&pdev->dev, &dma_direct_ops);
1721 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1722 set_dma_ops(&pdev->dev, &dma_iommu_ops);
1724 *pdev->dev.dma_mask = dma_mask;
1726 /* Update peer npu devices */
1727 pnv_npu_try_dma_set_bypass(pdev, bypass);
1732 static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev)
1734 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1735 struct pnv_phb *phb = hose->private_data;
1736 struct pci_dn *pdn = pci_get_pdn(pdev);
1737 struct pnv_ioda_pe *pe;
1740 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1743 pe = &phb->ioda.pe_array[pdn->pe_number];
1744 if (!pe->tce_bypass_enabled)
1745 return __dma_get_required_mask(&pdev->dev);
1748 end = pe->tce_bypass_base + memblock_end_of_DRAM();
1749 mask = 1ULL << (fls64(end) - 1);
1755 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
1756 struct pci_bus *bus)
1758 struct pci_dev *dev;
1760 list_for_each_entry(dev, &bus->devices, bus_list) {
1761 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1762 set_dma_offset(&dev->dev, pe->tce_bypass_base);
1763 iommu_add_device(&dev->dev);
1765 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1766 pnv_ioda_setup_bus_dma(pe, dev->subordinate);
1770 static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb,
1773 return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) :
1774 (phb->regs + 0x210);
1777 static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl,
1778 unsigned long index, unsigned long npages, bool rm)
1780 struct iommu_table_group_link *tgl = list_first_entry_or_null(
1781 &tbl->it_group_list, struct iommu_table_group_link,
1783 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1784 struct pnv_ioda_pe, table_group);
1785 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
1786 unsigned long start, end, inc;
1788 start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1789 end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1792 /* p7ioc-style invalidation, 2 TCEs per write */
1793 start |= (1ull << 63);
1794 end |= (1ull << 63);
1796 end |= inc - 1; /* round up end to be different than start */
1798 mb(); /* Ensure above stores are visible */
1799 while (start <= end) {
1801 __raw_rm_writeq(cpu_to_be64(start), invalidate);
1803 __raw_writeq(cpu_to_be64(start), invalidate);
1808 * The iommu layer will do another mb() for us on build()
1809 * and we don't care on free()
1813 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1814 long npages, unsigned long uaddr,
1815 enum dma_data_direction direction,
1816 unsigned long attrs)
1818 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1822 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1827 #ifdef CONFIG_IOMMU_API
1828 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
1829 unsigned long *hpa, enum dma_data_direction *direction)
1831 long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1834 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false);
1840 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
1843 pnv_tce_free(tbl, index, npages);
1845 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1848 static struct iommu_table_ops pnv_ioda1_iommu_ops = {
1849 .set = pnv_ioda1_tce_build,
1850 #ifdef CONFIG_IOMMU_API
1851 .exchange = pnv_ioda1_tce_xchg,
1853 .clear = pnv_ioda1_tce_free,
1857 #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0)
1858 #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1)
1859 #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2)
1861 void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
1863 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm);
1864 const unsigned long val = PHB3_TCE_KILL_INVAL_ALL;
1866 mb(); /* Ensure previous TCE table stores are visible */
1868 __raw_rm_writeq(cpu_to_be64(val), invalidate);
1870 __raw_writeq(cpu_to_be64(val), invalidate);
1873 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)
1875 /* 01xb - invalidate TCEs that match the specified PE# */
1876 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false);
1877 unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
1879 mb(); /* Ensure above stores are visible */
1880 __raw_writeq(cpu_to_be64(val), invalidate);
1883 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm,
1884 unsigned shift, unsigned long index,
1885 unsigned long npages)
1887 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
1888 unsigned long start, end, inc;
1890 /* We'll invalidate DMA address in PE scope */
1891 start = PHB3_TCE_KILL_INVAL_ONE;
1892 start |= (pe->pe_number & 0xFF);
1895 /* Figure out the start, end and step */
1896 start |= (index << shift);
1897 end |= ((index + npages - 1) << shift);
1898 inc = (0x1ull << shift);
1901 while (start <= end) {
1903 __raw_rm_writeq(cpu_to_be64(start), invalidate);
1905 __raw_writeq(cpu_to_be64(start), invalidate);
1910 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
1912 struct pnv_phb *phb = pe->phb;
1914 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
1915 pnv_pci_phb3_tce_invalidate_pe(pe);
1917 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE,
1918 pe->pe_number, 0, 0, 0);
1921 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
1922 unsigned long index, unsigned long npages, bool rm)
1924 struct iommu_table_group_link *tgl;
1926 list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) {
1927 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1928 struct pnv_ioda_pe, table_group);
1929 struct pnv_phb *phb = pe->phb;
1930 unsigned int shift = tbl->it_page_shift;
1932 if (phb->type == PNV_PHB_NPU) {
1934 * The NVLink hardware does not support TCE kill
1935 * per TCE entry so we have to invalidate
1936 * the entire cache for it.
1938 pnv_pci_phb3_tce_invalidate_entire(phb, rm);
1941 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
1942 pnv_pci_phb3_tce_invalidate(pe, rm, shift,
1945 opal_rm_pci_tce_kill(phb->opal_id,
1946 OPAL_PCI_TCE_KILL_PAGES,
1947 pe->pe_number, 1u << shift,
1948 index << shift, npages);
1950 opal_pci_tce_kill(phb->opal_id,
1951 OPAL_PCI_TCE_KILL_PAGES,
1952 pe->pe_number, 1u << shift,
1953 index << shift, npages);
1957 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
1958 long npages, unsigned long uaddr,
1959 enum dma_data_direction direction,
1960 unsigned long attrs)
1962 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1966 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1971 #ifdef CONFIG_IOMMU_API
1972 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
1973 unsigned long *hpa, enum dma_data_direction *direction)
1975 long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1978 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);
1984 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
1987 pnv_tce_free(tbl, index, npages);
1989 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1992 static void pnv_ioda2_table_free(struct iommu_table *tbl)
1994 pnv_pci_ioda2_table_free_pages(tbl);
1995 iommu_free_table(tbl, "pnv");
1998 static struct iommu_table_ops pnv_ioda2_iommu_ops = {
1999 .set = pnv_ioda2_tce_build,
2000 #ifdef CONFIG_IOMMU_API
2001 .exchange = pnv_ioda2_tce_xchg,
2003 .clear = pnv_ioda2_tce_free,
2005 .free = pnv_ioda2_table_free,
2008 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data)
2010 unsigned int *weight = (unsigned int *)data;
2012 /* This is quite simplistic. The "base" weight of a device
2013 * is 10. 0 means no DMA is to be accounted for it.
2015 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
2018 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
2019 dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
2020 dev->class == PCI_CLASS_SERIAL_USB_EHCI)
2022 else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
2030 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe)
2032 unsigned int weight = 0;
2034 /* SRIOV VF has same DMA32 weight as its PF */
2035 #ifdef CONFIG_PCI_IOV
2036 if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) {
2037 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight);
2042 if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) {
2043 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight);
2044 } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) {
2045 struct pci_dev *pdev;
2047 list_for_each_entry(pdev, &pe->pbus->devices, bus_list)
2048 pnv_pci_ioda_dev_dma_weight(pdev, &weight);
2049 } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) {
2050 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight);
2056 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
2057 struct pnv_ioda_pe *pe)
2060 struct page *tce_mem = NULL;
2061 struct iommu_table *tbl;
2062 unsigned int weight, total_weight = 0;
2063 unsigned int tce32_segsz, base, segs, avail, i;
2067 /* XXX FIXME: Handle 64-bit only DMA devices */
2068 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
2069 /* XXX FIXME: Allocate multi-level tables on PHB3 */
2070 weight = pnv_pci_ioda_pe_dma_weight(pe);
2074 pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight,
2076 segs = (weight * phb->ioda.dma32_count) / total_weight;
2081 * Allocate contiguous DMA32 segments. We begin with the expected
2082 * number of segments. With one more attempt, the number of DMA32
2083 * segments to be allocated is decreased by one until one segment
2084 * is allocated successfully.
2087 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) {
2088 for (avail = 0, i = base; i < base + segs; i++) {
2089 if (phb->ioda.dma32_segmap[i] ==
2100 pe_warn(pe, "No available DMA32 segments\n");
2105 tbl = pnv_pci_table_alloc(phb->hose->node);
2106 iommu_register_group(&pe->table_group, phb->hose->global_number,
2108 pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
2110 /* Grab a 32-bit TCE table */
2111 pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
2112 weight, total_weight, base, segs);
2113 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
2114 base * PNV_IODA1_DMA32_SEGSIZE,
2115 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1);
2117 /* XXX Currently, we allocate one big contiguous table for the
2118 * TCEs. We only really need one chunk per 256M of TCE space
2119 * (ie per segment) but that's an optimization for later, it
2120 * requires some added smarts with our get/put_tce implementation
2122 * Each TCE page is 4KB in size and each TCE entry occupies 8
2125 tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3);
2126 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
2127 get_order(tce32_segsz * segs));
2129 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
2132 addr = page_address(tce_mem);
2133 memset(addr, 0, tce32_segsz * segs);
2136 for (i = 0; i < segs; i++) {
2137 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2140 __pa(addr) + tce32_segsz * i,
2141 tce32_segsz, IOMMU_PAGE_SIZE_4K);
2143 pe_err(pe, " Failed to configure 32-bit TCE table,"
2149 /* Setup DMA32 segment mapping */
2150 for (i = base; i < base + segs; i++)
2151 phb->ioda.dma32_segmap[i] = pe->pe_number;
2153 /* Setup linux iommu table */
2154 pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs,
2155 base * PNV_IODA1_DMA32_SEGSIZE,
2156 IOMMU_PAGE_SHIFT_4K);
2158 tbl->it_ops = &pnv_ioda1_iommu_ops;
2159 pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
2160 pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
2161 iommu_init_table(tbl, phb->hose->node);
2163 if (pe->flags & PNV_IODA_PE_DEV) {
2165 * Setting table base here only for carrying iommu_group
2166 * further down to let iommu_add_device() do the job.
2167 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2169 set_iommu_table_base(&pe->pdev->dev, tbl);
2170 iommu_add_device(&pe->pdev->dev);
2171 } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2172 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2176 /* XXX Failure: Try to fallback to 64-bit only ? */
2178 __free_pages(tce_mem, get_order(tce32_segsz * segs));
2180 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
2181 iommu_free_table(tbl, "pnv");
2185 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
2186 int num, struct iommu_table *tbl)
2188 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2190 struct pnv_phb *phb = pe->phb;
2192 const unsigned long size = tbl->it_indirect_levels ?
2193 tbl->it_level_size : tbl->it_size;
2194 const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
2195 const __u64 win_size = tbl->it_size << tbl->it_page_shift;
2197 pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num,
2198 start_addr, start_addr + win_size - 1,
2199 IOMMU_PAGE_SIZE(tbl));
2202 * Map TCE table through TVT. The TVE index is the PE number
2203 * shifted by 1 bit for 32-bits DMA space.
2205 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2207 (pe->pe_number << 1) + num,
2208 tbl->it_indirect_levels + 1,
2211 IOMMU_PAGE_SIZE(tbl));
2213 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc);
2217 pnv_pci_link_table_and_group(phb->hose->node, num,
2218 tbl, &pe->table_group);
2219 pnv_pci_phb3_tce_invalidate_pe(pe);
2224 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
2226 uint16_t window_id = (pe->pe_number << 1 ) + 1;
2229 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2231 phys_addr_t top = memblock_end_of_DRAM();
2233 top = roundup_pow_of_two(top);
2234 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2237 pe->tce_bypass_base,
2240 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2243 pe->tce_bypass_base,
2247 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2249 pe->tce_bypass_enabled = enable;
2252 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2253 __u32 page_shift, __u64 window_size, __u32 levels,
2254 struct iommu_table *tbl);
2256 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2257 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2258 struct iommu_table **ptbl)
2260 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2262 int nid = pe->phb->hose->node;
2263 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2265 struct iommu_table *tbl;
2267 tbl = pnv_pci_table_alloc(nid);
2271 ret = pnv_pci_ioda2_table_alloc_pages(nid,
2272 bus_offset, page_shift, window_size,
2275 iommu_free_table(tbl, "pnv");
2279 tbl->it_ops = &pnv_ioda2_iommu_ops;
2286 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2288 struct iommu_table *tbl = NULL;
2292 * crashkernel= specifies the kdump kernel's maximum memory at
2293 * some offset and there is no guaranteed the result is a power
2294 * of 2, which will cause errors later.
2296 const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
2299 * In memory constrained environments, e.g. kdump kernel, the
2300 * DMA window can be larger than available memory, which will
2301 * cause errors later.
2303 const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory);
2305 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0,
2306 IOMMU_PAGE_SHIFT_4K,
2308 POWERNV_IOMMU_DEFAULT_LEVELS, &tbl);
2310 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2315 iommu_init_table(tbl, pe->phb->hose->node);
2317 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2319 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2321 pnv_ioda2_table_free(tbl);
2325 if (!pnv_iommu_bypass_disabled)
2326 pnv_pci_ioda2_set_bypass(pe, true);
2329 * Setting table base here only for carrying iommu_group
2330 * further down to let iommu_add_device() do the job.
2331 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2333 if (pe->flags & PNV_IODA_PE_DEV)
2334 set_iommu_table_base(&pe->pdev->dev, tbl);
2339 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2340 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2343 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2345 struct pnv_phb *phb = pe->phb;
2348 pe_info(pe, "Removing DMA window #%d\n", num);
2350 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2351 (pe->pe_number << 1) + num,
2352 0/* levels */, 0/* table address */,
2353 0/* table size */, 0/* page size */);
2355 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2357 pnv_pci_phb3_tce_invalidate_pe(pe);
2359 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2365 #ifdef CONFIG_IOMMU_API
2366 static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2367 __u64 window_size, __u32 levels)
2369 unsigned long bytes = 0;
2370 const unsigned window_shift = ilog2(window_size);
2371 unsigned entries_shift = window_shift - page_shift;
2372 unsigned table_shift = entries_shift + 3;
2373 unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2374 unsigned long direct_table_size;
2376 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2377 (window_size > memory_hotplug_max()) ||
2378 !is_power_of_2(window_size))
2381 /* Calculate a direct table size from window_size and levels */
2382 entries_shift = (entries_shift + levels - 1) / levels;
2383 table_shift = entries_shift + 3;
2384 table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2385 direct_table_size = 1UL << table_shift;
2387 for ( ; levels; --levels) {
2388 bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2390 tce_table_size /= direct_table_size;
2391 tce_table_size <<= 3;
2392 tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size);
2398 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
2400 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2402 /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2403 struct iommu_table *tbl = pe->table_group.tables[0];
2405 pnv_pci_ioda2_set_bypass(pe, false);
2406 pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2407 pnv_ioda2_table_free(tbl);
2410 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2412 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2415 pnv_pci_ioda2_setup_default_config(pe);
2418 static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
2419 .get_table_size = pnv_pci_ioda2_get_table_size,
2420 .create_table = pnv_pci_ioda2_create_table,
2421 .set_window = pnv_pci_ioda2_set_window,
2422 .unset_window = pnv_pci_ioda2_unset_window,
2423 .take_ownership = pnv_ioda2_take_ownership,
2424 .release_ownership = pnv_ioda2_release_ownership,
2427 static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque)
2429 struct pci_controller *hose;
2430 struct pnv_phb *phb;
2431 struct pnv_ioda_pe **ptmppe = opaque;
2432 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
2433 struct pci_dn *pdn = pci_get_pdn(pdev);
2435 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
2438 hose = pci_bus_to_host(pdev->bus);
2439 phb = hose->private_data;
2440 if (phb->type != PNV_PHB_NPU)
2443 *ptmppe = &phb->ioda.pe_array[pdn->pe_number];
2449 * This returns PE of associated NPU.
2450 * This assumes that NPU is in the same IOMMU group with GPU and there is
2453 static struct pnv_ioda_pe *gpe_table_group_to_npe(
2454 struct iommu_table_group *table_group)
2456 struct pnv_ioda_pe *npe = NULL;
2457 int ret = iommu_group_for_each_dev(table_group->group, &npe,
2458 gpe_table_group_to_npe_cb);
2460 BUG_ON(!ret || !npe);
2465 static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group,
2466 int num, struct iommu_table *tbl)
2468 long ret = pnv_pci_ioda2_set_window(table_group, num, tbl);
2473 ret = pnv_npu_set_window(gpe_table_group_to_npe(table_group), num, tbl);
2475 pnv_pci_ioda2_unset_window(table_group, num);
2480 static long pnv_pci_ioda2_npu_unset_window(
2481 struct iommu_table_group *table_group,
2484 long ret = pnv_pci_ioda2_unset_window(table_group, num);
2489 return pnv_npu_unset_window(gpe_table_group_to_npe(table_group), num);
2492 static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group)
2495 * Detach NPU first as pnv_ioda2_take_ownership() will destroy
2496 * the iommu_table if 32bit DMA is enabled.
2498 pnv_npu_take_ownership(gpe_table_group_to_npe(table_group));
2499 pnv_ioda2_take_ownership(table_group);
2502 static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = {
2503 .get_table_size = pnv_pci_ioda2_get_table_size,
2504 .create_table = pnv_pci_ioda2_create_table,
2505 .set_window = pnv_pci_ioda2_npu_set_window,
2506 .unset_window = pnv_pci_ioda2_npu_unset_window,
2507 .take_ownership = pnv_ioda2_npu_take_ownership,
2508 .release_ownership = pnv_ioda2_release_ownership,
2511 static void pnv_pci_ioda_setup_iommu_api(void)
2513 struct pci_controller *hose, *tmp;
2514 struct pnv_phb *phb;
2515 struct pnv_ioda_pe *pe, *gpe;
2518 * Now we have all PHBs discovered, time to add NPU devices to
2519 * the corresponding IOMMU groups.
2521 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2522 phb = hose->private_data;
2524 if (phb->type != PNV_PHB_NPU)
2527 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2528 gpe = pnv_pci_npu_setup_iommu(pe);
2530 gpe->table_group.ops = &pnv_pci_ioda2_npu_ops;
2534 #else /* !CONFIG_IOMMU_API */
2535 static void pnv_pci_ioda_setup_iommu_api(void) { };
2538 static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift,
2539 unsigned levels, unsigned long limit,
2540 unsigned long *current_offset, unsigned long *total_allocated)
2542 struct page *tce_mem = NULL;
2544 unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT;
2545 unsigned long allocated = 1UL << (order + PAGE_SHIFT);
2546 unsigned entries = 1UL << (shift - 3);
2549 tce_mem = alloc_pages_node(nid, GFP_KERNEL, order);
2551 pr_err("Failed to allocate a TCE memory, order=%d\n", order);
2554 addr = page_address(tce_mem);
2555 memset(addr, 0, allocated);
2556 *total_allocated += allocated;
2560 *current_offset += allocated;
2564 for (i = 0; i < entries; ++i) {
2565 tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift,
2566 levels, limit, current_offset, total_allocated);
2570 addr[i] = cpu_to_be64(__pa(tmp) |
2571 TCE_PCI_READ | TCE_PCI_WRITE);
2573 if (*current_offset >= limit)
2580 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2581 unsigned long size, unsigned level);
2583 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2584 __u32 page_shift, __u64 window_size, __u32 levels,
2585 struct iommu_table *tbl)
2588 unsigned long offset = 0, level_shift, total_allocated = 0;
2589 const unsigned window_shift = ilog2(window_size);
2590 unsigned entries_shift = window_shift - page_shift;
2591 unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT);
2592 const unsigned long tce_table_size = 1UL << table_shift;
2594 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS))
2597 if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size))
2600 /* Adjust direct table size from window_size and levels */
2601 entries_shift = (entries_shift + levels - 1) / levels;
2602 level_shift = entries_shift + 3;
2603 level_shift = max_t(unsigned, level_shift, PAGE_SHIFT);
2605 /* Allocate TCE table */
2606 addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift,
2607 levels, tce_table_size, &offset, &total_allocated);
2609 /* addr==NULL means that the first level allocation failed */
2614 * First level was allocated but some lower level failed as
2615 * we did not allocate as much as we wanted,
2616 * release partially allocated table.
2618 if (offset < tce_table_size) {
2619 pnv_pci_ioda2_table_do_free_pages(addr,
2620 1ULL << (level_shift - 3), levels - 1);
2624 /* Setup linux iommu table */
2625 pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset,
2627 tbl->it_level_size = 1ULL << (level_shift - 3);
2628 tbl->it_indirect_levels = levels - 1;
2629 tbl->it_allocated_size = total_allocated;
2631 pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n",
2632 window_size, tce_table_size, bus_offset);
2637 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2638 unsigned long size, unsigned level)
2640 const unsigned long addr_ul = (unsigned long) addr &
2641 ~(TCE_PCI_READ | TCE_PCI_WRITE);
2645 u64 *tmp = (u64 *) addr_ul;
2647 for (i = 0; i < size; ++i) {
2648 unsigned long hpa = be64_to_cpu(tmp[i]);
2650 if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE)))
2653 pnv_pci_ioda2_table_do_free_pages(__va(hpa), size,
2658 free_pages(addr_ul, get_order(size << 3));
2661 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl)
2663 const unsigned long size = tbl->it_indirect_levels ?
2664 tbl->it_level_size : tbl->it_size;
2669 pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size,
2670 tbl->it_indirect_levels);
2673 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2674 struct pnv_ioda_pe *pe)
2678 if (!pnv_pci_ioda_pe_dma_weight(pe))
2681 /* TVE #1 is selected by PCI address bit 59 */
2682 pe->tce_bypass_base = 1ull << 59;
2684 iommu_register_group(&pe->table_group, phb->hose->global_number,
2687 /* The PE will reserve all possible 32-bits space */
2688 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
2689 phb->ioda.m32_pci_base);
2691 /* Setup linux iommu table */
2692 pe->table_group.tce32_start = 0;
2693 pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2694 pe->table_group.max_dynamic_windows_supported =
2695 IOMMU_TABLE_GROUP_MAX_TABLES;
2696 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2697 pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M;
2698 #ifdef CONFIG_IOMMU_API
2699 pe->table_group.ops = &pnv_pci_ioda2_ops;
2702 rc = pnv_pci_ioda2_setup_default_config(pe);
2706 if (pe->flags & PNV_IODA_PE_DEV)
2707 iommu_add_device(&pe->pdev->dev);
2708 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2709 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2712 #ifdef CONFIG_PCI_MSI
2713 static void pnv_ioda2_msi_eoi(struct irq_data *d)
2715 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2716 struct irq_chip *chip = irq_data_get_irq_chip(d);
2717 struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2721 rc = opal_pci_msi_eoi(phb->opal_id, hw_irq);
2728 void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2730 struct irq_data *idata;
2731 struct irq_chip *ichip;
2733 /* The MSI EOI OPAL call is only needed on PHB3 */
2734 if (phb->model != PNV_PHB_MODEL_PHB3)
2737 if (!phb->ioda.irq_chip_init) {
2739 * First time we setup an MSI IRQ, we need to setup the
2740 * corresponding IRQ chip to route correctly.
2742 idata = irq_get_irq_data(virq);
2743 ichip = irq_data_get_irq_chip(idata);
2744 phb->ioda.irq_chip_init = 1;
2745 phb->ioda.irq_chip = *ichip;
2746 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2748 irq_set_chip(virq, &phb->ioda.irq_chip);
2751 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2752 unsigned int hwirq, unsigned int virq,
2753 unsigned int is_64, struct msi_msg *msg)
2755 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2756 unsigned int xive_num = hwirq - phb->msi_base;
2760 /* No PE assigned ? bail out ... no MSI for you ! */
2764 /* Check if we have an MVE */
2765 if (pe->mve_number < 0)
2768 /* Force 32-bit MSI on some broken devices */
2769 if (dev->no_64bit_msi)
2772 /* Assign XIVE to PE */
2773 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2775 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2776 pci_name(dev), rc, xive_num);
2783 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2786 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2790 msg->address_hi = be64_to_cpu(addr64) >> 32;
2791 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
2795 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2798 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2802 msg->address_hi = 0;
2803 msg->address_lo = be32_to_cpu(addr32);
2805 msg->data = be32_to_cpu(data);
2807 pnv_set_msi_irq_chip(phb, virq);
2809 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2810 " address=%x_%08x data=%x PE# %d\n",
2811 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2812 msg->address_hi, msg->address_lo, data, pe->pe_number);
2817 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2820 const __be32 *prop = of_get_property(phb->hose->dn,
2821 "ibm,opal-msi-ranges", NULL);
2824 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2829 phb->msi_base = be32_to_cpup(prop);
2830 count = be32_to_cpup(prop + 1);
2831 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
2832 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2833 phb->hose->global_number);
2837 phb->msi_setup = pnv_pci_ioda_msi_setup;
2838 phb->msi32_support = 1;
2839 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2840 count, phb->msi_base);
2843 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
2844 #endif /* CONFIG_PCI_MSI */
2846 #ifdef CONFIG_PCI_IOV
2847 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
2849 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
2850 struct pnv_phb *phb = hose->private_data;
2851 const resource_size_t gate = phb->ioda.m64_segsize >> 2;
2852 struct resource *res;
2854 resource_size_t size, total_vf_bar_sz;
2858 if (!pdev->is_physfn || pdev->is_added)
2861 pdn = pci_get_pdn(pdev);
2862 pdn->vfs_expanded = 0;
2863 pdn->m64_single_mode = false;
2865 total_vfs = pci_sriov_get_totalvfs(pdev);
2866 mul = phb->ioda.total_pe_num;
2867 total_vf_bar_sz = 0;
2869 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2870 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2871 if (!res->flags || res->parent)
2873 if (!pnv_pci_is_m64(phb, res)) {
2874 dev_warn(&pdev->dev, "Don't support SR-IOV with"
2875 " non M64 VF BAR%d: %pR. \n",
2880 total_vf_bar_sz += pci_iov_resource_size(pdev,
2881 i + PCI_IOV_RESOURCES);
2884 * If bigger than quarter of M64 segment size, just round up
2887 * Generally, one M64 BAR maps one IOV BAR. To avoid conflict
2888 * with other devices, IOV BAR size is expanded to be
2889 * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64
2890 * segment size , the expanded size would equal to half of the
2891 * whole M64 space size, which will exhaust the M64 Space and
2892 * limit the system flexibility. This is a design decision to
2893 * set the boundary to quarter of the M64 segment size.
2895 if (total_vf_bar_sz > gate) {
2896 mul = roundup_pow_of_two(total_vfs);
2897 dev_info(&pdev->dev,
2898 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n",
2899 total_vf_bar_sz, gate, mul);
2900 pdn->m64_single_mode = true;
2905 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2906 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2907 if (!res->flags || res->parent)
2910 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
2912 * On PHB3, the minimum size alignment of M64 BAR in single
2915 if (pdn->m64_single_mode && (size < SZ_32M))
2917 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
2918 res->end = res->start + size * mul - 1;
2919 dev_dbg(&pdev->dev, " %pR\n", res);
2920 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
2923 pdn->vfs_expanded = mul;
2928 /* To save MMIO space, IOV BAR is truncated. */
2929 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2930 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2932 res->end = res->start - 1;
2935 #endif /* CONFIG_PCI_IOV */
2937 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
2938 struct resource *res)
2940 struct pnv_phb *phb = pe->phb;
2941 struct pci_bus_region region;
2945 if (!res || !res->flags || res->start > res->end)
2948 if (res->flags & IORESOURCE_IO) {
2949 region.start = res->start - phb->ioda.io_pci_base;
2950 region.end = res->end - phb->ioda.io_pci_base;
2951 index = region.start / phb->ioda.io_segsize;
2953 while (index < phb->ioda.total_pe_num &&
2954 region.start <= region.end) {
2955 phb->ioda.io_segmap[index] = pe->pe_number;
2956 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2957 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
2958 if (rc != OPAL_SUCCESS) {
2959 pr_err("%s: Error %lld mapping IO segment#%d to PE#%d\n",
2960 __func__, rc, index, pe->pe_number);
2964 region.start += phb->ioda.io_segsize;
2967 } else if ((res->flags & IORESOURCE_MEM) &&
2968 !pnv_pci_is_m64(phb, res)) {
2969 region.start = res->start -
2970 phb->hose->mem_offset[0] -
2971 phb->ioda.m32_pci_base;
2972 region.end = res->end -
2973 phb->hose->mem_offset[0] -
2974 phb->ioda.m32_pci_base;
2975 index = region.start / phb->ioda.m32_segsize;
2977 while (index < phb->ioda.total_pe_num &&
2978 region.start <= region.end) {
2979 phb->ioda.m32_segmap[index] = pe->pe_number;
2980 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2981 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
2982 if (rc != OPAL_SUCCESS) {
2983 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%d",
2984 __func__, rc, index, pe->pe_number);
2988 region.start += phb->ioda.m32_segsize;
2995 * This function is supposed to be called on basis of PE from top
2996 * to bottom style. So the the I/O or MMIO segment assigned to
2997 * parent PE could be overrided by its child PEs if necessary.
2999 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
3001 struct pci_dev *pdev;
3005 * NOTE: We only care PCI bus based PE for now. For PCI
3006 * device based PE, for example SRIOV sensitive VF should
3007 * be figured out later.
3009 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
3011 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
3012 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
3013 pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);
3016 * If the PE contains all subordinate PCI buses, the
3017 * windows of the child bridges should be mapped to
3020 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
3022 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
3023 pnv_ioda_setup_pe_res(pe,
3024 &pdev->resource[PCI_BRIDGE_RESOURCES + i]);
3028 static void pnv_pci_ioda_create_dbgfs(void)
3030 #ifdef CONFIG_DEBUG_FS
3031 struct pci_controller *hose, *tmp;
3032 struct pnv_phb *phb;
3035 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3036 phb = hose->private_data;
3038 /* Notify initialization of PHB done */
3039 phb->initialized = 1;
3041 sprintf(name, "PCI%04x", hose->global_number);
3042 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
3044 pr_warning("%s: Error on creating debugfs on PHB#%x\n",
3045 __func__, hose->global_number);
3047 #endif /* CONFIG_DEBUG_FS */
3050 static void pnv_pci_ioda_fixup(void)
3052 pnv_pci_ioda_setup_PEs();
3053 pnv_pci_ioda_setup_iommu_api();
3054 pnv_pci_ioda_create_dbgfs();
3058 eeh_addr_cache_build();
3063 * Returns the alignment for I/O or memory windows for P2P
3064 * bridges. That actually depends on how PEs are segmented.
3065 * For now, we return I/O or M32 segment size for PE sensitive
3066 * P2P bridges. Otherwise, the default values (4KiB for I/O,
3067 * 1MiB for memory) will be returned.
3069 * The current PCI bus might be put into one PE, which was
3070 * create against the parent PCI bridge. For that case, we
3071 * needn't enlarge the alignment so that we can save some
3074 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
3077 struct pci_dev *bridge;
3078 struct pci_controller *hose = pci_bus_to_host(bus);
3079 struct pnv_phb *phb = hose->private_data;
3080 int num_pci_bridges = 0;
3084 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
3086 if (num_pci_bridges >= 2)
3090 bridge = bridge->bus->self;
3094 * We fall back to M32 if M64 isn't supported. We enforce the M64
3095 * alignment for any 64-bit resource, PCIe doesn't care and
3096 * bridges only do 64-bit prefetchable anyway.
3098 if (phb->ioda.m64_segsize && (type & IORESOURCE_MEM_64))
3099 return phb->ioda.m64_segsize;
3100 if (type & IORESOURCE_MEM)
3101 return phb->ioda.m32_segsize;
3103 return phb->ioda.io_segsize;
3107 * We are updating root port or the upstream port of the
3108 * bridge behind the root port with PHB's windows in order
3109 * to accommodate the changes on required resources during
3110 * PCI (slot) hotplug, which is connected to either root
3111 * port or the downstream ports of PCIe switch behind the
3114 static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus,
3117 struct pci_controller *hose = pci_bus_to_host(bus);
3118 struct pnv_phb *phb = hose->private_data;
3119 struct pci_dev *bridge = bus->self;
3120 struct resource *r, *w;
3121 bool msi_region = false;
3124 /* Check if we need apply fixup to the bridge's windows */
3125 if (!pci_is_root_bus(bridge->bus) &&
3126 !pci_is_root_bus(bridge->bus->self->bus))
3129 /* Fixup the resources */
3130 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
3131 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i];
3132 if (!r->flags || !r->parent)
3136 if (r->flags & type & IORESOURCE_IO)
3137 w = &hose->io_resource;
3138 else if (pnv_pci_is_m64(phb, r) &&
3139 (type & IORESOURCE_PREFETCH) &&
3140 phb->ioda.m64_segsize)
3141 w = &hose->mem_resources[1];
3142 else if (r->flags & type & IORESOURCE_MEM) {
3143 w = &hose->mem_resources[0];
3147 r->start = w->start;
3150 /* The 64KB 32-bits MSI region shouldn't be included in
3151 * the 32-bits bridge window. Otherwise, we can see strange
3152 * issues. One of them is EEH error observed on Garrison.
3154 * Exclude top 1MB region which is the minimal alignment of
3155 * 32-bits bridge window.
3164 static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type)
3166 struct pci_controller *hose = pci_bus_to_host(bus);
3167 struct pnv_phb *phb = hose->private_data;
3168 struct pci_dev *bridge = bus->self;
3169 struct pnv_ioda_pe *pe;
3170 bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE);
3172 /* Extend bridge's windows if necessary */
3173 pnv_pci_fixup_bridge_resources(bus, type);
3175 /* The PE for root bus should be realized before any one else */
3176 if (!phb->ioda.root_pe_populated) {
3177 pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false);
3179 phb->ioda.root_pe_idx = pe->pe_number;
3180 phb->ioda.root_pe_populated = true;
3184 /* Don't assign PE to PCI bus, which doesn't have subordinate devices */
3185 if (list_empty(&bus->devices))
3188 /* Reserve PEs according to used M64 resources */
3189 if (phb->reserve_m64_pe)
3190 phb->reserve_m64_pe(bus, NULL, all);
3193 * Assign PE. We might run here because of partial hotplug.
3194 * For the case, we just pick up the existing PE and should
3195 * not allocate resources again.
3197 pe = pnv_ioda_setup_bus_PE(bus, all);
3201 pnv_ioda_setup_pe_seg(pe);
3202 switch (phb->type) {
3204 pnv_pci_ioda1_setup_dma_pe(phb, pe);
3207 pnv_pci_ioda2_setup_dma_pe(phb, pe);
3210 pr_warn("%s: No DMA for PHB#%d (type %d)\n",
3211 __func__, phb->hose->global_number, phb->type);
3215 #ifdef CONFIG_PCI_IOV
3216 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
3219 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3220 struct pnv_phb *phb = hose->private_data;
3221 struct pci_dn *pdn = pci_get_pdn(pdev);
3222 resource_size_t align;
3225 * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the
3226 * SR-IOV. While from hardware perspective, the range mapped by M64
3227 * BAR should be size aligned.
3229 * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra
3230 * powernv-specific hardware restriction is gone. But if just use the
3231 * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with
3232 * in one segment of M64 #15, which introduces the PE conflict between
3233 * PF and VF. Based on this, the minimum alignment of an IOV BAR is
3236 * This function returns the total IOV BAR size if M64 BAR is in
3237 * Shared PE mode or just VF BAR size if not.
3238 * If the M64 BAR is in Single PE mode, return the VF BAR size or
3239 * M64 segment size if IOV BAR size is less.
3241 align = pci_iov_resource_size(pdev, resno);
3242 if (!pdn->vfs_expanded)
3244 if (pdn->m64_single_mode)
3245 return max(align, (resource_size_t)phb->ioda.m64_segsize);
3247 return pdn->vfs_expanded * align;
3249 #endif /* CONFIG_PCI_IOV */
3251 /* Prevent enabling devices for which we couldn't properly
3254 bool pnv_pci_enable_device_hook(struct pci_dev *dev)
3256 struct pci_controller *hose = pci_bus_to_host(dev->bus);
3257 struct pnv_phb *phb = hose->private_data;
3260 /* The function is probably called while the PEs have
3261 * not be created yet. For example, resource reassignment
3262 * during PCI probe period. We just skip the check if
3265 if (!phb->initialized)
3268 pdn = pci_get_pdn(dev);
3269 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3275 static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group,
3278 struct pnv_ioda_pe *pe = container_of(table_group,
3279 struct pnv_ioda_pe, table_group);
3280 struct pnv_phb *phb = pe->phb;
3284 pe_info(pe, "Removing DMA window #%d\n", num);
3285 for (idx = 0; idx < phb->ioda.dma32_count; idx++) {
3286 if (phb->ioda.dma32_segmap[idx] != pe->pe_number)
3289 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
3290 idx, 0, 0ul, 0ul, 0ul);
3291 if (rc != OPAL_SUCCESS) {
3292 pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n",
3297 phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE;
3300 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
3301 return OPAL_SUCCESS;
3304 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe)
3306 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3307 struct iommu_table *tbl = pe->table_group.tables[0];
3313 rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0);
3314 if (rc != OPAL_SUCCESS)
3317 pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false);
3318 if (pe->table_group.group) {
3319 iommu_group_put(pe->table_group.group);
3320 WARN_ON(pe->table_group.group);
3323 free_pages(tbl->it_base, get_order(tbl->it_size << 3));
3324 iommu_free_table(tbl, "pnv");
3327 static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)
3329 struct iommu_table *tbl = pe->table_group.tables[0];
3330 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3331 #ifdef CONFIG_IOMMU_API
3338 #ifdef CONFIG_IOMMU_API
3339 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
3341 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
3344 pnv_pci_ioda2_set_bypass(pe, false);
3345 if (pe->table_group.group) {
3346 iommu_group_put(pe->table_group.group);
3347 WARN_ON(pe->table_group.group);
3350 pnv_pci_ioda2_table_free_pages(tbl);
3351 iommu_free_table(tbl, "pnv");
3354 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe,
3358 struct pnv_phb *phb = pe->phb;
3362 for (idx = 0; idx < phb->ioda.total_pe_num; idx++) {
3363 if (map[idx] != pe->pe_number)
3366 if (win == OPAL_M64_WINDOW_TYPE)
3367 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3368 phb->ioda.reserved_pe_idx, win,
3369 idx / PNV_IODA1_M64_SEGS,
3370 idx % PNV_IODA1_M64_SEGS);
3372 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3373 phb->ioda.reserved_pe_idx, win, 0, idx);
3375 if (rc != OPAL_SUCCESS)
3376 pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n",
3379 map[idx] = IODA_INVALID_PE;
3383 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe)
3385 struct pnv_phb *phb = pe->phb;
3387 if (phb->type == PNV_PHB_IODA1) {
3388 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE,
3389 phb->ioda.io_segmap);
3390 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3391 phb->ioda.m32_segmap);
3392 pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE,
3393 phb->ioda.m64_segmap);
3394 } else if (phb->type == PNV_PHB_IODA2) {
3395 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3396 phb->ioda.m32_segmap);
3400 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe)
3402 struct pnv_phb *phb = pe->phb;
3403 struct pnv_ioda_pe *slave, *tmp;
3405 /* Release slave PEs in compound PE */
3406 if (pe->flags & PNV_IODA_PE_MASTER) {
3407 list_for_each_entry_safe(slave, tmp, &pe->slaves, list)
3408 pnv_ioda_release_pe(slave);
3411 list_del(&pe->list);
3412 switch (phb->type) {
3414 pnv_pci_ioda1_release_pe_dma(pe);
3417 pnv_pci_ioda2_release_pe_dma(pe);
3423 pnv_ioda_release_pe_seg(pe);
3424 pnv_ioda_deconfigure_pe(pe->phb, pe);
3425 pnv_ioda_free_pe(pe);
3428 static void pnv_pci_release_device(struct pci_dev *pdev)
3430 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3431 struct pnv_phb *phb = hose->private_data;
3432 struct pci_dn *pdn = pci_get_pdn(pdev);
3433 struct pnv_ioda_pe *pe;
3435 if (pdev->is_virtfn)
3438 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3441 pe = &phb->ioda.pe_array[pdn->pe_number];
3442 WARN_ON(--pe->device_count < 0);
3443 if (pe->device_count == 0)
3444 pnv_ioda_release_pe(pe);
3447 static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
3449 struct pnv_phb *phb = hose->private_data;
3451 opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
3455 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3456 .dma_dev_setup = pnv_pci_dma_dev_setup,
3457 .dma_bus_setup = pnv_pci_dma_bus_setup,
3458 #ifdef CONFIG_PCI_MSI
3459 .setup_msi_irqs = pnv_setup_msi_irqs,
3460 .teardown_msi_irqs = pnv_teardown_msi_irqs,
3462 .enable_device_hook = pnv_pci_enable_device_hook,
3463 .release_device = pnv_pci_release_device,
3464 .window_alignment = pnv_pci_window_alignment,
3465 .setup_bridge = pnv_pci_setup_bridge,
3466 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3467 .dma_set_mask = pnv_pci_ioda_dma_set_mask,
3468 .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask,
3469 .shutdown = pnv_pci_ioda_shutdown,
3472 static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask)
3474 dev_err_once(&npdev->dev,
3475 "%s operation unsupported for NVLink devices\n",
3480 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
3481 .dma_dev_setup = pnv_pci_dma_dev_setup,
3482 #ifdef CONFIG_PCI_MSI
3483 .setup_msi_irqs = pnv_setup_msi_irqs,
3484 .teardown_msi_irqs = pnv_teardown_msi_irqs,
3486 .enable_device_hook = pnv_pci_enable_device_hook,
3487 .window_alignment = pnv_pci_window_alignment,
3488 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3489 .dma_set_mask = pnv_npu_dma_set_mask,
3490 .shutdown = pnv_pci_ioda_shutdown,
3493 #ifdef CONFIG_CXL_BASE
3494 const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops = {
3495 .dma_dev_setup = pnv_pci_dma_dev_setup,
3496 .dma_bus_setup = pnv_pci_dma_bus_setup,
3497 #ifdef CONFIG_PCI_MSI
3498 .setup_msi_irqs = pnv_cxl_cx4_setup_msi_irqs,
3499 .teardown_msi_irqs = pnv_cxl_cx4_teardown_msi_irqs,
3501 .enable_device_hook = pnv_cxl_enable_device_hook,
3502 .disable_device = pnv_cxl_disable_device,
3503 .release_device = pnv_pci_release_device,
3504 .window_alignment = pnv_pci_window_alignment,
3505 .setup_bridge = pnv_pci_setup_bridge,
3506 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3507 .dma_set_mask = pnv_pci_ioda_dma_set_mask,
3508 .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask,
3509 .shutdown = pnv_pci_ioda_shutdown,
3513 static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3514 u64 hub_id, int ioda_type)
3516 struct pci_controller *hose;
3517 struct pnv_phb *phb;
3518 unsigned long size, m64map_off, m32map_off, pemap_off;
3519 unsigned long iomap_off = 0, dma32map_off = 0;
3521 const __be64 *prop64;
3522 const __be32 *prop32;
3529 if (!of_device_is_available(np))
3532 pr_info("Initializing %s PHB (%s)\n",
3533 pnv_phb_names[ioda_type], of_node_full_name(np));
3535 prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3537 pr_err(" Missing \"ibm,opal-phbid\" property !\n");
3540 phb_id = be64_to_cpup(prop64);
3541 pr_debug(" PHB-ID : 0x%016llx\n", phb_id);
3543 phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0);
3545 /* Allocate PCI controller */
3546 phb->hose = hose = pcibios_alloc_controller(np);
3548 pr_err(" Can't allocate PCI controller for %s\n",
3550 memblock_free(__pa(phb), sizeof(struct pnv_phb));
3554 spin_lock_init(&phb->lock);
3555 prop32 = of_get_property(np, "bus-range", &len);
3556 if (prop32 && len == 8) {
3557 hose->first_busno = be32_to_cpu(prop32[0]);
3558 hose->last_busno = be32_to_cpu(prop32[1]);
3560 pr_warn(" Broken <bus-range> on %s\n", np->full_name);
3561 hose->first_busno = 0;
3562 hose->last_busno = 0xff;
3564 hose->private_data = phb;
3565 phb->hub_id = hub_id;
3566 phb->opal_id = phb_id;
3567 phb->type = ioda_type;
3568 mutex_init(&phb->ioda.pe_alloc_mutex);
3570 /* Detect specific models for error handling */
3571 if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3572 phb->model = PNV_PHB_MODEL_P7IOC;
3573 else if (of_device_is_compatible(np, "ibm,power8-pciex"))
3574 phb->model = PNV_PHB_MODEL_PHB3;
3575 else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
3576 phb->model = PNV_PHB_MODEL_NPU;
3578 phb->model = PNV_PHB_MODEL_UNKNOWN;
3580 /* Parse 32-bit and IO ranges (if any) */
3581 pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
3584 if (!of_address_to_resource(np, 0, &r)) {
3585 phb->regs_phys = r.start;
3586 phb->regs = ioremap(r.start, resource_size(&r));
3587 if (phb->regs == NULL)
3588 pr_err(" Failed to map registers !\n");
3591 /* Initialize more IODA stuff */
3592 phb->ioda.total_pe_num = 1;
3593 prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
3595 phb->ioda.total_pe_num = be32_to_cpup(prop32);
3596 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3598 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32);
3600 /* Invalidate RID to PE# mapping */
3601 for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++)
3602 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE;
3604 /* Parse 64-bit MMIO range */
3605 pnv_ioda_parse_m64_window(phb);
3607 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
3608 /* FW Has already off top 64k of M32 space (MSI space) */
3609 phb->ioda.m32_size += 0x10000;
3611 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num;
3612 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
3613 phb->ioda.io_size = hose->pci_io_size;
3614 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num;
3615 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3617 /* Calculate how many 32-bit TCE segments we have */
3618 phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3619 PNV_IODA1_DMA32_SEGSIZE;
3621 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3622 size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8,
3623 sizeof(unsigned long));
3625 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]);
3627 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]);
3628 if (phb->type == PNV_PHB_IODA1) {
3630 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]);
3631 dma32map_off = size;
3632 size += phb->ioda.dma32_count *
3633 sizeof(phb->ioda.dma32_segmap[0]);
3636 size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe);
3637 aux = memblock_virt_alloc(size, 0);
3638 phb->ioda.pe_alloc = aux;
3639 phb->ioda.m64_segmap = aux + m64map_off;
3640 phb->ioda.m32_segmap = aux + m32map_off;
3641 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) {
3642 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE;
3643 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE;
3645 if (phb->type == PNV_PHB_IODA1) {
3646 phb->ioda.io_segmap = aux + iomap_off;
3647 for (segno = 0; segno < phb->ioda.total_pe_num; segno++)
3648 phb->ioda.io_segmap[segno] = IODA_INVALID_PE;
3650 phb->ioda.dma32_segmap = aux + dma32map_off;
3651 for (segno = 0; segno < phb->ioda.dma32_count; segno++)
3652 phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE;
3654 phb->ioda.pe_array = aux + pemap_off;
3657 * Choose PE number for root bus, which shouldn't have
3658 * M64 resources consumed by its child devices. To pick
3659 * the PE number adjacent to the reserved one if possible.
3661 pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx);
3662 if (phb->ioda.reserved_pe_idx == 0) {
3663 phb->ioda.root_pe_idx = 1;
3664 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3665 } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) {
3666 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1;
3667 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3669 phb->ioda.root_pe_idx = IODA_INVALID_PE;
3672 INIT_LIST_HEAD(&phb->ioda.pe_list);
3673 mutex_init(&phb->ioda.pe_list_mutex);
3675 /* Calculate how many 32-bit TCE segments we have */
3676 phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3677 PNV_IODA1_DMA32_SEGSIZE;
3679 #if 0 /* We should really do that ... */
3680 rc = opal_pci_set_phb_mem_window(opal->phb_id,
3683 starting_real_address,
3684 starting_pci_address,
3688 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3689 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx,
3690 phb->ioda.m32_size, phb->ioda.m32_segsize);
3691 if (phb->ioda.m64_size)
3692 pr_info(" M64: 0x%lx [segment=0x%lx]\n",
3693 phb->ioda.m64_size, phb->ioda.m64_segsize);
3694 if (phb->ioda.io_size)
3695 pr_info(" IO: 0x%x [segment=0x%x]\n",
3696 phb->ioda.io_size, phb->ioda.io_segsize);
3699 phb->hose->ops = &pnv_pci_ops;
3700 phb->get_pe_state = pnv_ioda_get_pe_state;
3701 phb->freeze_pe = pnv_ioda_freeze_pe;
3702 phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
3704 /* Setup MSI support */
3705 pnv_pci_init_ioda_msis(phb);
3708 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3709 * to let the PCI core do resource assignment. It's supposed
3710 * that the PCI core will do correct I/O and MMIO alignment
3711 * for the P2P bridge bars so that each PCI bus (excluding
3712 * the child P2P bridges) can form individual PE.
3714 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
3716 if (phb->type == PNV_PHB_NPU) {
3717 hose->controller_ops = pnv_npu_ioda_controller_ops;
3719 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
3720 hose->controller_ops = pnv_pci_ioda_controller_ops;
3723 #ifdef CONFIG_PCI_IOV
3724 ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources;
3725 ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
3728 pci_add_flags(PCI_REASSIGN_ALL_RSRC);
3730 /* Reset IODA tables to a clean state */
3731 rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
3733 pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc);
3735 /* If we're running in kdump kerenl, the previous kerenl never
3736 * shutdown PCI devices correctly. We already got IODA table
3737 * cleaned out. So we have to issue PHB reset to stop all PCI
3738 * transactions from previous kerenl.
3740 if (is_kdump_kernel()) {
3741 pr_info(" Issue PHB reset ...\n");
3742 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
3743 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
3746 /* Remove M64 resource if we can't configure it successfully */
3747 if (!phb->init_m64 || phb->init_m64(phb))
3748 hose->mem_resources[1].flags = 0;
3751 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
3753 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
3756 void __init pnv_pci_init_npu_phb(struct device_node *np)
3758 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU);
3761 void __init pnv_pci_init_ioda_hub(struct device_node *np)
3763 struct device_node *phbn;
3764 const __be64 *prop64;
3767 pr_info("Probing IODA IO-Hub %s\n", np->full_name);
3769 prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
3771 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
3774 hub_id = be64_to_cpup(prop64);
3775 pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
3777 /* Count child PHBs */
3778 for_each_child_of_node(np, phbn) {
3779 /* Look for IODA1 PHBs */
3780 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
3781 pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);