2 * Support PCI/PCIe on PowerNV platforms
4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/crash_dump.h>
17 #include <linux/delay.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
20 #include <linux/memblock.h>
21 #include <linux/irq.h>
23 #include <linux/msi.h>
24 #include <linux/iommu.h>
25 #include <linux/rculist.h>
26 #include <linux/sizes.h>
28 #include <asm/sections.h>
31 #include <asm/pci-bridge.h>
32 #include <asm/machdep.h>
33 #include <asm/msi_bitmap.h>
34 #include <asm/ppc-pci.h>
36 #include <asm/iommu.h>
39 #include <asm/debugfs.h>
40 #include <asm/firmware.h>
41 #include <asm/pnv-pci.h>
42 #include <asm/mmzone.h>
44 #include <misc/cxl-base.h>
48 #include "../../../../drivers/pci/pci.h"
50 #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */
51 #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */
52 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000
54 static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_NVLINK",
57 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
59 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
71 if (pe->flags & PNV_IODA_PE_DEV)
72 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
73 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
74 sprintf(pfix, "%04x:%02x ",
75 pci_domain_nr(pe->pbus), pe->pbus->number);
77 else if (pe->flags & PNV_IODA_PE_VF)
78 sprintf(pfix, "%04x:%02x:%2x.%d",
79 pci_domain_nr(pe->parent_dev->bus),
80 (pe->rid & 0xff00) >> 8,
81 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
82 #endif /* CONFIG_PCI_IOV*/
84 printk("%spci %s: [PE# %.2x] %pV",
85 level, pfix, pe->pe_number, &vaf);
90 static bool pnv_iommu_bypass_disabled __read_mostly;
91 static bool pci_reset_phbs __read_mostly;
93 static int __init iommu_setup(char *str)
99 if (!strncmp(str, "nobypass", 8)) {
100 pnv_iommu_bypass_disabled = true;
101 pr_info("PowerNV: IOMMU bypass window disabled.\n");
104 str += strcspn(str, ",");
111 early_param("iommu", iommu_setup);
113 static int __init pci_reset_phbs_setup(char *str)
115 pci_reset_phbs = true;
119 early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup);
121 static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r)
124 * WARNING: We cannot rely on the resource flags. The Linux PCI
125 * allocation code sometimes decides to put a 64-bit prefetchable
126 * BAR in the 32-bit window, so we have to compare the addresses.
128 * For simplicity we only test resource start.
130 return (r->start >= phb->ioda.m64_base &&
131 r->start < (phb->ioda.m64_base + phb->ioda.m64_size));
134 static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags)
136 unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
138 return (resource_flags & flags) == flags;
141 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
145 phb->ioda.pe_array[pe_no].phb = phb;
146 phb->ioda.pe_array[pe_no].pe_number = pe_no;
149 * Clear the PE frozen state as it might be put into frozen state
150 * in the last PCI remove path. It's not harmful to do so when the
151 * PE is already in unfrozen state.
153 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
154 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
155 if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED)
156 pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n",
157 __func__, rc, phb->hose->global_number, pe_no);
159 return &phb->ioda.pe_array[pe_no];
162 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
164 if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) {
165 pr_warn("%s: Invalid PE %x on PHB#%x\n",
166 __func__, pe_no, phb->hose->global_number);
170 if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
171 pr_debug("%s: PE %x was reserved on PHB#%x\n",
172 __func__, pe_no, phb->hose->global_number);
174 pnv_ioda_init_pe(phb, pe_no);
177 static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb)
181 for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) {
182 if (!test_and_set_bit(pe, phb->ioda.pe_alloc))
183 return pnv_ioda_init_pe(phb, pe);
189 static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
191 struct pnv_phb *phb = pe->phb;
192 unsigned int pe_num = pe->pe_number;
195 WARN_ON(pe->npucomp); /* NPUs are not supposed to be freed */
197 memset(pe, 0, sizeof(struct pnv_ioda_pe));
198 clear_bit(pe_num, phb->ioda.pe_alloc);
201 /* The default M64 BAR is shared by all PEs */
202 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
208 /* Configure the default M64 BAR */
209 rc = opal_pci_set_phb_mem_window(phb->opal_id,
210 OPAL_M64_WINDOW_TYPE,
211 phb->ioda.m64_bar_idx,
215 if (rc != OPAL_SUCCESS) {
216 desc = "configuring";
220 /* Enable the default M64 BAR */
221 rc = opal_pci_phb_mmio_enable(phb->opal_id,
222 OPAL_M64_WINDOW_TYPE,
223 phb->ioda.m64_bar_idx,
224 OPAL_ENABLE_M64_SPLIT);
225 if (rc != OPAL_SUCCESS) {
231 * Exclude the segments for reserved and root bus PE, which
232 * are first or last two PEs.
234 r = &phb->hose->mem_resources[1];
235 if (phb->ioda.reserved_pe_idx == 0)
236 r->start += (2 * phb->ioda.m64_segsize);
237 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
238 r->end -= (2 * phb->ioda.m64_segsize);
240 pr_warn(" Cannot strip M64 segment for reserved PE#%x\n",
241 phb->ioda.reserved_pe_idx);
246 pr_warn(" Failure %lld %s M64 BAR#%d\n",
247 rc, desc, phb->ioda.m64_bar_idx);
248 opal_pci_phb_mmio_enable(phb->opal_id,
249 OPAL_M64_WINDOW_TYPE,
250 phb->ioda.m64_bar_idx,
255 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev,
256 unsigned long *pe_bitmap)
258 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
259 struct pnv_phb *phb = hose->private_data;
261 resource_size_t base, sgsz, start, end;
264 base = phb->ioda.m64_base;
265 sgsz = phb->ioda.m64_segsize;
266 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
267 r = &pdev->resource[i];
268 if (!r->parent || !pnv_pci_is_m64(phb, r))
271 start = _ALIGN_DOWN(r->start - base, sgsz);
272 end = _ALIGN_UP(r->end - base, sgsz);
273 for (segno = start / sgsz; segno < end / sgsz; segno++) {
275 set_bit(segno, pe_bitmap);
277 pnv_ioda_reserve_pe(phb, segno);
282 static int pnv_ioda1_init_m64(struct pnv_phb *phb)
288 * There are 16 M64 BARs, each of which has 8 segments. So
289 * there are as many M64 segments as the maximum number of
292 for (index = 0; index < PNV_IODA1_M64_NUM; index++) {
293 unsigned long base, segsz = phb->ioda.m64_segsize;
296 base = phb->ioda.m64_base +
297 index * PNV_IODA1_M64_SEGS * segsz;
298 rc = opal_pci_set_phb_mem_window(phb->opal_id,
299 OPAL_M64_WINDOW_TYPE, index, base, 0,
300 PNV_IODA1_M64_SEGS * segsz);
301 if (rc != OPAL_SUCCESS) {
302 pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n",
303 rc, phb->hose->global_number, index);
307 rc = opal_pci_phb_mmio_enable(phb->opal_id,
308 OPAL_M64_WINDOW_TYPE, index,
309 OPAL_ENABLE_M64_SPLIT);
310 if (rc != OPAL_SUCCESS) {
311 pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n",
312 rc, phb->hose->global_number, index);
318 * Exclude the segments for reserved and root bus PE, which
319 * are first or last two PEs.
321 r = &phb->hose->mem_resources[1];
322 if (phb->ioda.reserved_pe_idx == 0)
323 r->start += (2 * phb->ioda.m64_segsize);
324 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
325 r->end -= (2 * phb->ioda.m64_segsize);
327 WARN(1, "Wrong reserved PE#%x on PHB#%x\n",
328 phb->ioda.reserved_pe_idx, phb->hose->global_number);
333 for ( ; index >= 0; index--)
334 opal_pci_phb_mmio_enable(phb->opal_id,
335 OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64);
340 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus,
341 unsigned long *pe_bitmap,
344 struct pci_dev *pdev;
346 list_for_each_entry(pdev, &bus->devices, bus_list) {
347 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap);
349 if (all && pdev->subordinate)
350 pnv_ioda_reserve_m64_pe(pdev->subordinate,
355 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all)
357 struct pci_controller *hose = pci_bus_to_host(bus);
358 struct pnv_phb *phb = hose->private_data;
359 struct pnv_ioda_pe *master_pe, *pe;
360 unsigned long size, *pe_alloc;
363 /* Root bus shouldn't use M64 */
364 if (pci_is_root_bus(bus))
367 /* Allocate bitmap */
368 size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
369 pe_alloc = kzalloc(size, GFP_KERNEL);
371 pr_warn("%s: Out of memory !\n",
376 /* Figure out reserved PE numbers by the PE */
377 pnv_ioda_reserve_m64_pe(bus, pe_alloc, all);
380 * the current bus might not own M64 window and that's all
381 * contributed by its child buses. For the case, we needn't
382 * pick M64 dependent PE#.
384 if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) {
390 * Figure out the master PE and put all slave PEs to master
391 * PE's list to form compound PE.
395 while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) <
396 phb->ioda.total_pe_num) {
397 pe = &phb->ioda.pe_array[i];
399 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
401 pe->flags |= PNV_IODA_PE_MASTER;
402 INIT_LIST_HEAD(&pe->slaves);
405 pe->flags |= PNV_IODA_PE_SLAVE;
406 pe->master = master_pe;
407 list_add_tail(&pe->list, &master_pe->slaves);
411 * P7IOC supports M64DT, which helps mapping M64 segment
412 * to one particular PE#. However, PHB3 has fixed mapping
413 * between M64 segment and PE#. In order to have same logic
414 * for P7IOC and PHB3, we enforce fixed mapping between M64
415 * segment and PE# on P7IOC.
417 if (phb->type == PNV_PHB_IODA1) {
420 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
421 pe->pe_number, OPAL_M64_WINDOW_TYPE,
422 pe->pe_number / PNV_IODA1_M64_SEGS,
423 pe->pe_number % PNV_IODA1_M64_SEGS);
424 if (rc != OPAL_SUCCESS)
425 pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n",
426 __func__, rc, phb->hose->global_number,
435 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
437 struct pci_controller *hose = phb->hose;
438 struct device_node *dn = hose->dn;
439 struct resource *res;
444 if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) {
445 pr_info(" Not support M64 window\n");
449 if (!firmware_has_feature(FW_FEATURE_OPAL)) {
450 pr_info(" Firmware too old to support M64 window\n");
454 r = of_get_property(dn, "ibm,opal-m64-window", NULL);
456 pr_info(" No <ibm,opal-m64-window> on %pOF\n",
462 * Find the available M64 BAR range and pickup the last one for
463 * covering the whole 64-bits space. We support only one range.
465 if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges",
467 /* In absence of the property, assume 0..15 */
471 /* We only support 64 bits in our allocator */
472 if (m64_range[1] > 63) {
473 pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n",
474 __func__, m64_range[1], phb->hose->global_number);
477 /* Empty range, no m64 */
478 if (m64_range[1] <= m64_range[0]) {
479 pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n",
480 __func__, phb->hose->global_number);
484 /* Configure M64 informations */
485 res = &hose->mem_resources[1];
486 res->name = dn->full_name;
487 res->start = of_translate_address(dn, r + 2);
488 res->end = res->start + of_read_number(r + 4, 2) - 1;
489 res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
490 pci_addr = of_read_number(r, 2);
491 hose->mem_offset[1] = res->start - pci_addr;
493 phb->ioda.m64_size = resource_size(res);
494 phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num;
495 phb->ioda.m64_base = pci_addr;
497 /* This lines up nicely with the display from processing OF ranges */
498 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n",
499 res->start, res->end, pci_addr, m64_range[0],
500 m64_range[0] + m64_range[1] - 1);
502 /* Mark all M64 used up by default */
503 phb->ioda.m64_bar_alloc = (unsigned long)-1;
505 /* Use last M64 BAR to cover M64 window */
507 phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1];
509 pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx);
511 /* Mark remaining ones free */
512 for (i = m64_range[0]; i < m64_range[1]; i++)
513 clear_bit(i, &phb->ioda.m64_bar_alloc);
516 * Setup init functions for M64 based on IODA version, IODA3 uses
519 if (phb->type == PNV_PHB_IODA1)
520 phb->init_m64 = pnv_ioda1_init_m64;
522 phb->init_m64 = pnv_ioda2_init_m64;
525 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
527 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
528 struct pnv_ioda_pe *slave;
531 /* Fetch master PE */
532 if (pe->flags & PNV_IODA_PE_SLAVE) {
534 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
537 pe_no = pe->pe_number;
540 /* Freeze master PE */
541 rc = opal_pci_eeh_freeze_set(phb->opal_id,
543 OPAL_EEH_ACTION_SET_FREEZE_ALL);
544 if (rc != OPAL_SUCCESS) {
545 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
546 __func__, rc, phb->hose->global_number, pe_no);
550 /* Freeze slave PEs */
551 if (!(pe->flags & PNV_IODA_PE_MASTER))
554 list_for_each_entry(slave, &pe->slaves, list) {
555 rc = opal_pci_eeh_freeze_set(phb->opal_id,
557 OPAL_EEH_ACTION_SET_FREEZE_ALL);
558 if (rc != OPAL_SUCCESS)
559 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
560 __func__, rc, phb->hose->global_number,
565 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
567 struct pnv_ioda_pe *pe, *slave;
571 pe = &phb->ioda.pe_array[pe_no];
572 if (pe->flags & PNV_IODA_PE_SLAVE) {
574 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
575 pe_no = pe->pe_number;
578 /* Clear frozen state for master PE */
579 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
580 if (rc != OPAL_SUCCESS) {
581 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
582 __func__, rc, opt, phb->hose->global_number, pe_no);
586 if (!(pe->flags & PNV_IODA_PE_MASTER))
589 /* Clear frozen state for slave PEs */
590 list_for_each_entry(slave, &pe->slaves, list) {
591 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
594 if (rc != OPAL_SUCCESS) {
595 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
596 __func__, rc, opt, phb->hose->global_number,
605 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
607 struct pnv_ioda_pe *slave, *pe;
608 u8 fstate = 0, state;
612 /* Sanity check on PE number */
613 if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num)
614 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
617 * Fetch the master PE and the PE instance might be
618 * not initialized yet.
620 pe = &phb->ioda.pe_array[pe_no];
621 if (pe->flags & PNV_IODA_PE_SLAVE) {
623 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
624 pe_no = pe->pe_number;
627 /* Check the master PE */
628 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
629 &state, &pcierr, NULL);
630 if (rc != OPAL_SUCCESS) {
631 pr_warn("%s: Failure %lld getting "
632 "PHB#%x-PE#%x state\n",
634 phb->hose->global_number, pe_no);
635 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
638 /* Check the slave PE */
639 if (!(pe->flags & PNV_IODA_PE_MASTER))
642 list_for_each_entry(slave, &pe->slaves, list) {
643 rc = opal_pci_eeh_freeze_status(phb->opal_id,
648 if (rc != OPAL_SUCCESS) {
649 pr_warn("%s: Failure %lld getting "
650 "PHB#%x-PE#%x state\n",
652 phb->hose->global_number, slave->pe_number);
653 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
657 * Override the result based on the ascending
667 struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
669 struct pci_controller *hose = pci_bus_to_host(dev->bus);
670 struct pnv_phb *phb = hose->private_data;
671 struct pci_dn *pdn = pci_get_pdn(dev);
675 if (pdn->pe_number == IODA_INVALID_PE)
677 return &phb->ioda.pe_array[pdn->pe_number];
680 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
681 struct pnv_ioda_pe *parent,
682 struct pnv_ioda_pe *child,
685 const char *desc = is_add ? "adding" : "removing";
686 uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
687 OPAL_REMOVE_PE_FROM_DOMAIN;
688 struct pnv_ioda_pe *slave;
691 /* Parent PE affects child PE */
692 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
693 child->pe_number, op);
694 if (rc != OPAL_SUCCESS) {
695 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
700 if (!(child->flags & PNV_IODA_PE_MASTER))
703 /* Compound case: parent PE affects slave PEs */
704 list_for_each_entry(slave, &child->slaves, list) {
705 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
706 slave->pe_number, op);
707 if (rc != OPAL_SUCCESS) {
708 pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
717 static int pnv_ioda_set_peltv(struct pnv_phb *phb,
718 struct pnv_ioda_pe *pe,
721 struct pnv_ioda_pe *slave;
722 struct pci_dev *pdev = NULL;
726 * Clear PE frozen state. If it's master PE, we need
727 * clear slave PE frozen state as well.
730 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
731 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
732 if (pe->flags & PNV_IODA_PE_MASTER) {
733 list_for_each_entry(slave, &pe->slaves, list)
734 opal_pci_eeh_freeze_clear(phb->opal_id,
736 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
741 * Associate PE in PELT. We need add the PE into the
742 * corresponding PELT-V as well. Otherwise, the error
743 * originated from the PE might contribute to other
746 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
750 /* For compound PEs, any one affects all of them */
751 if (pe->flags & PNV_IODA_PE_MASTER) {
752 list_for_each_entry(slave, &pe->slaves, list) {
753 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
759 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
760 pdev = pe->pbus->self;
761 else if (pe->flags & PNV_IODA_PE_DEV)
762 pdev = pe->pdev->bus->self;
763 #ifdef CONFIG_PCI_IOV
764 else if (pe->flags & PNV_IODA_PE_VF)
765 pdev = pe->parent_dev;
766 #endif /* CONFIG_PCI_IOV */
768 struct pci_dn *pdn = pci_get_pdn(pdev);
769 struct pnv_ioda_pe *parent;
771 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
772 parent = &phb->ioda.pe_array[pdn->pe_number];
773 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
778 pdev = pdev->bus->self;
784 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
786 struct pci_dev *parent;
787 uint8_t bcomp, dcomp, fcomp;
791 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
795 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
796 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
797 parent = pe->pbus->self;
798 if (pe->flags & PNV_IODA_PE_BUS_ALL)
799 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
804 case 1: bcomp = OpalPciBusAll; break;
805 case 2: bcomp = OpalPciBus7Bits; break;
806 case 4: bcomp = OpalPciBus6Bits; break;
807 case 8: bcomp = OpalPciBus5Bits; break;
808 case 16: bcomp = OpalPciBus4Bits; break;
809 case 32: bcomp = OpalPciBus3Bits; break;
811 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
813 /* Do an exact match only */
814 bcomp = OpalPciBusAll;
816 rid_end = pe->rid + (count << 8);
818 #ifdef CONFIG_PCI_IOV
819 if (pe->flags & PNV_IODA_PE_VF)
820 parent = pe->parent_dev;
823 parent = pe->pdev->bus->self;
824 bcomp = OpalPciBusAll;
825 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
826 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
827 rid_end = pe->rid + 1;
830 /* Clear the reverse map */
831 for (rid = pe->rid; rid < rid_end; rid++)
832 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE;
834 /* Release from all parents PELT-V */
836 struct pci_dn *pdn = pci_get_pdn(parent);
837 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
838 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
839 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
840 /* XXX What to do in case of error ? */
842 parent = parent->bus->self;
845 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
846 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
848 /* Disassociate PE in PELT */
849 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
850 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
852 pe_warn(pe, "OPAL error %lld remove self from PELTV\n", rc);
853 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
854 bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
856 pe_err(pe, "OPAL error %lld trying to setup PELT table\n", rc);
860 #ifdef CONFIG_PCI_IOV
861 pe->parent_dev = NULL;
867 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
869 struct pci_dev *parent;
870 uint8_t bcomp, dcomp, fcomp;
871 long rc, rid_end, rid;
873 /* Bus validation ? */
877 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
878 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
879 parent = pe->pbus->self;
880 if (pe->flags & PNV_IODA_PE_BUS_ALL)
881 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
886 case 1: bcomp = OpalPciBusAll; break;
887 case 2: bcomp = OpalPciBus7Bits; break;
888 case 4: bcomp = OpalPciBus6Bits; break;
889 case 8: bcomp = OpalPciBus5Bits; break;
890 case 16: bcomp = OpalPciBus4Bits; break;
891 case 32: bcomp = OpalPciBus3Bits; break;
893 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
895 /* Do an exact match only */
896 bcomp = OpalPciBusAll;
898 rid_end = pe->rid + (count << 8);
900 #ifdef CONFIG_PCI_IOV
901 if (pe->flags & PNV_IODA_PE_VF)
902 parent = pe->parent_dev;
904 #endif /* CONFIG_PCI_IOV */
905 parent = pe->pdev->bus->self;
906 bcomp = OpalPciBusAll;
907 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
908 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
909 rid_end = pe->rid + 1;
913 * Associate PE in PELT. We need add the PE into the
914 * corresponding PELT-V as well. Otherwise, the error
915 * originated from the PE might contribute to other
918 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
919 bcomp, dcomp, fcomp, OPAL_MAP_PE);
921 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
926 * Configure PELTV. NPUs don't have a PELTV table so skip
927 * configuration on them.
929 if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI)
930 pnv_ioda_set_peltv(phb, pe, true);
932 /* Setup reverse map */
933 for (rid = pe->rid; rid < rid_end; rid++)
934 phb->ioda.pe_rmap[rid] = pe->pe_number;
936 /* Setup one MVTs on IODA1 */
937 if (phb->type != PNV_PHB_IODA1) {
942 pe->mve_number = pe->pe_number;
943 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
944 if (rc != OPAL_SUCCESS) {
945 pe_err(pe, "OPAL error %ld setting up MVE %x\n",
949 rc = opal_pci_set_mve_enable(phb->opal_id,
950 pe->mve_number, OPAL_ENABLE_MVE);
952 pe_err(pe, "OPAL error %ld enabling MVE %x\n",
962 #ifdef CONFIG_PCI_IOV
963 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
965 struct pci_dn *pdn = pci_get_pdn(dev);
967 struct resource *res, res2;
968 resource_size_t size;
975 * "offset" is in VFs. The M64 windows are sized so that when they
976 * are segmented, each segment is the same size as the IOV BAR.
977 * Each segment is in a separate PE, and the high order bits of the
978 * address are the PE number. Therefore, each VF's BAR is in a
979 * separate PE, and changing the IOV BAR start address changes the
980 * range of PEs the VFs are in.
982 num_vfs = pdn->num_vfs;
983 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
984 res = &dev->resource[i + PCI_IOV_RESOURCES];
985 if (!res->flags || !res->parent)
989 * The actual IOV BAR range is determined by the start address
990 * and the actual size for num_vfs VFs BAR. This check is to
991 * make sure that after shifting, the range will not overlap
992 * with another device.
994 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
995 res2.flags = res->flags;
996 res2.start = res->start + (size * offset);
997 res2.end = res2.start + (size * num_vfs) - 1;
999 if (res2.end > res->end) {
1000 dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
1001 i, &res2, res, num_vfs, offset);
1007 * Since M64 BAR shares segments among all possible 256 PEs,
1008 * we have to shift the beginning of PF IOV BAR to make it start from
1009 * the segment which belongs to the PE number assigned to the first VF.
1010 * This creates a "hole" in the /proc/iomem which could be used for
1011 * allocating other resources so we reserve this area below and
1012 * release when IOV is released.
1014 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1015 res = &dev->resource[i + PCI_IOV_RESOURCES];
1016 if (!res->flags || !res->parent)
1019 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
1021 res->start += size * offset;
1023 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
1024 i, &res2, res, (offset > 0) ? "En" : "Dis",
1028 devm_release_resource(&dev->dev, &pdn->holes[i]);
1029 memset(&pdn->holes[i], 0, sizeof(pdn->holes[i]));
1032 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
1035 pdn->holes[i].start = res2.start;
1036 pdn->holes[i].end = res2.start + size * offset - 1;
1037 pdn->holes[i].flags = IORESOURCE_BUS;
1038 pdn->holes[i].name = "pnv_iov_reserved";
1039 devm_request_resource(&dev->dev, res->parent,
1045 #endif /* CONFIG_PCI_IOV */
1047 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
1049 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1050 struct pnv_phb *phb = hose->private_data;
1051 struct pci_dn *pdn = pci_get_pdn(dev);
1052 struct pnv_ioda_pe *pe;
1055 pr_err("%s: Device tree node not associated properly\n",
1059 if (pdn->pe_number != IODA_INVALID_PE)
1062 pe = pnv_ioda_alloc_pe(phb);
1064 pr_warn("%s: Not enough PE# available, disabling device\n",
1069 /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
1070 * pointer in the PE data structure, both should be destroyed at the
1071 * same time. However, this needs to be looked at more closely again
1072 * once we actually start removing things (Hotplug, SR-IOV, ...)
1074 * At some point we want to remove the PDN completely anyways
1077 pdn->pe_number = pe->pe_number;
1078 pe->flags = PNV_IODA_PE_DEV;
1081 pe->mve_number = -1;
1082 pe->rid = dev->bus->number << 8 | pdn->devfn;
1084 pe_info(pe, "Associated device to PE\n");
1086 if (pnv_ioda_configure_pe(phb, pe)) {
1087 /* XXX What do we do here ? */
1088 pnv_ioda_free_pe(pe);
1089 pdn->pe_number = IODA_INVALID_PE;
1095 /* Put PE to the list */
1096 list_add_tail(&pe->list, &phb->ioda.pe_list);
1101 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
1103 struct pci_dev *dev;
1105 list_for_each_entry(dev, &bus->devices, bus_list) {
1106 struct pci_dn *pdn = pci_get_pdn(dev);
1109 pr_warn("%s: No device node associated with device !\n",
1115 * In partial hotplug case, the PCI device might be still
1116 * associated with the PE and needn't attach it to the PE
1119 if (pdn->pe_number != IODA_INVALID_PE)
1123 pdn->pe_number = pe->pe_number;
1124 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1125 pnv_ioda_setup_same_PE(dev->subordinate, pe);
1130 * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1131 * single PCI bus. Another one that contains the primary PCI bus and its
1132 * subordinate PCI devices and buses. The second type of PE is normally
1133 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1135 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
1137 struct pci_controller *hose = pci_bus_to_host(bus);
1138 struct pnv_phb *phb = hose->private_data;
1139 struct pnv_ioda_pe *pe = NULL;
1140 unsigned int pe_num;
1143 * In partial hotplug case, the PE instance might be still alive.
1144 * We should reuse it instead of allocating a new one.
1146 pe_num = phb->ioda.pe_rmap[bus->number << 8];
1147 if (pe_num != IODA_INVALID_PE) {
1148 pe = &phb->ioda.pe_array[pe_num];
1149 pnv_ioda_setup_same_PE(bus, pe);
1153 /* PE number for root bus should have been reserved */
1154 if (pci_is_root_bus(bus) &&
1155 phb->ioda.root_pe_idx != IODA_INVALID_PE)
1156 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx];
1158 /* Check if PE is determined by M64 */
1160 pe = pnv_ioda_pick_m64_pe(bus, all);
1162 /* The PE number isn't pinned by M64 */
1164 pe = pnv_ioda_alloc_pe(phb);
1167 pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1168 __func__, pci_domain_nr(bus), bus->number);
1172 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1175 pe->mve_number = -1;
1176 pe->rid = bus->busn_res.start << 8;
1179 pe_info(pe, "Secondary bus %pad..%pad associated with PE#%x\n",
1180 &bus->busn_res.start, &bus->busn_res.end,
1183 pe_info(pe, "Secondary bus %pad associated with PE#%x\n",
1184 &bus->busn_res.start, pe->pe_number);
1186 if (pnv_ioda_configure_pe(phb, pe)) {
1187 /* XXX What do we do here ? */
1188 pnv_ioda_free_pe(pe);
1193 /* Associate it with all child devices */
1194 pnv_ioda_setup_same_PE(bus, pe);
1196 /* Put PE to the list */
1197 list_add_tail(&pe->list, &phb->ioda.pe_list);
1202 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
1204 int pe_num, found_pe = false, rc;
1206 struct pnv_ioda_pe *pe;
1207 struct pci_dev *gpu_pdev;
1208 struct pci_dn *npu_pdn;
1209 struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
1210 struct pnv_phb *phb = hose->private_data;
1213 * Due to a hardware errata PE#0 on the NPU is reserved for
1214 * error handling. This means we only have three PEs remaining
1215 * which need to be assigned to four links, implying some
1216 * links must share PEs.
1218 * To achieve this we assign PEs such that NPUs linking the
1219 * same GPU get assigned the same PE.
1221 gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
1222 for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
1223 pe = &phb->ioda.pe_array[pe_num];
1227 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
1229 * This device has the same peer GPU so should
1230 * be assigned the same PE as the existing
1233 dev_info(&npu_pdev->dev,
1234 "Associating to existing PE %x\n", pe_num);
1235 pci_dev_get(npu_pdev);
1236 npu_pdn = pci_get_pdn(npu_pdev);
1237 rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
1238 npu_pdn->pe_number = pe_num;
1239 phb->ioda.pe_rmap[rid] = pe->pe_number;
1241 /* Map the PE to this link */
1242 rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
1244 OPAL_COMPARE_RID_DEVICE_NUMBER,
1245 OPAL_COMPARE_RID_FUNCTION_NUMBER,
1247 WARN_ON(rc != OPAL_SUCCESS);
1255 * Could not find an existing PE so allocate a new
1258 return pnv_ioda_setup_dev_PE(npu_pdev);
1263 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
1265 struct pci_dev *pdev;
1267 list_for_each_entry(pdev, &bus->devices, bus_list)
1268 pnv_ioda_setup_npu_PE(pdev);
1271 static void pnv_pci_ioda_setup_PEs(void)
1273 struct pci_controller *hose;
1274 struct pnv_phb *phb;
1275 struct pci_bus *bus;
1276 struct pci_dev *pdev;
1277 struct pnv_ioda_pe *pe;
1279 list_for_each_entry(hose, &hose_list, list_node) {
1280 phb = hose->private_data;
1281 if (phb->type == PNV_PHB_NPU_NVLINK) {
1282 /* PE#0 is needed for error reporting */
1283 pnv_ioda_reserve_pe(phb, 0);
1284 pnv_ioda_setup_npu_PEs(hose->bus);
1285 if (phb->model == PNV_PHB_MODEL_NPU2)
1286 WARN_ON_ONCE(pnv_npu2_init(hose));
1288 if (phb->type == PNV_PHB_NPU_OCAPI) {
1290 list_for_each_entry(pdev, &bus->devices, bus_list)
1291 pnv_ioda_setup_dev_PE(pdev);
1294 list_for_each_entry(hose, &hose_list, list_node) {
1295 phb = hose->private_data;
1296 if (phb->type != PNV_PHB_IODA2)
1299 list_for_each_entry(pe, &phb->ioda.pe_list, list)
1300 pnv_npu2_map_lpar(pe, MSR_DR | MSR_PR | MSR_HV);
1304 #ifdef CONFIG_PCI_IOV
1305 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
1307 struct pci_bus *bus;
1308 struct pci_controller *hose;
1309 struct pnv_phb *phb;
1315 hose = pci_bus_to_host(bus);
1316 phb = hose->private_data;
1317 pdn = pci_get_pdn(pdev);
1319 if (pdn->m64_single_mode)
1324 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1325 for (j = 0; j < m64_bars; j++) {
1326 if (pdn->m64_map[j][i] == IODA_INVALID_M64)
1328 opal_pci_phb_mmio_enable(phb->opal_id,
1329 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0);
1330 clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc);
1331 pdn->m64_map[j][i] = IODA_INVALID_M64;
1334 kfree(pdn->m64_map);
1338 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
1340 struct pci_bus *bus;
1341 struct pci_controller *hose;
1342 struct pnv_phb *phb;
1345 struct resource *res;
1349 resource_size_t size, start;
1354 hose = pci_bus_to_host(bus);
1355 phb = hose->private_data;
1356 pdn = pci_get_pdn(pdev);
1357 total_vfs = pci_sriov_get_totalvfs(pdev);
1359 if (pdn->m64_single_mode)
1364 pdn->m64_map = kmalloc_array(m64_bars,
1365 sizeof(*pdn->m64_map),
1369 /* Initialize the m64_map to IODA_INVALID_M64 */
1370 for (i = 0; i < m64_bars ; i++)
1371 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++)
1372 pdn->m64_map[i][j] = IODA_INVALID_M64;
1375 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1376 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1377 if (!res->flags || !res->parent)
1380 for (j = 0; j < m64_bars; j++) {
1382 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1383 phb->ioda.m64_bar_idx + 1, 0);
1385 if (win >= phb->ioda.m64_bar_idx + 1)
1387 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1389 pdn->m64_map[j][i] = win;
1391 if (pdn->m64_single_mode) {
1392 size = pci_iov_resource_size(pdev,
1393 PCI_IOV_RESOURCES + i);
1394 start = res->start + size * j;
1396 size = resource_size(res);
1400 /* Map the M64 here */
1401 if (pdn->m64_single_mode) {
1402 pe_num = pdn->pe_num_map[j];
1403 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1404 pe_num, OPAL_M64_WINDOW_TYPE,
1405 pdn->m64_map[j][i], 0);
1408 rc = opal_pci_set_phb_mem_window(phb->opal_id,
1409 OPAL_M64_WINDOW_TYPE,
1416 if (rc != OPAL_SUCCESS) {
1417 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1422 if (pdn->m64_single_mode)
1423 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1424 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2);
1426 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1427 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1);
1429 if (rc != OPAL_SUCCESS) {
1430 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1439 pnv_pci_vf_release_m64(pdev, num_vfs);
1443 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1446 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1448 struct iommu_table *tbl;
1451 tbl = pe->table_group.tables[0];
1452 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1454 pe_warn(pe, "OPAL error %lld release DMA window\n", rc);
1456 pnv_pci_ioda2_set_bypass(pe, false);
1457 if (pe->table_group.group) {
1458 iommu_group_put(pe->table_group.group);
1459 BUG_ON(pe->table_group.group);
1461 iommu_tce_table_put(tbl);
1464 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
1466 struct pci_bus *bus;
1467 struct pci_controller *hose;
1468 struct pnv_phb *phb;
1469 struct pnv_ioda_pe *pe, *pe_n;
1473 hose = pci_bus_to_host(bus);
1474 phb = hose->private_data;
1475 pdn = pci_get_pdn(pdev);
1477 if (!pdev->is_physfn)
1480 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1481 if (pe->parent_dev != pdev)
1484 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1486 /* Remove from list */
1487 mutex_lock(&phb->ioda.pe_list_mutex);
1488 list_del(&pe->list);
1489 mutex_unlock(&phb->ioda.pe_list_mutex);
1491 pnv_ioda_deconfigure_pe(phb, pe);
1493 pnv_ioda_free_pe(pe);
1497 void pnv_pci_sriov_disable(struct pci_dev *pdev)
1499 struct pci_bus *bus;
1500 struct pci_controller *hose;
1501 struct pnv_phb *phb;
1502 struct pnv_ioda_pe *pe;
1507 hose = pci_bus_to_host(bus);
1508 phb = hose->private_data;
1509 pdn = pci_get_pdn(pdev);
1510 num_vfs = pdn->num_vfs;
1512 /* Release VF PEs */
1513 pnv_ioda_release_vf_PE(pdev);
1515 if (phb->type == PNV_PHB_IODA2) {
1516 if (!pdn->m64_single_mode)
1517 pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map);
1519 /* Release M64 windows */
1520 pnv_pci_vf_release_m64(pdev, num_vfs);
1522 /* Release PE numbers */
1523 if (pdn->m64_single_mode) {
1524 for (i = 0; i < num_vfs; i++) {
1525 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1528 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1529 pnv_ioda_free_pe(pe);
1532 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1533 /* Releasing pe_num_map */
1534 kfree(pdn->pe_num_map);
1538 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1539 struct pnv_ioda_pe *pe);
1540 #ifdef CONFIG_IOMMU_API
1541 static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe,
1542 struct iommu_table_group *table_group, struct pci_bus *bus);
1545 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1547 struct pci_bus *bus;
1548 struct pci_controller *hose;
1549 struct pnv_phb *phb;
1550 struct pnv_ioda_pe *pe;
1556 hose = pci_bus_to_host(bus);
1557 phb = hose->private_data;
1558 pdn = pci_get_pdn(pdev);
1560 if (!pdev->is_physfn)
1563 /* Reserve PE for each VF */
1564 for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1565 if (pdn->m64_single_mode)
1566 pe_num = pdn->pe_num_map[vf_index];
1568 pe_num = *pdn->pe_num_map + vf_index;
1570 pe = &phb->ioda.pe_array[pe_num];
1571 pe->pe_number = pe_num;
1573 pe->flags = PNV_IODA_PE_VF;
1575 pe->parent_dev = pdev;
1576 pe->mve_number = -1;
1577 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) |
1578 pci_iov_virtfn_devfn(pdev, vf_index);
1580 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n",
1581 hose->global_number, pdev->bus->number,
1582 PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
1583 PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num);
1585 if (pnv_ioda_configure_pe(phb, pe)) {
1586 /* XXX What do we do here ? */
1587 pnv_ioda_free_pe(pe);
1592 /* Put PE to the list */
1593 mutex_lock(&phb->ioda.pe_list_mutex);
1594 list_add_tail(&pe->list, &phb->ioda.pe_list);
1595 mutex_unlock(&phb->ioda.pe_list_mutex);
1597 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1598 #ifdef CONFIG_IOMMU_API
1599 iommu_register_group(&pe->table_group,
1600 pe->phb->hose->global_number, pe->pe_number);
1601 pnv_ioda_setup_bus_iommu_group(pe, &pe->table_group, NULL);
1606 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1608 struct pci_bus *bus;
1609 struct pci_controller *hose;
1610 struct pnv_phb *phb;
1611 struct pnv_ioda_pe *pe;
1617 hose = pci_bus_to_host(bus);
1618 phb = hose->private_data;
1619 pdn = pci_get_pdn(pdev);
1621 if (phb->type == PNV_PHB_IODA2) {
1622 if (!pdn->vfs_expanded) {
1623 dev_info(&pdev->dev, "don't support this SRIOV device"
1624 " with non 64bit-prefetchable IOV BAR\n");
1629 * When M64 BARs functions in Single PE mode, the number of VFs
1630 * could be enabled must be less than the number of M64 BARs.
1632 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) {
1633 dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n");
1637 /* Allocating pe_num_map */
1638 if (pdn->m64_single_mode)
1639 pdn->pe_num_map = kmalloc_array(num_vfs,
1640 sizeof(*pdn->pe_num_map),
1643 pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL);
1645 if (!pdn->pe_num_map)
1648 if (pdn->m64_single_mode)
1649 for (i = 0; i < num_vfs; i++)
1650 pdn->pe_num_map[i] = IODA_INVALID_PE;
1652 /* Calculate available PE for required VFs */
1653 if (pdn->m64_single_mode) {
1654 for (i = 0; i < num_vfs; i++) {
1655 pe = pnv_ioda_alloc_pe(phb);
1661 pdn->pe_num_map[i] = pe->pe_number;
1664 mutex_lock(&phb->ioda.pe_alloc_mutex);
1665 *pdn->pe_num_map = bitmap_find_next_zero_area(
1666 phb->ioda.pe_alloc, phb->ioda.total_pe_num,
1668 if (*pdn->pe_num_map >= phb->ioda.total_pe_num) {
1669 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1670 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1671 kfree(pdn->pe_num_map);
1674 bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1675 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1677 pdn->num_vfs = num_vfs;
1679 /* Assign M64 window accordingly */
1680 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
1682 dev_info(&pdev->dev, "Not enough M64 window resources\n");
1687 * When using one M64 BAR to map one IOV BAR, we need to shift
1688 * the IOV BAR according to the PE# allocated to the VFs.
1689 * Otherwise, the PE# for the VF will conflict with others.
1691 if (!pdn->m64_single_mode) {
1692 ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map);
1699 pnv_ioda_setup_vf_PE(pdev, num_vfs);
1704 if (pdn->m64_single_mode) {
1705 for (i = 0; i < num_vfs; i++) {
1706 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1709 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1710 pnv_ioda_free_pe(pe);
1713 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1715 /* Releasing pe_num_map */
1716 kfree(pdn->pe_num_map);
1721 int pnv_pcibios_sriov_disable(struct pci_dev *pdev)
1723 pnv_pci_sriov_disable(pdev);
1725 /* Release PCI data */
1726 remove_dev_pci_data(pdev);
1730 int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1732 /* Allocate PCI data */
1733 add_dev_pci_data(pdev);
1735 return pnv_pci_sriov_enable(pdev, num_vfs);
1737 #endif /* CONFIG_PCI_IOV */
1739 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
1741 struct pci_dn *pdn = pci_get_pdn(pdev);
1742 struct pnv_ioda_pe *pe;
1745 * The function can be called while the PE#
1746 * hasn't been assigned. Do nothing for the
1749 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1752 pe = &phb->ioda.pe_array[pdn->pe_number];
1753 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1754 pdev->dev.archdata.dma_offset = pe->tce_bypass_base;
1755 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1757 * Note: iommu_add_device() will fail here as
1758 * for physical PE: the device is already added by now;
1759 * for virtual PE: sysfs entries are not ready yet and
1760 * tce_iommu_bus_notifier will add the device to a group later.
1765 * Reconfigure TVE#0 to be usable as 64-bit DMA space.
1767 * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses.
1768 * Devices can only access more than that if bit 59 of the PCI address is set
1769 * by hardware, which indicates TVE#1 should be used instead of TVE#0.
1770 * Many PCI devices are not capable of addressing that many bits, and as a
1771 * result are limited to the 4GB of virtual memory made available to 32-bit
1774 * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit
1775 * devices by configuring the virtual memory past the first 4GB inaccessible
1776 * by 64-bit DMAs. This should only be used by devices that want more than
1777 * 4GB, and only on PEs that have no 32-bit devices.
1779 * Currently this will only work on PHB3 (POWER8).
1781 static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe)
1783 u64 window_size, table_size, tce_count, addr;
1784 struct page *table_pages;
1785 u64 tce_order = 28; /* 256MB TCEs */
1790 * Window size needs to be a power of two, but needs to account for
1791 * shifting memory by the 4GB offset required to skip 32bit space.
1793 window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32));
1794 tce_count = window_size >> tce_order;
1795 table_size = tce_count << 3;
1797 if (table_size < PAGE_SIZE)
1798 table_size = PAGE_SIZE;
1800 table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL,
1801 get_order(table_size));
1805 tces = page_address(table_pages);
1809 memset(tces, 0, table_size);
1811 for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) {
1812 tces[(addr + (1ULL << 32)) >> tce_order] =
1813 cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE);
1816 rc = opal_pci_map_pe_dma_window(pe->phb->opal_id,
1818 /* reconfigure window 0 */
1819 (pe->pe_number << 1) + 0,
1824 if (rc == OPAL_SUCCESS) {
1825 pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n");
1829 pe_err(pe, "Error configuring 64-bit DMA bypass\n");
1833 static bool pnv_pci_ioda_iommu_bypass_supported(struct pci_dev *pdev,
1836 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1837 struct pnv_phb *phb = hose->private_data;
1838 struct pci_dn *pdn = pci_get_pdn(pdev);
1839 struct pnv_ioda_pe *pe;
1841 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1844 pe = &phb->ioda.pe_array[pdn->pe_number];
1845 if (pe->tce_bypass_enabled) {
1846 u64 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1847 if (dma_mask >= top)
1852 * If the device can't set the TCE bypass bit but still wants
1853 * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to
1854 * bypass the 32-bit region and be usable for 64-bit DMAs.
1855 * The device needs to be able to address all of this space.
1857 if (dma_mask >> 32 &&
1858 dma_mask > (memory_hotplug_max() + (1ULL << 32)) &&
1859 /* pe->pdev should be set if it's a single device, pe->pbus if not */
1860 (pe->device_count == 1 || !pe->pbus) &&
1861 phb->model == PNV_PHB_MODEL_PHB3) {
1862 /* Configure the bypass mode */
1863 s64 rc = pnv_pci_ioda_dma_64bit_bypass(pe);
1866 /* 4GB offset bypasses 32-bit space */
1867 pdev->dev.archdata.dma_offset = (1ULL << 32);
1874 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus)
1876 struct pci_dev *dev;
1878 list_for_each_entry(dev, &bus->devices, bus_list) {
1879 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1880 dev->dev.archdata.dma_offset = pe->tce_bypass_base;
1882 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1883 pnv_ioda_setup_bus_dma(pe, dev->subordinate);
1887 static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb,
1890 return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) :
1891 (phb->regs + 0x210);
1894 static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl,
1895 unsigned long index, unsigned long npages, bool rm)
1897 struct iommu_table_group_link *tgl = list_first_entry_or_null(
1898 &tbl->it_group_list, struct iommu_table_group_link,
1900 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1901 struct pnv_ioda_pe, table_group);
1902 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
1903 unsigned long start, end, inc;
1905 start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1906 end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1909 /* p7ioc-style invalidation, 2 TCEs per write */
1910 start |= (1ull << 63);
1911 end |= (1ull << 63);
1913 end |= inc - 1; /* round up end to be different than start */
1915 mb(); /* Ensure above stores are visible */
1916 while (start <= end) {
1918 __raw_rm_writeq_be(start, invalidate);
1920 __raw_writeq_be(start, invalidate);
1926 * The iommu layer will do another mb() for us on build()
1927 * and we don't care on free()
1931 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1932 long npages, unsigned long uaddr,
1933 enum dma_data_direction direction,
1934 unsigned long attrs)
1936 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1940 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1945 #ifdef CONFIG_IOMMU_API
1946 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
1947 unsigned long *hpa, enum dma_data_direction *direction)
1949 long ret = pnv_tce_xchg(tbl, index, hpa, direction, true);
1952 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false);
1957 static int pnv_ioda1_tce_xchg_rm(struct iommu_table *tbl, long index,
1958 unsigned long *hpa, enum dma_data_direction *direction)
1960 long ret = pnv_tce_xchg(tbl, index, hpa, direction, false);
1963 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, true);
1969 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
1972 pnv_tce_free(tbl, index, npages);
1974 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1977 static struct iommu_table_ops pnv_ioda1_iommu_ops = {
1978 .set = pnv_ioda1_tce_build,
1979 #ifdef CONFIG_IOMMU_API
1980 .exchange = pnv_ioda1_tce_xchg,
1981 .exchange_rm = pnv_ioda1_tce_xchg_rm,
1982 .useraddrptr = pnv_tce_useraddrptr,
1984 .clear = pnv_ioda1_tce_free,
1988 #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0)
1989 #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1)
1990 #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2)
1992 static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
1994 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm);
1995 const unsigned long val = PHB3_TCE_KILL_INVAL_ALL;
1997 mb(); /* Ensure previous TCE table stores are visible */
1999 __raw_rm_writeq_be(val, invalidate);
2001 __raw_writeq_be(val, invalidate);
2004 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)
2006 /* 01xb - invalidate TCEs that match the specified PE# */
2007 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false);
2008 unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
2010 mb(); /* Ensure above stores are visible */
2011 __raw_writeq_be(val, invalidate);
2014 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm,
2015 unsigned shift, unsigned long index,
2016 unsigned long npages)
2018 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
2019 unsigned long start, end, inc;
2021 /* We'll invalidate DMA address in PE scope */
2022 start = PHB3_TCE_KILL_INVAL_ONE;
2023 start |= (pe->pe_number & 0xFF);
2026 /* Figure out the start, end and step */
2027 start |= (index << shift);
2028 end |= ((index + npages - 1) << shift);
2029 inc = (0x1ull << shift);
2032 while (start <= end) {
2034 __raw_rm_writeq_be(start, invalidate);
2036 __raw_writeq_be(start, invalidate);
2041 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
2043 struct pnv_phb *phb = pe->phb;
2045 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
2046 pnv_pci_phb3_tce_invalidate_pe(pe);
2048 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE,
2049 pe->pe_number, 0, 0, 0);
2052 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
2053 unsigned long index, unsigned long npages, bool rm)
2055 struct iommu_table_group_link *tgl;
2057 list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) {
2058 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
2059 struct pnv_ioda_pe, table_group);
2060 struct pnv_phb *phb = pe->phb;
2061 unsigned int shift = tbl->it_page_shift;
2064 * NVLink1 can use the TCE kill register directly as
2065 * it's the same as PHB3. NVLink2 is different and
2066 * should go via the OPAL call.
2068 if (phb->model == PNV_PHB_MODEL_NPU) {
2070 * The NVLink hardware does not support TCE kill
2071 * per TCE entry so we have to invalidate
2072 * the entire cache for it.
2074 pnv_pci_phb3_tce_invalidate_entire(phb, rm);
2077 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
2078 pnv_pci_phb3_tce_invalidate(pe, rm, shift,
2081 opal_pci_tce_kill(phb->opal_id,
2082 OPAL_PCI_TCE_KILL_PAGES,
2083 pe->pe_number, 1u << shift,
2084 index << shift, npages);
2088 void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
2090 if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3)
2091 pnv_pci_phb3_tce_invalidate_entire(phb, rm);
2093 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0);
2096 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
2097 long npages, unsigned long uaddr,
2098 enum dma_data_direction direction,
2099 unsigned long attrs)
2101 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
2105 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2110 #ifdef CONFIG_IOMMU_API
2111 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
2112 unsigned long *hpa, enum dma_data_direction *direction)
2114 long ret = pnv_tce_xchg(tbl, index, hpa, direction, true);
2117 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);
2122 static int pnv_ioda2_tce_xchg_rm(struct iommu_table *tbl, long index,
2123 unsigned long *hpa, enum dma_data_direction *direction)
2125 long ret = pnv_tce_xchg(tbl, index, hpa, direction, false);
2128 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, true);
2134 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
2137 pnv_tce_free(tbl, index, npages);
2139 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2142 static struct iommu_table_ops pnv_ioda2_iommu_ops = {
2143 .set = pnv_ioda2_tce_build,
2144 #ifdef CONFIG_IOMMU_API
2145 .exchange = pnv_ioda2_tce_xchg,
2146 .exchange_rm = pnv_ioda2_tce_xchg_rm,
2147 .useraddrptr = pnv_tce_useraddrptr,
2149 .clear = pnv_ioda2_tce_free,
2151 .free = pnv_pci_ioda2_table_free_pages,
2154 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data)
2156 unsigned int *weight = (unsigned int *)data;
2158 /* This is quite simplistic. The "base" weight of a device
2159 * is 10. 0 means no DMA is to be accounted for it.
2161 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
2164 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
2165 dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
2166 dev->class == PCI_CLASS_SERIAL_USB_EHCI)
2168 else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
2176 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe)
2178 unsigned int weight = 0;
2180 /* SRIOV VF has same DMA32 weight as its PF */
2181 #ifdef CONFIG_PCI_IOV
2182 if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) {
2183 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight);
2188 if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) {
2189 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight);
2190 } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) {
2191 struct pci_dev *pdev;
2193 list_for_each_entry(pdev, &pe->pbus->devices, bus_list)
2194 pnv_pci_ioda_dev_dma_weight(pdev, &weight);
2195 } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) {
2196 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight);
2202 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
2203 struct pnv_ioda_pe *pe)
2206 struct page *tce_mem = NULL;
2207 struct iommu_table *tbl;
2208 unsigned int weight, total_weight = 0;
2209 unsigned int tce32_segsz, base, segs, avail, i;
2213 /* XXX FIXME: Handle 64-bit only DMA devices */
2214 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
2215 /* XXX FIXME: Allocate multi-level tables on PHB3 */
2216 weight = pnv_pci_ioda_pe_dma_weight(pe);
2220 pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight,
2222 segs = (weight * phb->ioda.dma32_count) / total_weight;
2227 * Allocate contiguous DMA32 segments. We begin with the expected
2228 * number of segments. With one more attempt, the number of DMA32
2229 * segments to be allocated is decreased by one until one segment
2230 * is allocated successfully.
2233 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) {
2234 for (avail = 0, i = base; i < base + segs; i++) {
2235 if (phb->ioda.dma32_segmap[i] ==
2246 pe_warn(pe, "No available DMA32 segments\n");
2251 tbl = pnv_pci_table_alloc(phb->hose->node);
2255 iommu_register_group(&pe->table_group, phb->hose->global_number,
2257 pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
2259 /* Grab a 32-bit TCE table */
2260 pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
2261 weight, total_weight, base, segs);
2262 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
2263 base * PNV_IODA1_DMA32_SEGSIZE,
2264 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1);
2266 /* XXX Currently, we allocate one big contiguous table for the
2267 * TCEs. We only really need one chunk per 256M of TCE space
2268 * (ie per segment) but that's an optimization for later, it
2269 * requires some added smarts with our get/put_tce implementation
2271 * Each TCE page is 4KB in size and each TCE entry occupies 8
2274 tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3);
2275 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
2276 get_order(tce32_segsz * segs));
2278 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
2281 addr = page_address(tce_mem);
2282 memset(addr, 0, tce32_segsz * segs);
2285 for (i = 0; i < segs; i++) {
2286 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2289 __pa(addr) + tce32_segsz * i,
2290 tce32_segsz, IOMMU_PAGE_SIZE_4K);
2292 pe_err(pe, " Failed to configure 32-bit TCE table, err %lld\n",
2298 /* Setup DMA32 segment mapping */
2299 for (i = base; i < base + segs; i++)
2300 phb->ioda.dma32_segmap[i] = pe->pe_number;
2302 /* Setup linux iommu table */
2303 pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs,
2304 base * PNV_IODA1_DMA32_SEGSIZE,
2305 IOMMU_PAGE_SHIFT_4K);
2307 tbl->it_ops = &pnv_ioda1_iommu_ops;
2308 pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
2309 pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
2310 iommu_init_table(tbl, phb->hose->node);
2312 if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2313 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2317 /* XXX Failure: Try to fallback to 64-bit only ? */
2319 __free_pages(tce_mem, get_order(tce32_segsz * segs));
2321 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
2322 iommu_tce_table_put(tbl);
2326 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
2327 int num, struct iommu_table *tbl)
2329 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2331 struct pnv_phb *phb = pe->phb;
2333 const unsigned long size = tbl->it_indirect_levels ?
2334 tbl->it_level_size : tbl->it_size;
2335 const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
2336 const __u64 win_size = tbl->it_size << tbl->it_page_shift;
2338 pe_info(pe, "Setting up window#%d %llx..%llx pg=%lx\n",
2339 num, start_addr, start_addr + win_size - 1,
2340 IOMMU_PAGE_SIZE(tbl));
2343 * Map TCE table through TVT. The TVE index is the PE number
2344 * shifted by 1 bit for 32-bits DMA space.
2346 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2348 (pe->pe_number << 1) + num,
2349 tbl->it_indirect_levels + 1,
2352 IOMMU_PAGE_SIZE(tbl));
2354 pe_err(pe, "Failed to configure TCE table, err %lld\n", rc);
2358 pnv_pci_link_table_and_group(phb->hose->node, num,
2359 tbl, &pe->table_group);
2360 pnv_pci_ioda2_tce_invalidate_pe(pe);
2365 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
2367 uint16_t window_id = (pe->pe_number << 1 ) + 1;
2370 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2372 phys_addr_t top = memblock_end_of_DRAM();
2374 top = roundup_pow_of_two(top);
2375 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2378 pe->tce_bypass_base,
2381 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2384 pe->tce_bypass_base,
2388 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2390 pe->tce_bypass_enabled = enable;
2393 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2394 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2395 bool alloc_userspace_copy, struct iommu_table **ptbl)
2397 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2399 int nid = pe->phb->hose->node;
2400 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2402 struct iommu_table *tbl;
2404 tbl = pnv_pci_table_alloc(nid);
2408 tbl->it_ops = &pnv_ioda2_iommu_ops;
2410 ret = pnv_pci_ioda2_table_alloc_pages(nid,
2411 bus_offset, page_shift, window_size,
2412 levels, alloc_userspace_copy, tbl);
2414 iommu_tce_table_put(tbl);
2423 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2425 struct iommu_table *tbl = NULL;
2429 * crashkernel= specifies the kdump kernel's maximum memory at
2430 * some offset and there is no guaranteed the result is a power
2431 * of 2, which will cause errors later.
2433 const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
2436 * In memory constrained environments, e.g. kdump kernel, the
2437 * DMA window can be larger than available memory, which will
2438 * cause errors later.
2440 const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory);
2442 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0,
2443 IOMMU_PAGE_SHIFT_4K,
2445 POWERNV_IOMMU_DEFAULT_LEVELS, false, &tbl);
2447 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2452 iommu_init_table(tbl, pe->phb->hose->node);
2454 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2456 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2458 iommu_tce_table_put(tbl);
2462 if (!pnv_iommu_bypass_disabled)
2463 pnv_pci_ioda2_set_bypass(pe, true);
2466 * Set table base for the case of IOMMU DMA use. Usually this is done
2467 * from dma_dev_setup() which is not called when a device is returned
2468 * from VFIO so do it here.
2471 set_iommu_table_base(&pe->pdev->dev, tbl);
2476 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2477 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2480 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2482 struct pnv_phb *phb = pe->phb;
2485 pe_info(pe, "Removing DMA window #%d\n", num);
2487 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2488 (pe->pe_number << 1) + num,
2489 0/* levels */, 0/* table address */,
2490 0/* table size */, 0/* page size */);
2492 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2494 pnv_pci_ioda2_tce_invalidate_pe(pe);
2496 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2502 #ifdef CONFIG_IOMMU_API
2503 unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2504 __u64 window_size, __u32 levels)
2506 unsigned long bytes = 0;
2507 const unsigned window_shift = ilog2(window_size);
2508 unsigned entries_shift = window_shift - page_shift;
2509 unsigned table_shift = entries_shift + 3;
2510 unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2511 unsigned long direct_table_size;
2513 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2514 !is_power_of_2(window_size))
2517 /* Calculate a direct table size from window_size and levels */
2518 entries_shift = (entries_shift + levels - 1) / levels;
2519 table_shift = entries_shift + 3;
2520 table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2521 direct_table_size = 1UL << table_shift;
2523 for ( ; levels; --levels) {
2524 bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2526 tce_table_size /= direct_table_size;
2527 tce_table_size <<= 3;
2528 tce_table_size = max_t(unsigned long,
2529 tce_table_size, direct_table_size);
2532 return bytes + bytes; /* one for HW table, one for userspace copy */
2535 static long pnv_pci_ioda2_create_table_userspace(
2536 struct iommu_table_group *table_group,
2537 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2538 struct iommu_table **ptbl)
2540 long ret = pnv_pci_ioda2_create_table(table_group,
2541 num, page_shift, window_size, levels, true, ptbl);
2544 (*ptbl)->it_allocated_size = pnv_pci_ioda2_get_table_size(
2545 page_shift, window_size, levels);
2549 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
2551 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2553 /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2554 struct iommu_table *tbl = pe->table_group.tables[0];
2556 pnv_pci_ioda2_set_bypass(pe, false);
2557 pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2559 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2561 set_iommu_table_base(&pe->pdev->dev, NULL);
2562 iommu_tce_table_put(tbl);
2565 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2567 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2570 pnv_pci_ioda2_setup_default_config(pe);
2572 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2575 static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
2576 .get_table_size = pnv_pci_ioda2_get_table_size,
2577 .create_table = pnv_pci_ioda2_create_table_userspace,
2578 .set_window = pnv_pci_ioda2_set_window,
2579 .unset_window = pnv_pci_ioda2_unset_window,
2580 .take_ownership = pnv_ioda2_take_ownership,
2581 .release_ownership = pnv_ioda2_release_ownership,
2584 static void pnv_ioda_setup_bus_iommu_group_add_devices(struct pnv_ioda_pe *pe,
2585 struct iommu_table_group *table_group,
2586 struct pci_bus *bus)
2588 struct pci_dev *dev;
2590 list_for_each_entry(dev, &bus->devices, bus_list) {
2591 iommu_add_device(table_group, &dev->dev);
2593 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
2594 pnv_ioda_setup_bus_iommu_group_add_devices(pe,
2595 table_group, dev->subordinate);
2599 static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe,
2600 struct iommu_table_group *table_group, struct pci_bus *bus)
2603 if (pe->flags & PNV_IODA_PE_DEV)
2604 iommu_add_device(table_group, &pe->pdev->dev);
2606 if ((pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) || bus)
2607 pnv_ioda_setup_bus_iommu_group_add_devices(pe, table_group,
2611 static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb);
2613 static void pnv_pci_ioda_setup_iommu_api(void)
2615 struct pci_controller *hose;
2616 struct pnv_phb *phb;
2617 struct pnv_ioda_pe *pe;
2620 * There are 4 types of PEs:
2621 * - PNV_IODA_PE_BUS: a downstream port with an adapter,
2622 * created from pnv_pci_setup_bridge();
2623 * - PNV_IODA_PE_BUS_ALL: a PCI-PCIX bridge with devices behind it,
2624 * created from pnv_pci_setup_bridge();
2625 * - PNV_IODA_PE_VF: a SRIOV virtual function,
2626 * created from pnv_pcibios_sriov_enable();
2627 * - PNV_IODA_PE_DEV: an NPU or OCAPI device,
2628 * created from pnv_pci_ioda_fixup().
2630 * Normally a PE is represented by an IOMMU group, however for
2631 * devices with side channels the groups need to be more strict.
2633 list_for_each_entry(hose, &hose_list, list_node) {
2634 phb = hose->private_data;
2636 if (phb->type == PNV_PHB_NPU_NVLINK ||
2637 phb->type == PNV_PHB_NPU_OCAPI)
2640 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2641 struct iommu_table_group *table_group;
2643 table_group = pnv_try_setup_npu_table_group(pe);
2645 if (!pnv_pci_ioda_pe_dma_weight(pe))
2648 table_group = &pe->table_group;
2649 iommu_register_group(&pe->table_group,
2650 pe->phb->hose->global_number,
2653 pnv_ioda_setup_bus_iommu_group(pe, table_group,
2659 * Now we have all PHBs discovered, time to add NPU devices to
2660 * the corresponding IOMMU groups.
2662 list_for_each_entry(hose, &hose_list, list_node) {
2663 unsigned long pgsizes;
2665 phb = hose->private_data;
2667 if (phb->type != PNV_PHB_NPU_NVLINK)
2670 pgsizes = pnv_ioda_parse_tce_sizes(phb);
2671 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2673 * IODA2 bridges get this set up from
2674 * pci_controller_ops::setup_bridge but NPU bridges
2675 * do not have this hook defined so we do it here.
2677 pe->table_group.pgsizes = pgsizes;
2678 pnv_npu_compound_attach(pe);
2682 #else /* !CONFIG_IOMMU_API */
2683 static void pnv_pci_ioda_setup_iommu_api(void) { };
2686 static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb)
2688 struct pci_controller *hose = phb->hose;
2689 struct device_node *dn = hose->dn;
2690 unsigned long mask = 0;
2694 count = of_property_count_u32_elems(dn, "ibm,supported-tce-sizes");
2696 mask = SZ_4K | SZ_64K;
2697 /* Add 16M for POWER8 by default */
2698 if (cpu_has_feature(CPU_FTR_ARCH_207S) &&
2699 !cpu_has_feature(CPU_FTR_ARCH_300))
2700 mask |= SZ_16M | SZ_256M;
2704 for (i = 0; i < count; i++) {
2705 rc = of_property_read_u32_index(dn, "ibm,supported-tce-sizes",
2708 mask |= 1ULL << val;
2714 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2715 struct pnv_ioda_pe *pe)
2719 if (!pnv_pci_ioda_pe_dma_weight(pe))
2722 /* TVE #1 is selected by PCI address bit 59 */
2723 pe->tce_bypass_base = 1ull << 59;
2725 /* The PE will reserve all possible 32-bits space */
2726 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
2727 phb->ioda.m32_pci_base);
2729 /* Setup linux iommu table */
2730 pe->table_group.tce32_start = 0;
2731 pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2732 pe->table_group.max_dynamic_windows_supported =
2733 IOMMU_TABLE_GROUP_MAX_TABLES;
2734 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2735 pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb);
2736 #ifdef CONFIG_IOMMU_API
2737 pe->table_group.ops = &pnv_pci_ioda2_ops;
2740 rc = pnv_pci_ioda2_setup_default_config(pe);
2744 if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2745 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2748 int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq)
2750 struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2753 return opal_pci_msi_eoi(phb->opal_id, hw_irq);
2756 static void pnv_ioda2_msi_eoi(struct irq_data *d)
2759 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2760 struct irq_chip *chip = irq_data_get_irq_chip(d);
2762 rc = pnv_opal_pci_msi_eoi(chip, hw_irq);
2769 void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2771 struct irq_data *idata;
2772 struct irq_chip *ichip;
2774 /* The MSI EOI OPAL call is only needed on PHB3 */
2775 if (phb->model != PNV_PHB_MODEL_PHB3)
2778 if (!phb->ioda.irq_chip_init) {
2780 * First time we setup an MSI IRQ, we need to setup the
2781 * corresponding IRQ chip to route correctly.
2783 idata = irq_get_irq_data(virq);
2784 ichip = irq_data_get_irq_chip(idata);
2785 phb->ioda.irq_chip_init = 1;
2786 phb->ioda.irq_chip = *ichip;
2787 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2789 irq_set_chip(virq, &phb->ioda.irq_chip);
2793 * Returns true iff chip is something that we could call
2794 * pnv_opal_pci_msi_eoi for.
2796 bool is_pnv_opal_msi(struct irq_chip *chip)
2798 return chip->irq_eoi == pnv_ioda2_msi_eoi;
2800 EXPORT_SYMBOL_GPL(is_pnv_opal_msi);
2802 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2803 unsigned int hwirq, unsigned int virq,
2804 unsigned int is_64, struct msi_msg *msg)
2806 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2807 unsigned int xive_num = hwirq - phb->msi_base;
2811 /* No PE assigned ? bail out ... no MSI for you ! */
2815 /* Check if we have an MVE */
2816 if (pe->mve_number < 0)
2819 /* Force 32-bit MSI on some broken devices */
2820 if (dev->no_64bit_msi)
2823 /* Assign XIVE to PE */
2824 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2826 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2827 pci_name(dev), rc, xive_num);
2834 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2837 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2841 msg->address_hi = be64_to_cpu(addr64) >> 32;
2842 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
2846 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2849 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2853 msg->address_hi = 0;
2854 msg->address_lo = be32_to_cpu(addr32);
2856 msg->data = be32_to_cpu(data);
2858 pnv_set_msi_irq_chip(phb, virq);
2860 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2861 " address=%x_%08x data=%x PE# %x\n",
2862 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2863 msg->address_hi, msg->address_lo, data, pe->pe_number);
2868 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2871 const __be32 *prop = of_get_property(phb->hose->dn,
2872 "ibm,opal-msi-ranges", NULL);
2875 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2880 phb->msi_base = be32_to_cpup(prop);
2881 count = be32_to_cpup(prop + 1);
2882 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
2883 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2884 phb->hose->global_number);
2888 phb->msi_setup = pnv_pci_ioda_msi_setup;
2889 phb->msi32_support = 1;
2890 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2891 count, phb->msi_base);
2894 #ifdef CONFIG_PCI_IOV
2895 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
2897 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
2898 struct pnv_phb *phb = hose->private_data;
2899 const resource_size_t gate = phb->ioda.m64_segsize >> 2;
2900 struct resource *res;
2902 resource_size_t size, total_vf_bar_sz;
2906 if (!pdev->is_physfn || pci_dev_is_added(pdev))
2909 pdn = pci_get_pdn(pdev);
2910 pdn->vfs_expanded = 0;
2911 pdn->m64_single_mode = false;
2913 total_vfs = pci_sriov_get_totalvfs(pdev);
2914 mul = phb->ioda.total_pe_num;
2915 total_vf_bar_sz = 0;
2917 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2918 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2919 if (!res->flags || res->parent)
2921 if (!pnv_pci_is_m64_flags(res->flags)) {
2922 dev_warn(&pdev->dev, "Don't support SR-IOV with"
2923 " non M64 VF BAR%d: %pR. \n",
2928 total_vf_bar_sz += pci_iov_resource_size(pdev,
2929 i + PCI_IOV_RESOURCES);
2932 * If bigger than quarter of M64 segment size, just round up
2935 * Generally, one M64 BAR maps one IOV BAR. To avoid conflict
2936 * with other devices, IOV BAR size is expanded to be
2937 * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64
2938 * segment size , the expanded size would equal to half of the
2939 * whole M64 space size, which will exhaust the M64 Space and
2940 * limit the system flexibility. This is a design decision to
2941 * set the boundary to quarter of the M64 segment size.
2943 if (total_vf_bar_sz > gate) {
2944 mul = roundup_pow_of_two(total_vfs);
2945 dev_info(&pdev->dev,
2946 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n",
2947 total_vf_bar_sz, gate, mul);
2948 pdn->m64_single_mode = true;
2953 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2954 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2955 if (!res->flags || res->parent)
2958 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
2960 * On PHB3, the minimum size alignment of M64 BAR in single
2963 if (pdn->m64_single_mode && (size < SZ_32M))
2965 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
2966 res->end = res->start + size * mul - 1;
2967 dev_dbg(&pdev->dev, " %pR\n", res);
2968 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
2971 pdn->vfs_expanded = mul;
2976 /* To save MMIO space, IOV BAR is truncated. */
2977 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2978 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2980 res->end = res->start - 1;
2983 #endif /* CONFIG_PCI_IOV */
2985 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
2986 struct resource *res)
2988 struct pnv_phb *phb = pe->phb;
2989 struct pci_bus_region region;
2993 if (!res || !res->flags || res->start > res->end)
2996 if (res->flags & IORESOURCE_IO) {
2997 region.start = res->start - phb->ioda.io_pci_base;
2998 region.end = res->end - phb->ioda.io_pci_base;
2999 index = region.start / phb->ioda.io_segsize;
3001 while (index < phb->ioda.total_pe_num &&
3002 region.start <= region.end) {
3003 phb->ioda.io_segmap[index] = pe->pe_number;
3004 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3005 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
3006 if (rc != OPAL_SUCCESS) {
3007 pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n",
3008 __func__, rc, index, pe->pe_number);
3012 region.start += phb->ioda.io_segsize;
3015 } else if ((res->flags & IORESOURCE_MEM) &&
3016 !pnv_pci_is_m64(phb, res)) {
3017 region.start = res->start -
3018 phb->hose->mem_offset[0] -
3019 phb->ioda.m32_pci_base;
3020 region.end = res->end -
3021 phb->hose->mem_offset[0] -
3022 phb->ioda.m32_pci_base;
3023 index = region.start / phb->ioda.m32_segsize;
3025 while (index < phb->ioda.total_pe_num &&
3026 region.start <= region.end) {
3027 phb->ioda.m32_segmap[index] = pe->pe_number;
3028 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3029 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
3030 if (rc != OPAL_SUCCESS) {
3031 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x",
3032 __func__, rc, index, pe->pe_number);
3036 region.start += phb->ioda.m32_segsize;
3043 * This function is supposed to be called on basis of PE from top
3044 * to bottom style. So the the I/O or MMIO segment assigned to
3045 * parent PE could be overridden by its child PEs if necessary.
3047 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
3049 struct pci_dev *pdev;
3053 * NOTE: We only care PCI bus based PE for now. For PCI
3054 * device based PE, for example SRIOV sensitive VF should
3055 * be figured out later.
3057 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
3059 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
3060 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
3061 pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);
3064 * If the PE contains all subordinate PCI buses, the
3065 * windows of the child bridges should be mapped to
3068 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
3070 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
3071 pnv_ioda_setup_pe_res(pe,
3072 &pdev->resource[PCI_BRIDGE_RESOURCES + i]);
3076 #ifdef CONFIG_DEBUG_FS
3077 static int pnv_pci_diag_data_set(void *data, u64 val)
3079 struct pci_controller *hose;
3080 struct pnv_phb *phb;
3086 hose = (struct pci_controller *)data;
3087 if (!hose || !hose->private_data)
3090 phb = hose->private_data;
3092 /* Retrieve the diag data from firmware */
3093 ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data,
3094 phb->diag_data_size);
3095 if (ret != OPAL_SUCCESS)
3098 /* Print the diag data to the kernel log */
3099 pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data);
3103 DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL,
3104 pnv_pci_diag_data_set, "%llu\n");
3106 #endif /* CONFIG_DEBUG_FS */
3108 static void pnv_pci_ioda_create_dbgfs(void)
3110 #ifdef CONFIG_DEBUG_FS
3111 struct pci_controller *hose, *tmp;
3112 struct pnv_phb *phb;
3115 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3116 phb = hose->private_data;
3118 /* Notify initialization of PHB done */
3119 phb->initialized = 1;
3121 sprintf(name, "PCI%04x", hose->global_number);
3122 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
3124 pr_warn("%s: Error on creating debugfs on PHB#%x\n",
3125 __func__, hose->global_number);
3129 debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose,
3130 &pnv_pci_diag_data_fops);
3132 #endif /* CONFIG_DEBUG_FS */
3135 static void pnv_pci_enable_bridge(struct pci_bus *bus)
3137 struct pci_dev *dev = bus->self;
3138 struct pci_bus *child;
3140 /* Empty bus ? bail */
3141 if (list_empty(&bus->devices))
3145 * If there's a bridge associated with that bus enable it. This works
3146 * around races in the generic code if the enabling is done during
3147 * parallel probing. This can be removed once those races have been
3151 int rc = pci_enable_device(dev);
3153 pci_err(dev, "Error enabling bridge (%d)\n", rc);
3154 pci_set_master(dev);
3157 /* Perform the same to child busses */
3158 list_for_each_entry(child, &bus->children, node)
3159 pnv_pci_enable_bridge(child);
3162 static void pnv_pci_enable_bridges(void)
3164 struct pci_controller *hose;
3166 list_for_each_entry(hose, &hose_list, list_node)
3167 pnv_pci_enable_bridge(hose->bus);
3170 static void pnv_pci_ioda_fixup(void)
3172 pnv_pci_ioda_setup_PEs();
3173 pnv_pci_ioda_setup_iommu_api();
3174 pnv_pci_ioda_create_dbgfs();
3176 pnv_pci_enable_bridges();
3179 pnv_eeh_post_init();
3184 * Returns the alignment for I/O or memory windows for P2P
3185 * bridges. That actually depends on how PEs are segmented.
3186 * For now, we return I/O or M32 segment size for PE sensitive
3187 * P2P bridges. Otherwise, the default values (4KiB for I/O,
3188 * 1MiB for memory) will be returned.
3190 * The current PCI bus might be put into one PE, which was
3191 * create against the parent PCI bridge. For that case, we
3192 * needn't enlarge the alignment so that we can save some
3195 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
3198 struct pci_dev *bridge;
3199 struct pci_controller *hose = pci_bus_to_host(bus);
3200 struct pnv_phb *phb = hose->private_data;
3201 int num_pci_bridges = 0;
3205 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
3207 if (num_pci_bridges >= 2)
3211 bridge = bridge->bus->self;
3215 * We fall back to M32 if M64 isn't supported. We enforce the M64
3216 * alignment for any 64-bit resource, PCIe doesn't care and
3217 * bridges only do 64-bit prefetchable anyway.
3219 if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type))
3220 return phb->ioda.m64_segsize;
3221 if (type & IORESOURCE_MEM)
3222 return phb->ioda.m32_segsize;
3224 return phb->ioda.io_segsize;
3228 * We are updating root port or the upstream port of the
3229 * bridge behind the root port with PHB's windows in order
3230 * to accommodate the changes on required resources during
3231 * PCI (slot) hotplug, which is connected to either root
3232 * port or the downstream ports of PCIe switch behind the
3235 static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus,
3238 struct pci_controller *hose = pci_bus_to_host(bus);
3239 struct pnv_phb *phb = hose->private_data;
3240 struct pci_dev *bridge = bus->self;
3241 struct resource *r, *w;
3242 bool msi_region = false;
3245 /* Check if we need apply fixup to the bridge's windows */
3246 if (!pci_is_root_bus(bridge->bus) &&
3247 !pci_is_root_bus(bridge->bus->self->bus))
3250 /* Fixup the resources */
3251 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
3252 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i];
3253 if (!r->flags || !r->parent)
3257 if (r->flags & type & IORESOURCE_IO)
3258 w = &hose->io_resource;
3259 else if (pnv_pci_is_m64(phb, r) &&
3260 (type & IORESOURCE_PREFETCH) &&
3261 phb->ioda.m64_segsize)
3262 w = &hose->mem_resources[1];
3263 else if (r->flags & type & IORESOURCE_MEM) {
3264 w = &hose->mem_resources[0];
3268 r->start = w->start;
3271 /* The 64KB 32-bits MSI region shouldn't be included in
3272 * the 32-bits bridge window. Otherwise, we can see strange
3273 * issues. One of them is EEH error observed on Garrison.
3275 * Exclude top 1MB region which is the minimal alignment of
3276 * 32-bits bridge window.
3285 static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type)
3287 struct pci_controller *hose = pci_bus_to_host(bus);
3288 struct pnv_phb *phb = hose->private_data;
3289 struct pci_dev *bridge = bus->self;
3290 struct pnv_ioda_pe *pe;
3291 bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE);
3293 /* Extend bridge's windows if necessary */
3294 pnv_pci_fixup_bridge_resources(bus, type);
3296 /* The PE for root bus should be realized before any one else */
3297 if (!phb->ioda.root_pe_populated) {
3298 pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false);
3300 phb->ioda.root_pe_idx = pe->pe_number;
3301 phb->ioda.root_pe_populated = true;
3305 /* Don't assign PE to PCI bus, which doesn't have subordinate devices */
3306 if (list_empty(&bus->devices))
3309 /* Reserve PEs according to used M64 resources */
3310 pnv_ioda_reserve_m64_pe(bus, NULL, all);
3313 * Assign PE. We might run here because of partial hotplug.
3314 * For the case, we just pick up the existing PE and should
3315 * not allocate resources again.
3317 pe = pnv_ioda_setup_bus_PE(bus, all);
3321 pnv_ioda_setup_pe_seg(pe);
3322 switch (phb->type) {
3324 pnv_pci_ioda1_setup_dma_pe(phb, pe);
3327 pnv_pci_ioda2_setup_dma_pe(phb, pe);
3330 pr_warn("%s: No DMA for PHB#%x (type %d)\n",
3331 __func__, phb->hose->global_number, phb->type);
3335 static resource_size_t pnv_pci_default_alignment(void)
3340 #ifdef CONFIG_PCI_IOV
3341 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
3344 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3345 struct pnv_phb *phb = hose->private_data;
3346 struct pci_dn *pdn = pci_get_pdn(pdev);
3347 resource_size_t align;
3350 * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the
3351 * SR-IOV. While from hardware perspective, the range mapped by M64
3352 * BAR should be size aligned.
3354 * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra
3355 * powernv-specific hardware restriction is gone. But if just use the
3356 * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with
3357 * in one segment of M64 #15, which introduces the PE conflict between
3358 * PF and VF. Based on this, the minimum alignment of an IOV BAR is
3361 * This function returns the total IOV BAR size if M64 BAR is in
3362 * Shared PE mode or just VF BAR size if not.
3363 * If the M64 BAR is in Single PE mode, return the VF BAR size or
3364 * M64 segment size if IOV BAR size is less.
3366 align = pci_iov_resource_size(pdev, resno);
3367 if (!pdn->vfs_expanded)
3369 if (pdn->m64_single_mode)
3370 return max(align, (resource_size_t)phb->ioda.m64_segsize);
3372 return pdn->vfs_expanded * align;
3374 #endif /* CONFIG_PCI_IOV */
3376 /* Prevent enabling devices for which we couldn't properly
3379 static bool pnv_pci_enable_device_hook(struct pci_dev *dev)
3381 struct pci_controller *hose = pci_bus_to_host(dev->bus);
3382 struct pnv_phb *phb = hose->private_data;
3385 /* The function is probably called while the PEs have
3386 * not be created yet. For example, resource reassignment
3387 * during PCI probe period. We just skip the check if
3390 if (!phb->initialized)
3393 pdn = pci_get_pdn(dev);
3394 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3400 static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group,
3403 struct pnv_ioda_pe *pe = container_of(table_group,
3404 struct pnv_ioda_pe, table_group);
3405 struct pnv_phb *phb = pe->phb;
3409 pe_info(pe, "Removing DMA window #%d\n", num);
3410 for (idx = 0; idx < phb->ioda.dma32_count; idx++) {
3411 if (phb->ioda.dma32_segmap[idx] != pe->pe_number)
3414 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
3415 idx, 0, 0ul, 0ul, 0ul);
3416 if (rc != OPAL_SUCCESS) {
3417 pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n",
3422 phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE;
3425 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
3426 return OPAL_SUCCESS;
3429 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe)
3431 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3432 struct iommu_table *tbl = pe->table_group.tables[0];
3438 rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0);
3439 if (rc != OPAL_SUCCESS)
3442 pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false);
3443 if (pe->table_group.group) {
3444 iommu_group_put(pe->table_group.group);
3445 WARN_ON(pe->table_group.group);
3448 free_pages(tbl->it_base, get_order(tbl->it_size << 3));
3449 iommu_tce_table_put(tbl);
3452 static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)
3454 struct iommu_table *tbl = pe->table_group.tables[0];
3455 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3456 #ifdef CONFIG_IOMMU_API
3463 #ifdef CONFIG_IOMMU_API
3464 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
3466 pe_warn(pe, "OPAL error %lld release DMA window\n", rc);
3469 pnv_pci_ioda2_set_bypass(pe, false);
3470 if (pe->table_group.group) {
3471 iommu_group_put(pe->table_group.group);
3472 WARN_ON(pe->table_group.group);
3475 iommu_tce_table_put(tbl);
3478 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe,
3482 struct pnv_phb *phb = pe->phb;
3486 for (idx = 0; idx < phb->ioda.total_pe_num; idx++) {
3487 if (map[idx] != pe->pe_number)
3490 if (win == OPAL_M64_WINDOW_TYPE)
3491 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3492 phb->ioda.reserved_pe_idx, win,
3493 idx / PNV_IODA1_M64_SEGS,
3494 idx % PNV_IODA1_M64_SEGS);
3496 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3497 phb->ioda.reserved_pe_idx, win, 0, idx);
3499 if (rc != OPAL_SUCCESS)
3500 pe_warn(pe, "Error %lld unmapping (%d) segment#%d\n",
3503 map[idx] = IODA_INVALID_PE;
3507 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe)
3509 struct pnv_phb *phb = pe->phb;
3511 if (phb->type == PNV_PHB_IODA1) {
3512 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE,
3513 phb->ioda.io_segmap);
3514 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3515 phb->ioda.m32_segmap);
3516 pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE,
3517 phb->ioda.m64_segmap);
3518 } else if (phb->type == PNV_PHB_IODA2) {
3519 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3520 phb->ioda.m32_segmap);
3524 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe)
3526 struct pnv_phb *phb = pe->phb;
3527 struct pnv_ioda_pe *slave, *tmp;
3529 list_del(&pe->list);
3530 switch (phb->type) {
3532 pnv_pci_ioda1_release_pe_dma(pe);
3535 pnv_pci_ioda2_release_pe_dma(pe);
3541 pnv_ioda_release_pe_seg(pe);
3542 pnv_ioda_deconfigure_pe(pe->phb, pe);
3544 /* Release slave PEs in the compound PE */
3545 if (pe->flags & PNV_IODA_PE_MASTER) {
3546 list_for_each_entry_safe(slave, tmp, &pe->slaves, list) {
3547 list_del(&slave->list);
3548 pnv_ioda_free_pe(slave);
3553 * The PE for root bus can be removed because of hotplug in EEH
3554 * recovery for fenced PHB error. We need to mark the PE dead so
3555 * that it can be populated again in PCI hot add path. The PE
3556 * shouldn't be destroyed as it's the global reserved resource.
3558 if (phb->ioda.root_pe_populated &&
3559 phb->ioda.root_pe_idx == pe->pe_number)
3560 phb->ioda.root_pe_populated = false;
3562 pnv_ioda_free_pe(pe);
3565 static void pnv_pci_release_device(struct pci_dev *pdev)
3567 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3568 struct pnv_phb *phb = hose->private_data;
3569 struct pci_dn *pdn = pci_get_pdn(pdev);
3570 struct pnv_ioda_pe *pe;
3572 if (pdev->is_virtfn)
3575 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3579 * PCI hotplug can happen as part of EEH error recovery. The @pdn
3580 * isn't removed and added afterwards in this scenario. We should
3581 * set the PE number in @pdn to an invalid one. Otherwise, the PE's
3582 * device count is decreased on removing devices while failing to
3583 * be increased on adding devices. It leads to unbalanced PE's device
3584 * count and eventually make normal PCI hotplug path broken.
3586 pe = &phb->ioda.pe_array[pdn->pe_number];
3587 pdn->pe_number = IODA_INVALID_PE;
3589 WARN_ON(--pe->device_count < 0);
3590 if (pe->device_count == 0)
3591 pnv_ioda_release_pe(pe);
3594 static void pnv_npu_disable_device(struct pci_dev *pdev)
3596 struct eeh_dev *edev = pci_dev_to_eeh_dev(pdev);
3597 struct eeh_pe *eehpe = edev ? edev->pe : NULL;
3599 if (eehpe && eeh_ops && eeh_ops->reset)
3600 eeh_ops->reset(eehpe, EEH_RESET_HOT);
3603 static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
3605 struct pnv_phb *phb = hose->private_data;
3607 opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
3611 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3612 .dma_dev_setup = pnv_pci_dma_dev_setup,
3613 .dma_bus_setup = pnv_pci_dma_bus_setup,
3614 .iommu_bypass_supported = pnv_pci_ioda_iommu_bypass_supported,
3615 .setup_msi_irqs = pnv_setup_msi_irqs,
3616 .teardown_msi_irqs = pnv_teardown_msi_irqs,
3617 .enable_device_hook = pnv_pci_enable_device_hook,
3618 .release_device = pnv_pci_release_device,
3619 .window_alignment = pnv_pci_window_alignment,
3620 .setup_bridge = pnv_pci_setup_bridge,
3621 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3622 .shutdown = pnv_pci_ioda_shutdown,
3625 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
3626 .dma_dev_setup = pnv_pci_dma_dev_setup,
3627 .setup_msi_irqs = pnv_setup_msi_irqs,
3628 .teardown_msi_irqs = pnv_teardown_msi_irqs,
3629 .enable_device_hook = pnv_pci_enable_device_hook,
3630 .window_alignment = pnv_pci_window_alignment,
3631 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3632 .shutdown = pnv_pci_ioda_shutdown,
3633 .disable_device = pnv_npu_disable_device,
3636 static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = {
3637 .enable_device_hook = pnv_pci_enable_device_hook,
3638 .window_alignment = pnv_pci_window_alignment,
3639 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3640 .shutdown = pnv_pci_ioda_shutdown,
3643 static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3644 u64 hub_id, int ioda_type)
3646 struct pci_controller *hose;
3647 struct pnv_phb *phb;
3648 unsigned long size, m64map_off, m32map_off, pemap_off;
3649 unsigned long iomap_off = 0, dma32map_off = 0;
3651 const __be64 *prop64;
3652 const __be32 *prop32;
3659 if (!of_device_is_available(np))
3662 pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np);
3664 prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3666 pr_err(" Missing \"ibm,opal-phbid\" property !\n");
3669 phb_id = be64_to_cpup(prop64);
3670 pr_debug(" PHB-ID : 0x%016llx\n", phb_id);
3672 phb = memblock_alloc(sizeof(*phb), SMP_CACHE_BYTES);
3674 panic("%s: Failed to allocate %zu bytes\n", __func__,
3677 /* Allocate PCI controller */
3678 phb->hose = hose = pcibios_alloc_controller(np);
3680 pr_err(" Can't allocate PCI controller for %pOF\n",
3682 memblock_free(__pa(phb), sizeof(struct pnv_phb));
3686 spin_lock_init(&phb->lock);
3687 prop32 = of_get_property(np, "bus-range", &len);
3688 if (prop32 && len == 8) {
3689 hose->first_busno = be32_to_cpu(prop32[0]);
3690 hose->last_busno = be32_to_cpu(prop32[1]);
3692 pr_warn(" Broken <bus-range> on %pOF\n", np);
3693 hose->first_busno = 0;
3694 hose->last_busno = 0xff;
3696 hose->private_data = phb;
3697 phb->hub_id = hub_id;
3698 phb->opal_id = phb_id;
3699 phb->type = ioda_type;
3700 mutex_init(&phb->ioda.pe_alloc_mutex);
3702 /* Detect specific models for error handling */
3703 if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3704 phb->model = PNV_PHB_MODEL_P7IOC;
3705 else if (of_device_is_compatible(np, "ibm,power8-pciex"))
3706 phb->model = PNV_PHB_MODEL_PHB3;
3707 else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
3708 phb->model = PNV_PHB_MODEL_NPU;
3709 else if (of_device_is_compatible(np, "ibm,power9-npu-pciex"))
3710 phb->model = PNV_PHB_MODEL_NPU2;
3712 phb->model = PNV_PHB_MODEL_UNKNOWN;
3714 /* Initialize diagnostic data buffer */
3715 prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL);
3717 phb->diag_data_size = be32_to_cpup(prop32);
3719 phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE;
3721 phb->diag_data = memblock_alloc(phb->diag_data_size, SMP_CACHE_BYTES);
3722 if (!phb->diag_data)
3723 panic("%s: Failed to allocate %u bytes\n", __func__,
3724 phb->diag_data_size);
3726 /* Parse 32-bit and IO ranges (if any) */
3727 pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
3730 if (!of_address_to_resource(np, 0, &r)) {
3731 phb->regs_phys = r.start;
3732 phb->regs = ioremap(r.start, resource_size(&r));
3733 if (phb->regs == NULL)
3734 pr_err(" Failed to map registers !\n");
3737 /* Initialize more IODA stuff */
3738 phb->ioda.total_pe_num = 1;
3739 prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
3741 phb->ioda.total_pe_num = be32_to_cpup(prop32);
3742 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3744 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32);
3746 /* Invalidate RID to PE# mapping */
3747 for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++)
3748 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE;
3750 /* Parse 64-bit MMIO range */
3751 pnv_ioda_parse_m64_window(phb);
3753 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
3754 /* FW Has already off top 64k of M32 space (MSI space) */
3755 phb->ioda.m32_size += 0x10000;
3757 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num;
3758 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
3759 phb->ioda.io_size = hose->pci_io_size;
3760 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num;
3761 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3763 /* Calculate how many 32-bit TCE segments we have */
3764 phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3765 PNV_IODA1_DMA32_SEGSIZE;
3767 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3768 size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8,
3769 sizeof(unsigned long));
3771 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]);
3773 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]);
3774 if (phb->type == PNV_PHB_IODA1) {
3776 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]);
3777 dma32map_off = size;
3778 size += phb->ioda.dma32_count *
3779 sizeof(phb->ioda.dma32_segmap[0]);
3782 size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe);
3783 aux = memblock_alloc(size, SMP_CACHE_BYTES);
3785 panic("%s: Failed to allocate %lu bytes\n", __func__, size);
3786 phb->ioda.pe_alloc = aux;
3787 phb->ioda.m64_segmap = aux + m64map_off;
3788 phb->ioda.m32_segmap = aux + m32map_off;
3789 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) {
3790 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE;
3791 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE;
3793 if (phb->type == PNV_PHB_IODA1) {
3794 phb->ioda.io_segmap = aux + iomap_off;
3795 for (segno = 0; segno < phb->ioda.total_pe_num; segno++)
3796 phb->ioda.io_segmap[segno] = IODA_INVALID_PE;
3798 phb->ioda.dma32_segmap = aux + dma32map_off;
3799 for (segno = 0; segno < phb->ioda.dma32_count; segno++)
3800 phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE;
3802 phb->ioda.pe_array = aux + pemap_off;
3805 * Choose PE number for root bus, which shouldn't have
3806 * M64 resources consumed by its child devices. To pick
3807 * the PE number adjacent to the reserved one if possible.
3809 pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx);
3810 if (phb->ioda.reserved_pe_idx == 0) {
3811 phb->ioda.root_pe_idx = 1;
3812 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3813 } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) {
3814 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1;
3815 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3817 phb->ioda.root_pe_idx = IODA_INVALID_PE;
3820 INIT_LIST_HEAD(&phb->ioda.pe_list);
3821 mutex_init(&phb->ioda.pe_list_mutex);
3823 /* Calculate how many 32-bit TCE segments we have */
3824 phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3825 PNV_IODA1_DMA32_SEGSIZE;
3827 #if 0 /* We should really do that ... */
3828 rc = opal_pci_set_phb_mem_window(opal->phb_id,
3831 starting_real_address,
3832 starting_pci_address,
3836 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3837 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx,
3838 phb->ioda.m32_size, phb->ioda.m32_segsize);
3839 if (phb->ioda.m64_size)
3840 pr_info(" M64: 0x%lx [segment=0x%lx]\n",
3841 phb->ioda.m64_size, phb->ioda.m64_segsize);
3842 if (phb->ioda.io_size)
3843 pr_info(" IO: 0x%x [segment=0x%x]\n",
3844 phb->ioda.io_size, phb->ioda.io_segsize);
3847 phb->hose->ops = &pnv_pci_ops;
3848 phb->get_pe_state = pnv_ioda_get_pe_state;
3849 phb->freeze_pe = pnv_ioda_freeze_pe;
3850 phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
3852 /* Setup MSI support */
3853 pnv_pci_init_ioda_msis(phb);
3856 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3857 * to let the PCI core do resource assignment. It's supposed
3858 * that the PCI core will do correct I/O and MMIO alignment
3859 * for the P2P bridge bars so that each PCI bus (excluding
3860 * the child P2P bridges) can form individual PE.
3862 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
3864 switch (phb->type) {
3865 case PNV_PHB_NPU_NVLINK:
3866 hose->controller_ops = pnv_npu_ioda_controller_ops;
3868 case PNV_PHB_NPU_OCAPI:
3869 hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops;
3872 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
3873 hose->controller_ops = pnv_pci_ioda_controller_ops;
3876 ppc_md.pcibios_default_alignment = pnv_pci_default_alignment;
3878 #ifdef CONFIG_PCI_IOV
3879 ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources;
3880 ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
3881 ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable;
3882 ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable;
3885 pci_add_flags(PCI_REASSIGN_ALL_RSRC);
3887 /* Reset IODA tables to a clean state */
3888 rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
3890 pr_warn(" OPAL Error %ld performing IODA table reset !\n", rc);
3893 * If we're running in kdump kernel, the previous kernel never
3894 * shutdown PCI devices correctly. We already got IODA table
3895 * cleaned out. So we have to issue PHB reset to stop all PCI
3896 * transactions from previous kernel. The ppc_pci_reset_phbs
3897 * kernel parameter will force this reset too. Additionally,
3898 * if the IODA reset above failed then use a bigger hammer.
3899 * This can happen if we get a PHB fatal error in very early
3902 if (is_kdump_kernel() || pci_reset_phbs || rc) {
3903 pr_info(" Issue PHB reset ...\n");
3904 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
3905 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
3908 /* Remove M64 resource if we can't configure it successfully */
3909 if (!phb->init_m64 || phb->init_m64(phb))
3910 hose->mem_resources[1].flags = 0;
3913 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
3915 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
3918 void __init pnv_pci_init_npu_phb(struct device_node *np)
3920 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_NVLINK);
3923 void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np)
3925 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI);
3928 static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev)
3930 struct pci_controller *hose = pci_bus_to_host(dev->bus);
3931 struct pnv_phb *phb = hose->private_data;
3933 if (!machine_is(powernv))
3936 if (phb->type == PNV_PHB_NPU_OCAPI)
3937 dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
3939 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup);
3941 void __init pnv_pci_init_ioda_hub(struct device_node *np)
3943 struct device_node *phbn;
3944 const __be64 *prop64;
3947 pr_info("Probing IODA IO-Hub %pOF\n", np);
3949 prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
3951 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
3954 hub_id = be64_to_cpup(prop64);
3955 pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
3957 /* Count child PHBs */
3958 for_each_child_of_node(np, phbn) {
3959 /* Look for IODA1 PHBs */
3960 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
3961 pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);